JPS5919377B2 - digital output device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital output device in a process input/output device.

FIG. 1 is a circuit diagram showing a conventional digital output device.

1 in FIG. 1 is a register selection circuit, and 2a
, 2b are registers for holding output data. The registers 2a and 2b are configured to hold data to be output to the output circuits 3a and 3b through a 1-byte data line 100 (consisting of 8 lines). and,
Selects output data held in registers 2a and 2b from register selection circuit 1 through selection line 200,
The selected output data is sent to output circuits 3a and 3b. Send to output circuits 3a and 3b. The 1-byte output data is output from the output circuits 3a and 3b to an output point such as a switch in a bit-by-bit manner. As a result, the operations of switches and the like are controlled for each bit of the contents held in the registers 2a and 2b. Note that the lines La and Lb between the registers 2a and 2b and the output circuits 3a and 3b are each composed of eight lines. In such a conventional digital output device, register 2
The data held in a and 2b is output in units of 1 byte (or 2 bytes). Therefore, in order to change only the bit data corresponding to an arbitrary output point among the 8-bit output data stored in register 2a or 2b, it is necessary to change the data stored in register 2a or 2b. Store data in software,
Software is required to convert data into data that changes only arbitrary output points. However, in order to change only an arbitrary output point, the software processing becomes complicated. This invention was developed in consideration of the above points, and by providing each output point with a mask function, it is possible to change only an arbitrary output point without having to memorize it using software, and it is expected to simplify software processing. The purpose of the present invention is to provide a digital output device that can perform the following functions.

Embodiments of the digital output device of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment thereof. In FIG. 2, numeral 11 is a decoding circuit for register selection. The input end of the decode circuit 11 is connected to n lines, and the output end thereof sends a decode signal BA to gates 12a and 12b through lines Tla and tlb. Each gate 12a, 12b is composed of eight AND gates, and a decode signal BA is commonly input to all the AND gates. In addition, a register (hereinafter abbreviated as REG) 13 for holding mask data is connected from the output end of the decoding circuit 11 to a line TlO.
A signal 300 is sent out. This signal 300 is an enable signal when inputting mask data to REG13. In the software, mask data representing an arbitrary output point to be changed is first output to REGl3 via the data line 110 by a write (WRITE) command, and then to REGl4a for holding predetermined output data via the data line 110. or 14b・
...outputs data considering only the data at the output point using a write command. REG for holding the above output data
l4a, l4b... each have 8 flips. This is a register consisting of a flop. The above REGl3 and output data holding REGl4a, l4b...
A data line 110 is connected.

This data line 110 is composed of 8 lines and transmits 1 byte of data. The output end of REGl3 is connected to gates 12a and 1 through lines T2a and 2t2b.
A mask signal 400 is sent to the terminal 2b.
This 8-bit mask signal 400 is applied to the gates 12a and 12.
They are supplied in one-to-one correspondence to the eight AND gates forming the gate b. The three output ends of gates 12a and 12b are connected to REG14 for holding output data through lines T3a and t3b.
A clock signal 500 is sent to the terminals a and l4b. Each of the lines T2a, t2b, t3a, and t3b is composed of eight lines. And gate 1
2a and 12b are 3 lines from the decoding circuit 11 to the line Tl.
The decode signal BA (signal for inputting data on the data line 110) introduced through a and tlb is input to REGl.
3 through lines T2a and t2b to convert the data input enable 4 signal into the above-mentioned clock signal 500. The output terminals of the output data holding REGs 14a and 14b are connected to data output circuits 15a and 15b through eight lines, respectively. next,
The operation of the digital output device of the present invention configured as above will be explained.

Now, assume that only an arbitrary bit of the data output circuit 15a or 15b is changed to change the output signal to the corresponding output point (hereinafter referred to as point A for convenience). That is, only the output signal to point A is changed without affecting the state of the output signal to output points other than point A.
In this case, first, the address indicating REGl3 is output to the decoding circuit 11, and the mask data indicated by (the output change of) point A is output to the data line 110. Then, the signal 300 is sent from the decoding circuit 11 to the mask data holding REG13 through the line TlO, and this signal 30
0, mask data indicating the point A on the data line 110 is held in REG13. Next, REGs (REGl4a, l4b...
, and in the following explanation it is assumed to be REGl4a) is sent to the decoding circuit 11.
Further, when data considering only point A is output to the data line 110, a decode signal BA is sent from the decode circuit 11 to the gate 12a (provided corresponding to REGl4a) via the line Tla. This results in
In the eight AND gates forming the gate 12a,
An AND condition is taken between the mask data held in REG13 and the decode signal BA. However, R.E.
Gl4af) bit data at point A (REGl4af) from the AND gate of the gate 12a corresponding to the flip-flop holding the data via line T3a); A clock signal 500 is output to the flop. This allows REGl4af)A
Flip corresponding to the bit of the point. Bit data corresponding to point A in the data on data line 110 (taking only point A into account) is held in the flop, and the data is output to data output circuit 15a. As is clear, R.E.
Flips corresponding to bits other than point A in Gl4a. The state of the flop does not change. Therefore, according to this embodiment, the flip. Only the content held on the flop can be changed. Note that in normal data output, REG14a (or RE
Since the clock signal 500 can be supplied to all eight flip-flops constituting Gl4b...),
Conventional operation can be performed. As described above, according to the digital device of the present invention, when it is desired to change any output point of any output data holding register, the data in bytes that are being output at that time can be changed by software. It is possible to change only an arbitrary output point without memorizing it, and therefore software processing can be simplified.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional digital output device, Figure 2 is a block diagram of a conventional digital output device.
The figure is a block diagram of an embodiment of the digital output device of the present invention. 11... Decode circuit, 12a, 12b... Gate, 13... Mask data holding register (REG),
14a, 14b...Register for holding output data (RE
G), 15a, 15b... data output circuit.

Claims (1)

[Claims] 1. A mask register that stores mask data, a plurality of output data holding registers that store output data, a common data line that outputs data to this output data holding register and the mask register, and a register address that is decoded. The circuit includes a decoding circuit, and a plurality of gates that take logic conditions for a signal specifying each of the output data holding registers outputted from the decoding circuit and mask data from the mask register, and specified by the output signal of the gate. A digital output device characterized in that bit data corresponding to the output data is stored in a specified bit position of the output data holding register in which only the bit position is considered.