JPS5919495B2 - Shock noise prevention circuit - Google Patents
Shock noise prevention circuitInfo
- Publication number
- JPS5919495B2 JPS5919495B2 JP52141824A JP14182477A JPS5919495B2 JP S5919495 B2 JPS5919495 B2 JP S5919495B2 JP 52141824 A JP52141824 A JP 52141824A JP 14182477 A JP14182477 A JP 14182477A JP S5919495 B2 JPS5919495 B2 JP S5919495B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- turned
- shock noise
- power
- receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Noise Elimination (AREA)
Description
【発明の詳細な説明】
本発明は、難訓時の急激な信号レベルの変動や電源のオ
ン、オフ時の急激な電圧変動によつて生じるショックノ
イズを防止する回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that prevents shock noise caused by sudden signal level fluctuations during difficult training or sudden voltage fluctuations when the power is turned on and off.
一般の受信機や増幅器に於いては、電源のオン、オフに
よる急激な電圧変化によつてショックノイズが発生する
場合がある。In general receivers and amplifiers, shock noise may occur due to sudden voltage changes caused by turning the power on or off.
例えばバイアス帰還型の直結増幅器に於いて、電源電圧
が所定の値から或る値に低下或は零から或る値に上昇し
たとき、前段のトランジスタが急にオフからオンになつ
て次段の直結トランジスタがそれによりオフからオンに
なつたりするので、無信号状態であるにも拘らず恰も大
きな信号が加えられたかのように動作し、ショックノイ
ズとして出力されることになる。又FM受信機に於いて
、同調状態から難訓したとき、周波数弁別回路の出力が
急激に変化するので、その変化がショックノイズとして
増幅されることになる。本発明は、前述の如きショック
ノイズが出力されることを防止することを目的とするも
のである。For example, in a bias feedback direct-coupled amplifier, when the power supply voltage drops from a predetermined value to a certain value or rises from zero to a certain value, the transistor in the previous stage suddenly turns from off to on, and the transistor in the next stage suddenly turns on. This causes the direct-coupled transistor to turn from off to on, so it operates as if a large signal had been applied even though there is no signal, and it is output as shock noise. Furthermore, in an FM receiver, when the receiver goes out of tune, the output of the frequency discrimination circuit changes rapidly, and this change is amplified as shock noise. An object of the present invention is to prevent the above-mentioned shock noise from being output.
以下実施例について詳細に説明する。第1図は本発明の
実施例の要部回路図であり、ANTはアンテナ、RFA
は高周波増幅器、MIXは周波数変換器、OSCは局部
発振器、IFAは中間周波増幅器、DETは周波数弁別
器等の検波器、AFAは音声周波増幅器、PAは電力増
幅器、SPはスピーカであつて、これらは周知の受信機
の構成を示すものである。Examples will be described in detail below. FIG. 1 is a circuit diagram of a main part of an embodiment of the present invention, where ANT is an antenna, RFA
is a high frequency amplifier, MIX is a frequency converter, OSC is a local oscillator, IFA is an intermediate frequency amplifier, DET is a detector such as a frequency discriminator, AFA is an audio frequency amplifier, PA is a power amplifier, and SP is a speaker. shows the configuration of a well-known receiver.
又CCは制御回路、PWは電源回路、Q1〜Q4はトラ
ンジスタ、R1〜R12は抵抗、C1〜C5はコンデン
サ、D1〜D4はダイオード、SWI、SW2はスイッ
チ、Tは電源トランスである。スイッチSWI、SW2
は端子a−c、d−f及び可動接点g、れを有し、且つ
連動して動作するものであり、受信機が動作中は可動接
点gが端子eに接触し、又可動端子れが端子cに接触し
、・商用電源からトランスTにより降圧されて、ダイオ
ードD3、D4により整流され、定電圧ダイオードD2
によりトランジスタQ4のベース電位が一定になるよう
にして直流電圧の安定化が図られ、このトランジスタQ
4の出力の直流電圧が各部の電源電圧として供給される
。Also, CC is a control circuit, PW is a power supply circuit, Q1 to Q4 are transistors, R1 to R12 are resistors, C1 to C5 are capacitors, D1 to D4 are diodes, SWI and SW2 are switches, and T is a power transformer. Switch SWI, SW2
has terminals a-c, d-f and a movable contact g, which operate in conjunction with each other, and when the receiver is in operation, the movable contact g contacts the terminal e, and the movable terminal contacts the terminal e. Contacts terminal c, voltage is stepped down from the commercial power supply by transformer T, rectified by diodes D3 and D4, and voltage regulator diode D2
This stabilizes the DC voltage by keeping the base potential of the transistor Q4 constant.
The DC voltage output from No. 4 is supplied as a power supply voltage to each part.
定常状態に於いてはNPNトランジスタQ1はオフ状態
となるように、そのバイアスが選定されているもので、
従つてトランジスタQ2、Q3もオフ状態となつている
。The bias is selected so that the NPN transistor Q1 is in an off state in a steady state.
Therefore, transistors Q2 and Q3 are also in an off state.
従つて制御回路CCは受信状態には何ら影響を及ぼさな
い。同調状態からダイヤル操作等により離調させると、
周波数弁別器DETの出力信号レベルが急激に変化し、
この変化成分がコンデンサC1を介してトランジスタQ
1のベースに加えられ、トランジスタQ1はオフからオ
ンになる。Therefore, the control circuit CC has no influence on the reception state. If you detune it from the tuned state by dial operation etc.,
The output signal level of the frequency discriminator DET changes suddenly,
This change component passes through the capacitor C1 to the transistor Q.
1 and turns transistor Q1 from off to on.
即ち検波出力レベルの急激な変化を検出することになる
。このトランジスタQ1のオンによりそのコレクタ電位
が低下し、そのコレクタにベースが接続されたPNPト
ランジスタQ2はベース電流が流れることによりオンと
なり、そのトランジスタQ2のコレクタ電位が上昇する
。それによつてこのトランジスタQ2のコレクタに抵抗
RlO、ダイオードD1を介してベースが接続されたト
ランジスタQ3はオフからオンとなり、電力増幅器PA
の入力が側路手段としてのトランジスタQ3によつて接
地される。従つて音声周波増幅器AFA以降の段の電力
増幅器、スピーカSP等には信号が伝達されないので、
離調時に生じるシヨツクノイズはスピーカSPから出力
されないものとなる。That is, a sudden change in the detection output level is detected. When the transistor Q1 is turned on, its collector potential decreases, and the PNP transistor Q2 whose base is connected to its collector is turned on as a base current flows, and the collector potential of the transistor Q2 rises. As a result, the transistor Q3 whose base is connected to the collector of the transistor Q2 via the resistor RlO and the diode D1 is turned on from off, and the power amplifier PA
The input of is grounded by transistor Q3 as a bypass means. Therefore, the signal is not transmitted to the power amplifier, speaker SP, etc. in the stage after the audio frequency amplifier AFA.
The shock noise that occurs during detuning is not output from the speaker SP.
第2図はスイツチSWl,SW2の一例の構成説明図で
あり、可動接点G,hが図示の実線位置の場合には電源
オフの状態であつて、可動接点hが端子A,b間に接触
しているので、トランジスタQ2のベースは抵抗R6を
介して接地されている状態となる。FIG. 2 is an explanatory diagram of the configuration of an example of switches SWl and SW2. When movable contacts G and h are in the solid line positions shown in the figure, the power is off, and movable contact h is in contact between terminals A and b. Therefore, the base of transistor Q2 is grounded via resistor R6.
可動接点G,hを点線位置に移動させて電源オンとする
とき、可動接点gが端子E,f間に接触した瞬間には、
未だ可動接点gは端子A,b間に接触しており、従つて
電源回路PWの出力電圧が立上る過程に於いては、トラ
ンジスタQ2のベースが抵抗R6を介して接地され、ト
ランジスタQ2,Q3はオンとなるので、電力増幅器P
Aの入力はトランジスタQ3により接地されることにな
る。そして可動接点gがほぼ完全に端子E,fに接触し
た状態となると、可動接点hは端子aから離れるので、
トランジスタQ2はオフ状態となり、トランジスタQ3
もオフとなる。When movable contacts G and h are moved to the dotted line position to turn on the power, the moment movable contact g comes into contact between terminals E and f,
The movable contact g is still in contact between terminals A and b, and therefore, in the process of rising the output voltage of power supply circuit PW, the base of transistor Q2 is grounded via resistor R6, and transistors Q2 and Q3 are grounded. is on, so the power amplifier P
The input of A will be grounded by transistor Q3. When the movable contact g comes into almost complete contact with the terminals E and f, the movable contact h separates from the terminal a.
Transistor Q2 is turned off and transistor Q3
is also turned off.
又電源オンからオフにするときは、前述と反対に可動接
点gが端子eから離れる前に可動接点hが端子aに接触
してトランジスタQ2をオンとし、それによつてトラン
ジスタQ3がオンとなるので、電力増幅器PAの入力が
接地される。Also, when turning the power off from on, contrary to the above, before movable contact g leaves terminal e, movable contact h contacts terminal a and turns on transistor Q2, which turns on transistor Q3. , the input of power amplifier PA is grounded.
従つて電源のオン、オフ時の電圧変動に伴なうシヨツク
ノイズは、離調時と同様にスピーカSPから出力される
ことはなくなる。以上説明したように、本発明は、周波
数弁別器等の検波器の出力レベルが同調時と離調時とに
於いて大きく変化するので、その急激な変化を検出し、
検波器DETの出力信号又はそれを増幅した音声周波増
幅器AFAの出力信号が電力増幅器やスピーカ等の後段
に伝達しないように側路手段によつて制御することによ
り同調状態から離調したときに生じるシヨツクノイズの
出力を防止することができるものである。Therefore, shock noise caused by voltage fluctuations when the power supply is turned on and off is no longer output from the speaker SP, as in the case of detuning. As explained above, the present invention detects the sudden change in the output level of a detector such as a frequency discriminator, which changes greatly between tuning and detuning, and
Occurs when the output signal of the detector DET or the output signal of the audio frequency amplifier AFA that amplifies it is detuned from the tuned state by controlling it with a bypass means so that it is not transmitted to a subsequent stage such as a power amplifier or speaker. This can prevent the output of shock noise.
又電源のオン、オフ時に生じるシヨツクノイズについて
も、電源スイツチSWlに連動するスイツチSW2を制
御回路に設け、電源スイツチSWlがオンになつた後に
オフ、電源スイツチSWlがオフになる前にオンとなる
ようにスイツチSW2を構成し、このスイツチSW2が
オンのときはトランジスタQ3等による側路手段により
信号の伝達を阻止して、不快感を与えるシヨツクノイズ
を確実に防止することができるものである。なお本発明
は前述の実施例にのみ限定されるものではなく、種々付
加変更し得るものである。Also, regarding the shock noise that occurs when the power is turned on and off, a switch SW2 that is linked to the power switch SWl is provided in the control circuit, and the switch SW2 is turned off after the power switch SWl is turned on, and turned on before the power switch SWl is turned off. The switch SW2 is configured in this way, and when the switch SW2 is on, signal transmission is blocked by bypass means such as the transistor Q3, thereby reliably preventing unpleasant shock noise. It should be noted that the present invention is not limited to the above-described embodiments, but can be modified in various ways.
第1図は本発明の実施例の要部回路図、第2図はスイツ
チの一例の構成説明図である。
ANTはアンテナ、RFAは高周波増幅器、MIXは周
波数変換器、0SCは局部発振器、IFAは中間周波増
幅器、DETは検波器、AFAは音声周波増幅器、SP
はスピーカ、CCは制御回路、PWは電源回路、Q1〜
Q4はトランジスタ、D1〜D4はダイオード、C1〜
C5はコンデンサ、R1〜Rl2は抵抗、SWl,SW
2はスイツチである。FIG. 1 is a circuit diagram of a main part of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a configuration of an example of a switch. ANT is antenna, RFA is high frequency amplifier, MIX is frequency converter, 0SC is local oscillator, IFA is intermediate frequency amplifier, DET is detector, AFA is audio frequency amplifier, SP
is the speaker, CC is the control circuit, PW is the power supply circuit, Q1~
Q4 is a transistor, D1-D4 are diodes, C1-
C5 is a capacitor, R1 to Rl2 are resistors, SWl, SW
2 is a switch.
Claims (1)
力レベルの変化を検出する検出手段、該検出手段の出力
により前記受信機の後段への信号の伝達を阻止する側路
手段とを含む制御回路を備え、電源スイッチと連動して
該電源スイッチがオンとなつた後にオフとなり、該電源
スイッチがオフとなる前にオンとなるスイッチを前記制
御回路に設け、該スイッチがオンのとき前記側路手段に
より強制的に前記信号が前記受信機の後段へ伝達される
ことを阻止する構成としたことを特徴とするショックノ
イズ防止回路。1 detection means for detecting a sudden change in the detection output level between the tuned state and the detuned state of the receiver; bypass means for blocking the transmission of the signal to the subsequent stage of the receiver by the output of the detection means; The control circuit is provided with a switch that operates in conjunction with a power switch to turn off after the power switch is turned on and turns on before the power switch is turned off, A shock noise prevention circuit characterized in that the circuit is configured to forcibly prevent the signal from being transmitted to a subsequent stage of the receiver by the bypass means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52141824A JPS5919495B2 (en) | 1977-11-26 | 1977-11-26 | Shock noise prevention circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52141824A JPS5919495B2 (en) | 1977-11-26 | 1977-11-26 | Shock noise prevention circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5474313A JPS5474313A (en) | 1979-06-14 |
| JPS5919495B2 true JPS5919495B2 (en) | 1984-05-07 |
Family
ID=15300973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52141824A Expired JPS5919495B2 (en) | 1977-11-26 | 1977-11-26 | Shock noise prevention circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5919495B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5711846U (en) * | 1980-06-25 | 1982-01-21 | ||
| FR2905593B1 (en) | 2006-09-13 | 2009-08-21 | Univ Paris Curie | UNDERWEAR FOR INCONTINENT PERSON AND TREATMENT DEVICE ASSOCIATED WITH UNDERWEAR |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5238093U (en) * | 1975-09-09 | 1977-03-17 |
-
1977
- 1977-11-26 JP JP52141824A patent/JPS5919495B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5474313A (en) | 1979-06-14 |
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