JPS5920116B2 - clock device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a timepiece device that reduces power consumption and can be effectively applied to wristwatches and the like.

2. Description of the Related Art In place of conventional analog display clocks with long and short hands, various digital display clocks that display the time using numbers have been developed.

For example, it is being considered to display numerical values on a liquid crystal in a wristwatch, thereby reducing power consumption and making the wristwatch more compact.

When this type of display device is used in a wristwatch, the battery storage capacity is limited, so a CMO8 with low power consumption is used as a driving means for the display device.

Due to the characteristics of the circuit, most of the power consumption of this CMO8 is consumed during switching, and it also has the property of increasing in proportion to the square of the power supply voltage. It is desirable to drive at a voltage as low as possible, for example 1.5V.

On the other hand, the numerical display section requires a driving voltage of at least 15 V to obtain contrast for display, and there is a large voltage difference between the driving voltages.

Therefore, a voltage conversion circuit is provided between the clock circuit and the display device, and the time data from the clock circuit is constantly supplied to the display section via the voltage conversion circuit to display the time. However, the drawback is that the voltage conversion circuit consumes a lot of power.

The present invention improves the above-mentioned drawbacks, and can reduce the power consumption of the circuit between the timekeeping circuit and the display section in a timepiece device in which the timekeeping operation is performed at a low voltage and the display operation is performed at a high voltage, for example. The present invention relates to a clock device using a liquid crystal display device.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 11 denotes a counting circuit consisting of a dynamic shift register in which a plurality of counting circuit elements are connected in series to count time in units of hours, minutes, and seconds. For example, a 1 second pulse signal from the device 12 is combined as a count signal via the timing control circuit 13 and the control circuit 14, so that a numerical value corresponding to that time is always counted and set.

The count signal from the counting circuit 11 is coupled to the AND circuit 15, and the gate of the AND circuit 15 is opened in response to a pulse every minimum unit of time display from the timing control circuit 13, for example, every minute. Make it.

Further, from the timing control circuit 13, the control clock φ for shifting of the counting circuit 11 is taken out, and is also coupled to the AND circuit 16, which is a clock signal generation circuit, together with the above-mentioned pulse signal every minute. The control clock is generated every minute.

The control clock and data are then supplied to an interface circuit 17 that converts voltage, and the output of this interface circuit 17 controls a liquid crystal driver 8 to drive a liquid crystal display device 19.

In this case, the interface circuit 17 is coupled to a holding clock that distributes and stores the supplied data for each display unit.

FIG. 2 shows the interface circuit 17 in FIG. 1 in more detail.
7 is a holding circuit 22a to 22d that holds time data displayed on the display device 19, and a field effect transistor F.
ET1. FET2゜FET and transistor FET
1, a control circuit consisting of a buffer 20 for writing data output from 1, a decoder 21 for decoding data in the buffer 20, and a digit counter 23 for storing the output of the decoder 21 in holding circuits 22a to 22d in a time-division manner. .

Field effect transistor FET15FET2. FET3
A display driving voltage of -15V is coupled through a load resistor R, and data, a control clock, and a holding clock are coupled to their respective gate electrodes.

That is, the data obtained from the transistor FET1 is written into the buffer 20 by the control clock, and the data from this buffer 20 is coupled to the decoder 21, so that each display digit 19a of the display device 19 = 19bt 19ct 1
Holding circuit 22 a e 22 b -2 corresponding to 9d
Binds to 2c-22d.

Then, data is transferred to each of the corresponding holding circuits 22a to 2 by a distribution signal from the digit counter 23 that counts the holding clock.
2d to hold the memory, and the drivers 18a, 18b, 18c
, 18d to the display device 19.

The FET 4 is a field effect transistor for an interface that couples a display drive signal to the display section.

Therefore, in the clock device configured in this way, the counting circuit 11 is configured with CMO8, and for example, 1.5V.
Since it is driven at a low voltage, the timekeeping operation consumes very little power.

Further, AND circuits 15 and 16 are provided in the control circuit for converting the voltage of the time data of the counting circuit 11 of the interface circuit 17 and writing it into the holding circuits 22a to 22d only when the minimum unit of time displayed on the display device 19 changes. Since the operation is performed by supplying the control clock and data generated from the interface circuit 170, the power consumption in the control circuit of the interface circuit 170 is minimized.

As described above, according to the present invention, the clock circuit section is configured with, for example, CMO8, which can sufficiently reduce power consumption at a low voltage, and the display section is effectively driven for display at a higher voltage.
It can be effectively configured as a wristwatch, for example, by reducing power consumption.

Furthermore, the circuit that transmits signals from the low-voltage clock circuit to the high-voltage display only operates when necessary.

Since the power consumption does not occur, the power consumption can be made very small, and the power supply section can be constructed with a sufficiently small capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a timepiece device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing, in particular, the interface section of the embodiment in detail. 11... Counting circuit, 12... Pulse generator, 13... Timing control circuit, 17
...Interface circuit, 16...Liquid crystal driver, 19...Display device, 20...
...Buffer, 23...Digit counter, FET1
~FET4... Field effect transistor.

Claims (1)

[Claims] 1. A clock circuit that counts a reference clock signal to obtain multi-digit time data, a display device that displays the multi-digit time data obtained by this clock circuit, and a multi-digit time data displayed on this display device. a plurality of holding circuits provided corresponding to the plurality of digits to hold the plurality of digits, and a display/drive circuit that constantly displays the plurality of digits of time data held by the plurality of holding circuits on the display device; time data output means for outputting the multi-digit time data obtained by the clock circuit every time the minimum unit of time data displayed on the display device changes; and a multi-digit time output from the time data output means. a decoder that sequentially decodes data in digit order; a means for outputting a distribution signal to the plurality of holding circuits for sequentially distributing and storing the multi-digit time data output from the decoder to the corresponding holding circuits; and a means for outputting the time data. voltage converting means provided between the means and the plurality of holding circuits for converting the multi-digit time data into a voltage for driving the display device, A timepiece device characterized in that the multi-digit time data of the timekeeping circuit is converted into a voltage for driving a display device and written into the plurality of holding circuits only when the minimum unit changes.