JPS5920128B2 - input/output control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an input/output control device, particularly an input/output control device that is commonly accessed from a plurality of processors, in which status information to be transferred from the input/output control device to the processor is generated. This invention relates to an input/output control device in which the input/output control device autonomously releases the pending state of the lower-level input/output device by the processor when a predetermined period of time or more has elapsed. .

Data transfer control between the processor side and input/output devices is
This is generally done through a channel and an input/output controller. The input/output control device controls data transfer and various status information related to data transfer, and notifies the processor of the status information through a channel by means of an interrupt or the like. This status information includes channel end information indicating the end of data transfer, device end information, error information during data transfer, and the like. While this status information is held in the input/output control device, the input/output control device is prevented from executing the next input/output command for the same input/output device. A problem arises when such an input/output control device is configured to be shared by multiple processors.

In other words, in this case, the input/output control device is provided with an access list f for multiple processors, and the input/output control device is time-divisionally connected to multiple processors for each input/output operation. Do the following.

Data transfer between one processor and one input/output device is generally controlled in units of multiple input/output operations, and the processor and the input/output device are logically connected. However, physically, they are connected intermittently in a time-sharing manner. If the above status information for one processor side is pending in the input/output control device, the input/output device associated with the status information will not be able to access the input/output device from the other processor side until the status information is received by the processor side. It is interlocked so that it cannot be used. For this reason, in the case of the above-mentioned shared configuration, if one processor goes down with the above status information being held in the input/output control device, the input/output device will Even if the processor is physically connected, it becomes completely unusable from the other processor side. If the other processor is an online processing system, for example, the system may go down. The present invention aims to solve the above-mentioned problems, and has an input/output control device that monitors the status pending state of each input/output device, autonomously releases the above state, and The purpose is to release the interlock state of the output device. For this purpose, the input/output control device of the present invention can be used even if the input/output control device of the present invention is not physically connected to the processor side until the status information is received by the processor side regarding data transfer between the processor side and the processor side. In an input/output control device that is configured to control an input/output device that maintains a logical connection state to a processor and has an access bus that is accessed in common from a plurality of processors, corresponding to the lower input/output device, An input/output device-compatible memory having at least information instructing which processor side is logically connected among the plurality of processor sides, and time information indicating the presence or absence of status information and the time since the status information was generated. When a predetermined time has elapsed since the occurrence of the status information to be transferred to at least the logically connected processor, the processor side transfers the input/output device to the input/output device. The feature is that the logical hold state is released autonomously. This will be explained below with reference to the drawings. FIG. 1 shows an embodiment of a data processing system to which the present invention is applied, and FIG. 2 shows the configuration of an embodiment of an input/output control device of the present invention.

In FIG. 1, 1A and 1B are processors, 2A,
2B represents a channel, 3 represents an input/output pedestal according to the present invention, and 4-0 to 4-n represent an input/output device, respectively.

As shown in FIG. 1, when an input/output control device 3 having access buses for a plurality of channels 2 controls one or more input/output devices 4, the problem described at the beginning of this specification occurs. .

That is, for example, the input/output device 40 that has just transferred data with the processor 1B through access from the processor 1B.
If the processor 1B side goes down while the status information related to the data transfer is held in the input/output control device, the input/output device 410 can be transferred to another processor 1B.
It becomes unusable from side A. In order to solve this problem, in the case of the present invention, the input/output control device 3 monitors the occurrence of this state and releases the undesired holding state of the input/output device 4-0.

FIG. 2 shows the configuration of an embodiment of the input/output control device 3. As shown in FIG.

Reference numeral 3 in the figure is an input/output control device, 4A and 4B are drivers/receivers, respectively, and channels 2A and 2B shown in FIG.
5 is a bus selection circuit section that selects a bus with one of the channels for each input/output operation, and 6 is an interface control section that is provided from the processor side. 7 is a read/write control unit; 8 is a bus selection control unit; 9-0 to 9-n are memory units corresponding to input/output devices; 10 is status information, 11 is connection compatible channel information, which indicates which channel is operating in response to a command, and 12 is time information, which is the time since the status information was generated. represents what is measured and set. In the illustrated case, for example, when a start 10 command from channel 2B is received, the interface control unit 6 performs control corresponding to the command,
When data is transferred between the input/output device 4-0 and the processor 1B in response to the command, and the input/output device 4-0 is in an empty state, the data is transferred via the read/write control unit 7. Data transfer is performed between the processor 1B side and the input/output device 4-0.

At this time, "channel 2BJ" is set as the connection corresponding channel information in the illustrated input/output device correspondence storage section 9-0.
During this time, the input/output control device 3 accepts start 10 commands for other input/output devices from the processor 1A or 1B side, depending on the availability of data transfer.
Processing corresponding to a command that has already been accepted is being performed.
In this state, when the data transfer between the processor 1B side and the input/output device 4-0 is completed or an error occurs in the data transfer, the above-mentioned status is generated. At this point, "present" is set as the status presence/absence information 10 on the storage unit 9-0 corresponding to the input/output device 4-0, and the subsequent time is set as the time information 12. The time report is updated over time until the status information is received by the processor 1B. The bus selection control section 8 constantly scans the storage sections 9-0 to 9-n corresponding to each input/output device.
When the time information 12 on -0 detects that a predetermined time (for example, one minute) has elapsed, the input/output device 4-0 is forcibly set to an idle state.

That is, the state in which the connection from the processor 1B side to the input/output device 4-0 is maintained is released. For example, when a new command is received for the input/output device 4-0, the status information held until then, that is, the processor 1B
The status information that should be reported for is disabled. Note that the invalidation processing mode is not limited to the above. As described above, according to the present invention, the input/output control device 3 autonomously monitors the occurrence of the undesired connection holding state and releases it.

For this reason, as mentioned above, for example, the input/output device 4-0 is not left unusable.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a data processing system to which the present invention is applied, and FIG. 2 shows the configuration of an embodiment of an input/output control device of the present invention. In the figure, 1 is a processor, 2 is a channel, 3 is an input/output control device, 4 is an input/output device, 5 is a bus selection circuit section, 6 is an interface control section, 7 is a read/write control section, and 8 is a bus selection section. The control section 9 represents an input/output device corresponding storage section.

Claims (1)

[Claims] 1 Input/output that maintains a logical connection state to the processor even if it is not physically connected to the processor until status information regarding data transfer to and from the processor is received by the processor. In an input/output control device that is configured to control a device and has an access bus that is commonly accessed by multiple processors, the logically connected state of the multiple processors corresponds to the lower input/output device. an input/output device corresponding storage unit having at least information instructing the processor side, the presence or absence of status information, and time information representing the time since the status information has been generated, and at least the above-mentioned logically connected state. When a predetermined time elapses from the generation of status information to be transferred to a certain processor, the logical holding state of the input/output device by the processor is autonomously released. An input/output control device characterized by: