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JPS5921073B2 - Multiplication/division circuit - Google Patents
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JPS5921073B2 - Multiplication/division circuit - Google Patents

Multiplication/division circuit

Info

Publication number
JPS5921073B2
JPS5921073B2 JP2239376A JP2239376A JPS5921073B2 JP S5921073 B2 JPS5921073 B2 JP S5921073B2 JP 2239376 A JP2239376 A JP 2239376A JP 2239376 A JP2239376 A JP 2239376A JP S5921073 B2 JPS5921073 B2 JP S5921073B2
Authority
JP
Japan
Prior art keywords
signal
transistor
resistor
supplied
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2239376A
Other languages
Japanese (ja)
Other versions
JPS52105747A (en
Inventor
弘司 市ケ谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2239376A priority Critical patent/JPS5921073B2/en
Publication of JPS52105747A publication Critical patent/JPS52105747A/en
Publication of JPS5921073B2 publication Critical patent/JPS5921073B2/en
Expired legal-status Critical Current

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  • Amplifiers (AREA)
  • Electrophonic Musical Instruments (AREA)

Description

【発明の詳細な説明】 本発明は、3つの信号■1 、■2及び■3があ3 るとき、−■1で表わされるような出力信号が■2 得られる乗除算回路に関し、特にきわめて簡単な構成に
より目的とする信号を容易に得ることができるようにし
たものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplication/division circuit that can obtain an output signal as represented by -■1 when there are three signals ■1, ■2, and ■3, and particularly, A target signal can be easily obtained with a simple configuration.

以下、本発明による乗除算回路を、図を参照して説明し
よう。
Hereinafter, a multiplication/division circuit according to the present invention will be explained with reference to the drawings.

第1図はその一例で、第1の抵抗R1と第1の電界効果
トランジスタ1のドレイン−ソースが直列に接続され、
その直列回路の両端間に正の第1の信号■1が供給され
る。
FIG. 1 is an example of this, in which the first resistor R1 and the drain-source of the first field effect transistor 1 are connected in series,
A positive first signal (1) is supplied across the series circuit.

また、第2の抵抗R2と第2の電界効果トランジスタ2
のドレイン−ソースが直列に接続され、その直列回路の
両端間に正の第2の信号V2が供給される。
In addition, the second resistor R2 and the second field effect transistor 2
are connected in series, and a positive second signal V2 is supplied across the series circuit.

さらに比較増巾器3が設けられ、その一側入力端に正の
第3の信号V3が供給され、その+側入力端に第2の抵
抗R2と第2の電界効果トランジスタ2の接続点、即ち
第2の電界効果トランジスタ2のドレインに得られる信
号が供給され、一方、第1及び第2の電界効果トランジ
スタ1及び2のゲート間に抵抗R3及びR4が直列に接
続され、比較増巾器3の出力信号がこれら抵抗R3及び
R4の接続点に供給される。
Furthermore, a comparison amplifier 3 is provided, one input end of which is supplied with a positive third signal V3, and a connection point between the second resistor R2 and the second field effect transistor 2 at its + side input end; That is, the obtained signal is supplied to the drain of the second field effect transistor 2, while resistors R3 and R4 are connected in series between the gates of the first and second field effect transistors 1 and 2, and a comparator amplifier is connected. 3 output signals are supplied to the connection point of these resistors R3 and R4.

ただし、■2〉■3である必要がある。この場合、第1
及び第2の抵抗R1及びR2の値は互にほぼ等しくされ
る。
However, it is necessary that ■2>■3. In this case, the first
The values of the second resistors R1 and R2 are approximately equal to each other.

また、第1及び第2の電界効果トランジスタ1及び2は
、Nチャンネルの接合型の場合で、両者はゲート電圧対
ドレイン−ソース間抵抗の特性がほぼ等しいものが用い
られる。
Further, the first and second field effect transistors 1 and 2 are of N-channel junction type, and both have substantially the same characteristics of gate voltage versus drain-source resistance.

そして第1の抵抗R1と第1の電界効果トランジスタ1
の接続点、即ち第1の電界効果トランジスタ1のドレイ
ンより出力信号V。
and a first resistor R1 and a first field effect transistor 1
The output signal V is output from the connection point of , that is, the drain of the first field effect transistor 1 .

が取出される。is taken out.

この回路でトランジスタ1,2のドレイン−ソース間抵
抗をそれぞれrllr2とすれば、トランジスタ1,2
のドレインに得られる信号V。
In this circuit, if the drain-source resistances of transistors 1 and 2 are rllr2, then transistors 1 and 2
The signal V obtained at the drain of.

。■いは、それぞれ、 で表わされる。. ■Yes, each It is expressed as

そして、このトランジスタ2のドレインに得られる信号
vAが第3の信号V3より小さいときは、比較増巾器3
の出力電圧vBは負になって、トランジスタ2のドレイ
ン−ソース間抵抗r2を大きくして信号vAを犬きくす
るように働き、逆に信号■いが第3の信号■3より大き
いときは、比較増巾器3の出力電圧VBは正になって、
トランジスタ2のドレイン−ソース間抵抗r2を小さく
して信号Vカを小さくするように働くので、結局信号V
Aは第3の信号■3に追従してこれと等しくなる。
When the signal vA obtained at the drain of this transistor 2 is smaller than the third signal V3, the comparison amplifier 3
The output voltage vB of becomes negative and works to increase the drain-source resistance r2 of the transistor 2 to make the signal vA stronger. Conversely, when the signal I is larger than the third signal I3, The output voltage VB of the comparison amplifier 3 becomes positive,
Since it works to reduce the resistance r2 between the drain and source of the transistor 2 and reduce the signal V force, the signal V
A follows the third signal 3 and becomes equal to it.

従って、 から となる。Therefore, from becomes.

そしてトランジスタ1及び2のゲート電圧対ドレイン−
ソース間抵抗の特性はほぼ等しく、トランジスタ1及び
2のゲート電圧は等しいから、となる。
and the gate voltage of transistors 1 and 2 vs. drain -
Since the characteristics of the source-to-source resistances are approximately equal and the gate voltages of transistors 1 and 2 are equal, the following equation is obtained.

よって、(5)式と(1)式とから、出力信号■。Therefore, from equations (5) and (1), the output signal ■.

は、となり、R1=R2であるから、 となる。is, and since R1=R2, becomes.

即ち、出力信号V。That is, the output signal V.

は、第1の信号■1を第2の信号■2で除し、それに第
3の信号■3を乗じたものとなる。
is obtained by dividing the first signal (1) by the second signal (2) and multiplying it by the third signal (2).

上述の乗除算回路を用いれば、電子楽器において、鍵盤
などの操作の際一定のエンベロープをもって音量を制御
し、かつ同時に音量ビブラートをかける場合、これを容
易に行うことができる。
By using the multiplication/division circuit described above, it is possible to easily control the volume of an electronic musical instrument using a constant envelope when operating a keyboard, etc., and apply volume vibrato at the same time.

即ち、上述の第1の信号■1 として、シンセサイザー
などから得られる、図のように一定の音色を呈する波形
が選択された音階に応じた周波数で連続的に繰返すもの
を供給し、第2の信号V2として、選択された音階に応
じた周期(第1の信号■1のそれより大きい)の正弦波
状のものを供給し、第3の信号v3として、高音の場合
には立上りが急で、低音の場合にはゆるやかになるよう
なエンベロープ波形を供給すれば、第2図に示すように
、出力信号V。
That is, as the above-mentioned first signal (1), a waveform obtained from a synthesizer or the like that exhibits a certain timbre as shown in the figure is supplied that is continuously repeated at a frequency corresponding to the selected scale, and the second signal As the signal V2, a sine wave with a period corresponding to the selected scale (larger than that of the first signal 1) is supplied, and as the third signal v3, the rise is steep in the case of high notes, If we supply an envelope waveform that is gentle for bass sounds, the output signal V will be generated as shown in Figure 2.

とじては、信号V1の振幅がさ)で変調されたものが得
られ、これをスピーカ2 に供給するときは、音量が漸次増大し、しかもビブラー
トがかかるようになる。
In the end, the amplitude of the signal V1 is modulated by 1), and when this is supplied to the speaker 2, the volume gradually increases and vibrato is applied.

上述の本発明による乗除算回路によれば、僅かのトラン
ジスタと抵抗により乗除算の演算を行なわすことができ
る。
According to the multiplication/division circuit according to the present invention described above, multiplication/division operations can be performed using only a few transistors and resistors.

なお、トランジスタとしては電界効果トランジスタに限
らず、バイポーラトランジスタを用いることもできる。
Note that the transistor is not limited to a field effect transistor, and a bipolar transistor can also be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による乗除算回路の一列の接続図、第2
図はその説明のだめの波形図である。 Ro及びR2は第1及び第2の抵抗、1及び2は第1及
び第2のトランジスタ、3は比較増巾器である。
FIG. 1 is a connection diagram of one row of multiplication/division circuits according to the present invention, and FIG.
The figure is a waveform diagram for illustration purposes only. Ro and R2 are first and second resistors, 1 and 2 are first and second transistors, and 3 is a comparison amplifier.

Claims (1)

【特許請求の範囲】 1 第1の抵抗と第1のトランジスタが直列に接続され
、その直列回路の両端間に第1の信号V1が供給され、
上記第1の抵抗と抵抗値がほぼ等しい第2の抵抗と第2
のトランジスタが直列に接続され、その直列回路の両端
間に第2の信号■2が供給され、上記第2の抵抗と上記
第2のトランジスタの接続点に得られる電圧が第3の信
号■3と比較され、その比較誤差信号が上記第1及び第
2のトランジスタの制御電極に供給されて、上記接続点
に得られる電圧が上記第3の信号■3と等しくなるよう
に上記第1及び第2のトランジスタの電流通路の抵抗が
制御され、上記第1の抵抗及び■3 上記第1のトランジスタの接続点よ!?−V、で■2 表わされる信号が得られるようにされた乗除算回路。
[Claims] 1. A first resistor and a first transistor are connected in series, and a first signal V1 is supplied between both ends of the series circuit,
a second resistor whose resistance value is approximately equal to that of the first resistor;
transistors are connected in series, a second signal (2) is supplied across the series circuit, and the voltage obtained at the connection point of the second resistor and the second transistor is a third signal (3). The comparison error signal is supplied to the control electrodes of the first and second transistors so that the voltage obtained at the connection point is equal to the third signal (3). The resistance of the current path of the transistor No. 2 is controlled, and the connection point of the first resistor and the first transistor No. 3 is controlled! ? A multiplication/division circuit configured to obtain a signal represented by -V, 2.
JP2239376A 1976-03-02 1976-03-02 Multiplication/division circuit Expired JPS5921073B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2239376A JPS5921073B2 (en) 1976-03-02 1976-03-02 Multiplication/division circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2239376A JPS5921073B2 (en) 1976-03-02 1976-03-02 Multiplication/division circuit

Publications (2)

Publication Number Publication Date
JPS52105747A JPS52105747A (en) 1977-09-05
JPS5921073B2 true JPS5921073B2 (en) 1984-05-17

Family

ID=12081406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2239376A Expired JPS5921073B2 (en) 1976-03-02 1976-03-02 Multiplication/division circuit

Country Status (1)

Country Link
JP (1) JPS5921073B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5616240A (en) * 1979-07-19 1981-02-17 Ricoh Co Ltd Analog multiplier

Also Published As

Publication number Publication date
JPS52105747A (en) 1977-09-05

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