JPS5921191B2 - Method for manufacturing field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate type semiconductor device having a metal-insulating film-semiconductor structure, a so-called MIS type field effect semiconductor device.

Generally, when a MIS type transistor is used as a switching element, one of the major factors that determines its speed is the capacitance Cdg generated due to the overlap between the gate electrode and the drain diffusion layer.

In order to reduce this capacitance while increasing integration, and to realize short channel devices through easy mask alignment, self-alignment technology has been developed that uses the gate electrode as a diffusion mask. Since the distance is about 0.8 times the vertical diffusion distance, it is difficult to suppress Cdg below a certain level. Further, since the diffusion process is a high temperature and long time process, it causes distortion in the crystal, which causes problems in terms of yield, reliability, noise, etc. Furthermore, there are a limited number of semiconductor materials from which source and drain regions can be easily formed by diffusion. Therefore, considering that speeds and integration will continue to increase in the future, no significant progress will be seen in the conventional method of using diffusion to form sources and drains. The purpose of the present invention is to eliminate the need for a diffusion process, and therefore to easily increase speed and integration, and to perform all processes at low temperatures, thereby easily increasing the yield and reliability of devices. It is an object of the present invention to provide a method for manufacturing a MIS type field effect semiconductor device that can be manufactured.

In the method for manufacturing a field effect semiconductor device of the present invention, when forming an MIS field effect transistor on a semiconductor substrate of one conductivity type, the end portion of the gate electrode is anodized using the resist layer used for patterning the gate portion as a mask. then depositing a material on the substrate in rectifying contact with the substrate, and patterning the layer of material by removing the resist layer to form a source or drain of the layer of material. This feature is described in detail below. The present invention does not use a diffusion layer for the source or drain, but preferably uses a metal that has a small barrier potential difference with the semiconductor of the channel region and a large barrier potential difference with the semiconductor of the substrate to form a Schottky contact with the source or drain. , and this electrode is deposited in a self-aligned arrangement with the gate electrode.

Since the Schottky contact used in the present invention is intended to construct a high-speed operation n-channel FET, the work function difference with the n-type semiconductor is small, and the work function difference with the p-type semiconductor or larger. or is necessary. In the case of an n-type channel using a silicon substrate, zirconium, titanium, indium, etc. are suitable for the source/drain electrodes.

That is, their work function is 4 eV, which is the value of n-type Si.
I. Does it need to be smaller? Next, FIG. 2 shows the energy band structure of zirconium used in the example when it comes into contact with silicon (Si). In Fig. 2a, φ is the barrier potential difference between n-type Si (n-type Si) and the source or drain electrode, and this is virtually ignored, so in this case, an ohmic current flows. .Second
In FIG. b, φ2 is the barrier potential difference with the P-type Si substrate, which is about 0.7 eV, so that a short contact is formed and it is understood that there is no conduction between the source and drain electrodes. That is, when the above metal materials are used for the source and drain electrodes, if the generation and erasure of n-type channels are controlled by the gate, the operation of the MIS type transistor can be achieved without the need for source and drain diffusion regions. . As will be seen herein, in the present invention the source or drain is comprised of a layer of material in rectifying contact with the substrate and in substantially non-rectifying contact with a channel of opposite conductivity type to the substrate. . Next, an embodiment of the present invention will be explained with reference to FIG.

First, as shown in FIG. 1a, a field insulating film 2 and a gate insulating film 3 are formed on a P-type S1 substrate 1 according to the well-known manufacturing process of MIS type semiconductor devices, and a gate electrode material 4 is applied over the entire surface. A predetermined pattern of photoresist layer 5 is provided on the surface. The layer 4 of gate electrode material may be a semiconductor such as polycrystalline Si doped with impurities or a metal such as aluminum (A1). Photoresist layer 5
The pattern shown in FIG. 2 is a pattern in which the area above the gate electrode part to be formed is left, and the area above the source/drain electrode part is removed.
In this state, using the photoresist layer 5 as a mask, the gate electrode material layer 4 and the gate insulating film 3 are selectively etched to pattern the gate portion. With this process,
A Si substrate 1 is provided in the region where the source and drain electrodes are to be provided.
surface or exposed. Next, when the gate electrode material layer 4 is anodized with the resist layer 5 remaining, only the exposed portion of the gate electrode material layer 4 under the end of the resist layer 5 is converted into an oxide film 6 by anodic oxidation. Furthermore, in this state, the resist layer 5
FIG. 1b shows a cross section of the source/drain electrode material 7 made of zirconium, titanium, indium, etc. deposited on the substrate by vacuum deposition while leaving the . This electrode material may be an n-type semiconductor such as n-type polycrystalline silicon. The thickness (lateral direction) of the oxide film 6 formed by anodic oxidation is, for example, 200 mm.
Let it be 0λ. When the resist layer 5 is removed using a resist removal solution in the state shown in FIG. 1b, the source and drain electrode material layers 7 on the resist layer 5 are lifted off, and the source and drain electrode patterns are completed. This state is shown in FIG. 1c. In the figure, 9 is a gate electrode, and an anodic oxide film 6 is formed at the end of the gate electrode to insulate it from the source and drain electrodes 8. Further, although the gate electrode material layer 4 remains on the field insulating film 2, it is insulated from the source and drain electrodes by the anodic oxide film 6. The gate electrode material layer 4 on the field insulating film 2 can also be used as a wiring layer by forming a resist layer 5 into an appropriate pattern. Further, as shown in FIG. 1d, an insulating film 10 and a wiring layer 11 are formed as necessary to obtain the intended field effect semiconductor device. In each of the above steps, the resist layer 5 is
Since the pattern is defined in three steps: patterning of the gate electrode 9 and gate insulating film 3, selective anodic oxidation of the gate electrode end 6, and patterning of the source and drain electrodes 8, the positions associated with the alignment operation are defined. There is no deviation at all, so the source and drain electrodes 8 are placed close to the gate electrode 9 at a distance equal to the thickness of the anodic oxide film 6, and both electrodes are reliably insulated. For example, if the impurity concentration is 1
0!6C! When a P-type Si substrate of IL-3 is used, the anodic oxide film 6 is formed to a thickness equal to or less than 2500λ of the depletion layer formed in the substrate by a gate voltage large enough to form a channel. Thus, substantially ohmic contact between the channel and the shot key metal 8 is maintained. That is, in the above embodiment, the thickness of the anodic oxide film 6 (anodized thickness) is about 2000, and therefore the electrode 8 functions as a source and drain without a diffusion region, and also serves as a gate electrode 9.
It also has sufficient insulation properties. Of course, if the impurity concentration of the substrate is lower than this, the thickness of the anodic oxide film 6 may be even larger. It is clear that the overlap capacitance Cdg between the gate electrode and the drain is significantly reduced in the present invention. As described above, according to the present invention, it is possible to manufacture a MIS type field effect semiconductor device in which the overlap capacitance Cdg of the gate and drain is significantly reduced without requiring a diffusion process, and which is capable of high-speed operation. It becomes possible to manufacture short channel devices with high yield and high degree of integration.

[Brief explanation of the drawing]

FIGS. 1a to 1d are diagrams explaining the manufacturing process of the embodiment of the present invention,
FIGS. 2a and 2b are diagrams for explaining the operating principle of the semiconductor device according to the present invention.

Claims (1)

[Claims] 1 When forming a MIS field effect transistor on a semiconductor substrate of one conductivity type, the end of the gate electrode is anodized using the resist layer used for patterning the gate portion as a mask, and then rectification is applied to the substrate on the substrate. A field effect semiconductor device, characterized in that after depositing a material that forms a sexual contact, the layer of material is patterned by removing the resist layer to form a source or drain made of the layer of material. manufacturing method.