JPS5921214B2 - variable phase shift circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION For example, VTR jitter and television receiver ghosting can be corrected by using a variable delay device.

The present invention aims to provide a variable phase shift circuit (variable delay circuit) suitable for use in such cases.

Now, in a circuit like the one shown in Figure 1A, the input voltage is e.
Output voltage e.

, these angular frequencies are ω and ■1 , then, 1-jωCR eo-eil+J,,,CR At the same time, the voltage e.

The phase θ is delayed by θ=2jan−′ωcR with respect to the voltage ei, and the group delay time (envelope delay time) dθ/dω is dθ 2CR dω 1+ωCR.

Similarly, in the circuit of FIG. 1B, dθ 2RL dω R+ωL, and in the circuit of FIG.
Furthermore, in the circuit of the first diagram, dθ 2CR (1+ω2LC) □ (1) dω (1-ω2LC)2+ω2C2R2.

Therefore, the circuits shown in FIGS. 1A to 1D function as delay circuits, and by changing the resistor R, the delay time dθ/dω can be varied.

For example, in the circuit shown in Figure 1, by changing the resistance R, the delay time dθ/d
ω can be changed over a fairly wide range.

The present invention focuses on such points to construct a variable delay circuit, and in this case, the input impedance of the negative feedback amplifier is used as the resistor R.

FIG. 3 shows an equivalent circuit of the variable delay circuit according to the present invention. 1 indicates an amplifier, a part of the output signal of which is negatively fed back to the input side of the amplifier 1 through the feedback circuit 2; It is considered to be an input parallel negative feedback amplifier.

Further, 3 indicates a subtraction circuit, which is R1 and R2.

In this case, if the bare gain of the amplifier 1 is A, the input impedance without feedback is Zl, and the feedback rate of the feedback circuit 2 is β, then the input impedance of the amplifier 1 during negative feedback is Z.
■ Z = −Z i ・・・・・・・・・
(2) 1+Aβ.

Regarding the circuit shown in FIG. 3, the input voltage ei and the output voltage e.

Since the potential at the connection point between resistors R1 and R2 is 2 e i , the following equation can be found.

That is, the voltage e.

The phase θ is delayed by ωCZ θ22tan-1□ 1-ω2LC with respect to the voltage ei, and when the group delay time dθ/dω is calculated, dθ
2CZ(1+ω2LD) -2□...(3) dω(1-ω2LC)2+ω2c2z2.

In this equation (3), if we set Z2R, we get (3
) formula coincides with formula (1), and the circuit in FIG. 3 is equivalent to the circuit in FIG. 1.

That is, if the impedance of the series circuit of the coil L and capacitor C shown in FIG. 1 is ZLO, then the output voltage e of the circuit shown in FIG.

is expressed as follows. zI,c R e = ei--e o ZLo+RZLo+R1 Lc-R --e 1 ZLC+R Also, the output voltage e of the circuit of FIG.

The result is as follows.

2R e=2e・□−2e □ −e 4 0 1R1+R2ZLO+R 10゛−2eiZLo+R ZLO−R =ei ZLc+R Therefore, in the circuit shown in the first diagram and the circuit shown in FIG. 3, the output voltage e.

are expressed by the same formula, so both are equivalent.

Moreover, in that case, the input impedance Z in equation (3) is
In this equation (2), the input impedance Z is the bare gain A of the amplifier 1 or the feedback factor β,
That is, it changes depending on the feedback amount Aβ.

Therefore, the circuit in FIG. 3 works as a delay circuit, and if the feedback amount Aβ is changed at that time, the delay time dθ/d
ω changes.

Therefore, the circuit of FIG. 3 functions as a variable delay circuit.

FIG. 4 shows an example of a variable delay circuit according to the present invention that satisfies the equivalent circuit shown in FIG.

That is, input terminal T1 is connected to the base of transistor Q1 through a series circuit of coil L and capacitor C.

This transistor Q1 constitutes the amplifier 1 and the subtraction circuit 3, and its base is further connected to the power supply terminal T3 through a resistor R3, and its cap is connected to the resistor R3.
2 to the terminal T3, and the output terminal T2
', and its emitter is grounded through the resistor R4 and between the collector-base and emitter of the diode-connected transistor Q2.

Further, terminal T1 is connected to the collector of transistor Q1 through resistor R1.

In this case, R4--! -R1-LR2.

2 Furthermore, a transistor Q3 is provided as a feedback circuit 2 for using the transistor Q1 as a negative feedback amplifier 1.

That is, the collector and base of transistor Q2 are connected to the base of transistor Q3 through resistor R5, the collector is connected to the base of transistor Q1, and the emitter of transistor Q3 is grounded.

Further, as means for changing the amount of feedback Aβ to the amplifier 1, a variable constant current source X1 is connected between the base of the transistor Q3 and ground.

According to such a configuration, since the power supply terminal T3 is grounded in an alternating current manner, the series circuit of resistors R1 and R2 is connected between the input terminal T1 and the ground. This is the same connection as shown in the equivalent circuit of FIG.

Also, since transistor Q1 works as a common emitter,
The phases of the signals at the base and collector are opposite.

In this case, the transistor Q2 is diode-connected and functions as a constant voltage element, and its impedance when looking from its collector/base to the ground side is sufficiently small, and the output impedance of the input signal source when seen from the terminal T. If ignored, the AC load on transistor Q1 is a parallel circuit of resistors R1 and R2, and R4=(R17R
2), the voltage gain of the transistor Q1 is 1.

Therefore, transistor Q1 will function as subtraction circuit 3.

And a capacitor C is connected to the base of the transistor Qt.
One end of is connected, and the connection point of resistors R1 and R2 and the output terminal T2 are connected to its collector.
These have the same connection relationship as the equivalent circuit shown in FIG.

Furthermore, since the emitter output of the transistor Q1 is fed back to the base of the transistor Q1 through the transistor Q3 in reverse phase, this transistor Q1 is subjected to parallel human input negative feedback. This corresponds to amplifier 1 in the equivalent circuit shown in the figure.

Therefore, the circuit shown in FIG. 4 functions as a delay circuit, and a delayed output is obtained at terminal T2.

In that case, the input impedance Z when looking from the capacitor C to the transistor Q1 side is as follows.

1 Here, the second term in the denominator of equation (4) is the reciprocal of the output impedance at the collector of transistor Q3, and 11 indicates the constant current of constant current source X.

Further, the third term in the denominator is the reciprocal of the input impedance at the base of the transistor Q1, and 11FBt indicates the current amplification factor of the transistor Qt.

In fact, since 1/R3n0, 1/R4hFE1=0, ZtomiR4exp (--R5II) --- (5)
It becomes T.

Therefore, as is clear from equation (4) or equation (5),
If you change the constant current ■1 of the constant current source Can be changed.

Thus, according to the present invention, a variable delay circuit can be obtained, which is simple in construction and low in cost.

Moreover, it has a wide band, a long delay time, and is easy to connect in multiple stages.

FIG. 5 shows another example of the invention.

In this example, transistors Q5 and Qa are provided, and their emitters are connected to a constant current source X through resistors R7 and R8.
3, whose collector is connected to the transistor QQ t
The collector of transistor Q9 is connected to terminal T3 through resistor R2, the collector of transistor Q1o is connected to terminal T3, the bases of transistors Qo and Qto are connected to bias power supply E1, and a first difference is established. A dynamic amplifier is configured.

Transistors Qzt, Q12 are also provided, the emitters of which are connected to the variable current source A dynamic amplifier is configured.

Furthermore, a transistor Q1s t Q14 is provided, the base of which is connected to the collectors of the transistors Q1□, Q1, and the transistors Q13 . The collector of Q14 is connected to terminal T3, and its emitter is connected to resistor R11J R1□
It is connected to the bases of transistors Q5 and Qa through the transistors Q5 and Qa.

Note 1 In this case, 1R1--R2-R72R8, R12R0=
It is assumed that RIO=R11-R12.

Further, the input terminal T1 is connected to the base of the transistor Q through a series circuit of a coil L and a capacitor C, and is connected to the collector of the transistor Q through a resistor R1, and the output terminal T2 is connected to this collector.

According to such a configuration, the transistors Q5 and Q.

acts as a cascode amplifier, that is, transistor Q5 acts as a common emitter, and transistor Q
9 acts as a common base, so the signal phase is opposite between the paste of transistor Q5 and the collector of transistor Q9, and since R7=(R17R2), the voltage gain of transistor QstQ is 1, and therefore transistors Q5 and Q9 function as a subtraction circuit 3.

Also, transistor Q5. Qa works as a first differential amplifier, transistors Qg and Qto work as a second differential amplifier, and the collector outputs of transistors Q1□ and Q11 are connected to transistors Q5. Since the signal is fed back to the base of Qa in reverse phase, these transistors function as a parallel input negative feedback amplifier.

Therefore, this circuit of FIG. 5 works as a delay circuit, and the terminal T
2, a delayed output is obtained.

In this case, constant current source X3. The constant current of I4 is changed to I3.
I4, the input impedance Z when looking from the capacitor C to the transistor Q is 3z=-R7I4.

Therefore, if the constant current 4 of the constant current source dω can be changed.

Although the above description is based on the circuit shown in FIG. 1, the same structure can be applied to the case where the circuit shown in FIGS. 1A to 1C is used as the basis, or other combinations.

[Brief explanation of drawings]

Fig. 1 is a connection diagram for explaining the present invention in detail, Fig. 2 is a characteristic diagram thereof, and Fig. 3 is a circuit diagram of the circuit according to the present invention.
4 and 5 are connection diagrams of an example of the present invention, respectively. T1 is an input terminal, T2 is an output terminal, 1 is an amplifier, and 2 is a feedback circuit.

Claims (1)

[Claims] 1. Supplying a first input signal to a reactance element, a feedback amplifier connected in series to the reactance element, an adjusting means for changing the amount of feedback of the feedback amplifier, and a series circuit of the reactance element and the feedback amplifier. a first input circuit; a second input circuit that is synchronized with the first input signal and provides a second input signal having a level substantially 1/2 that of the first input signal; a signal synthesis circuit that subtracts or adds the voltage generated at the connection point between the reactance element and the feedback amplifier and the second input signal; A variable phase shift circuit configured to obtain an output signal in which the phase of the first input signal is changed.