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JPS592177B2 - Method for manufacturing high power semiconductor devices - Google Patents
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JPS592177B2 - Method for manufacturing high power semiconductor devices - Google Patents

Method for manufacturing high power semiconductor devices

Info

Publication number
JPS592177B2
JPS592177B2 JP53147089A JP14708978A JPS592177B2 JP S592177 B2 JPS592177 B2 JP S592177B2 JP 53147089 A JP53147089 A JP 53147089A JP 14708978 A JP14708978 A JP 14708978A JP S592177 B2 JPS592177 B2 JP S592177B2
Authority
JP
Japan
Prior art keywords
layer
nickel
aluminum
chip
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53147089A
Other languages
Japanese (ja)
Other versions
JPS5574146A (en
Inventor
英二 山中
裕二 土師
正隆 龍田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tohoku Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tohoku Metal Industries Ltd filed Critical Tohoku Metal Industries Ltd
Priority to JP53147089A priority Critical patent/JPS592177B2/en
Publication of JPS5574146A publication Critical patent/JPS5574146A/en
Publication of JPS592177B2 publication Critical patent/JPS592177B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明ぱ、大電力半導体導体の製造方法に関し、特にそ
のチップ裏全面のメタライズ層およびメタライズ法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-power semiconductor conductor, and particularly to a metallization layer on the entire back surface of the chip and a metallization method.

近年、半導体装置ぱより大電力化が進み、チップが大型
化Lチップ裏全面をケースに鑞付けすることが必要にな
つて来た。
In recent years, as semiconductor devices have become more powerful, chips have become larger, and it has become necessary to braze the entire back surface of the L chip to the case.

このため、従来は、鑞付けを均一に行なうために、第1
図に示すようにシリコン半導体チップ1の裏全面にアル
ミ薄膜J2を付着した後、その表面に金の薄膜3を付し
、この金の薄膜3をケースに鑞付けするようにしていた
。この従来の方法では、チップのメタライズ工程の後、
各種エッチングや熱処理工程において、表面が酸化され
ることはないが、金を使用しているためコスト高となる
欠点がある。
For this reason, conventionally, in order to perform uniform brazing, the first
As shown in the figure, after an aluminum thin film J2 was attached to the entire back surface of the silicon semiconductor chip 1, a gold thin film 3 was attached to the surface thereof, and this gold thin film 3 was brazed to the case. In this conventional method, after the chip metallization process,
Although the surface is not oxidized during various etching and heat treatment processes, the use of gold has the disadvantage of high costs.

また、金が直接シリコンに附着したサすると、金イオン
のシリコンヘの拡散速度は他の金属イオンのそれに比べ
てはるかに早いので、半導体装置の長期間の使用の間に
、耐圧値が低下したり、リーク電流が増加する等特性の
悪化を招き、信頼性に乏しい。従来、金を使用せずに半
導体チップ裏全面に形成したアルミ薄膜上にニッケル層
を形成し、このニッケル層をケースに鑞付けした構造の
ものも用いられている。
In addition, when gold is directly attached to silicon, the diffusion rate of gold ions into silicon is much faster than that of other metal ions, so the withstand voltage value may decrease during long-term use of semiconductor devices. This leads to deterioration of characteristics such as an increase in leakage current, resulting in poor reliability. Conventionally, a structure in which a nickel layer is formed on a thin aluminum film formed on the entire back surface of a semiconductor chip without using gold, and this nickel layer is brazed to the case has also been used.

ニッケル表面は、本来、鑞材の伸びが非常に良く、鑞付
面に適した金属であるが、表面が酸化しやすい欠点があ
る。したがつてニッケル層をアルミ層形成に引続いて行
なつた場合、その後の半導体チップ表面の安定化処理工
程中で表面酸化を受けることになる。それ故、ニッケル
を鑞付け面として用いる場合にはアルミ層形成に引き続
いてニッケル層を形成するのではなく、半導体チップの
表面処理等の工程が終つて、チップをケースに鑞付け固
定する直前にニッケル層の形成を行なわねばならなかつ
た。しかしながら、アルミ層とニッケル層の形成ぱ金属
蒸着という同様の工程でありながら、これらを連続して
行なえないことは、製造工程を複雑にするし、製造上の
手間を要するばかりでなく不経済でもある。
A nickel surface originally has a very good elongation of the solder material, making it a suitable metal for a soldering surface, but it has the disadvantage that the surface is easily oxidized. Therefore, if the nickel layer is formed after the aluminum layer is formed, the surface will undergo surface oxidation during the subsequent stabilization process of the semiconductor chip surface. Therefore, when using nickel as a brazing surface, the nickel layer is not formed following the formation of the aluminum layer, but after the process such as surface treatment of the semiconductor chip is completed and immediately before the chip is brazed and fixed to the case. Formation of a nickel layer had to be carried out. However, although the formation of the aluminum layer and the nickel layer are the same process as the metal vapor deposition, the fact that these cannot be performed consecutively complicates the manufacturing process, not only requires manufacturing effort but also makes it uneconomical. be.

このため、従来では、ニツケルを鑞付け面とせず、前述
のように金を用いていたものである。
For this reason, conventionally, nickel was not used as the brazing surface, but gold was used as described above.

本発明は上記の点に鑑み、金の代Dにニツケルを鑞付け
面としながら、ニツケル層の形成をアルミ層形成に引き
続いて行ない、しかもニツケル表面を酸化のない清浄な
面としてケースへ鑞付けできる方法を提供し、もつて、
上記従来の欠点を解決するこへを目的とする。本発明に
゛よれば、半導体チツプの裏全面にアルミ層を形成後引
き続いてニツケル層を形成し、しかもニツケル層表面の
酸化等を避けるため、ニツケル層形成後、その上に更に
保護膜としてアルミ層を形成し、このアルミーニツケル
ーアルミの三重メタライズ層をもつた状態で半導体チツ
ブ表面の安定化処理等各種の表面処理を行ない、半導体
チツプをケースへ鑞付けする直前に最外アルミ層のみを
除去してニツケル層を露出させ、このニツケル層をケー
スへ鑞付けするようにしている。
In view of the above points, the present invention uses nickel as the brazing surface for the gold layer D, and performs the formation of the nickel layer subsequent to the formation of the aluminum layer, and in addition, brazes the nickel surface to the case with the nickel surface as a clean surface free from oxidation. We will provide you with ways to do so, and
The purpose of this invention is to solve the above-mentioned conventional drawbacks. According to the present invention, after forming an aluminum layer on the entire back surface of a semiconductor chip, a nickel layer is subsequently formed, and in order to avoid oxidation of the surface of the nickel layer, after forming the nickel layer, an aluminum layer is further formed as a protective film on top of the nickel layer. After forming a layer of aluminum and carrying out various surface treatments such as stabilization treatment on the surface of the semiconductor chip with this triple metallized layer of aluminum, only the outermost aluminum layer is formed just before soldering the semiconductor chip to the case. is removed to expose the nickel layer, which is then brazed to the case.

この結果、ニツケル層は表面を清浄に保つた状態でケー
スへ鑞付けできる。以下、本発明を図而に示す実施例を
参照して詳細に説明する。
As a result, the nickel layer can be brazed onto the case while keeping the surface clean. Hereinafter, the present invention will be described in detail with reference to illustrative embodiments.

第2図は、本発明によるメタライズ法を説明する各工程
での断面図を示している。
FIG. 2 shows cross-sectional views at each step to explain the metallization method according to the present invention.

第2図)を参照して、所要の回路素子を形成したシリコ
ンチツプ1の裏面に、通常の方法でアルミ層2を形成す
る。
Referring to FIG. 2), an aluminum layer 2 is formed by a conventional method on the back surface of the silicon chip 1 on which necessary circuit elements have been formed.

続いてこれを、400℃前後で熱処理して、シリコンチ
ツプ1とアルミ層2との接触部に沿つてアルミ−シリコ
ンの合金層を形成する。この合金層が第2図)以後に4
で示されている。次に、アルミ層2の表面に、ニツケル
層5を形成する(第2図)。
Subsequently, this is heat treated at around 400 DEG C. to form an aluminum-silicon alloy layer along the contact area between the silicon chip 1 and the aluminum layer 2. This alloy layer is shown in Figure 2) after 4
is shown. Next, a nickel layer 5 is formed on the surface of the aluminum layer 2 (FIG. 2).

このニツケル層は後に、ケースとの鑞付け面として利用
される。これに引き続いて、ニツケル層5の表面に、更
にアルミ層6を形成する(第2図))。
This nickel layer is later used as a soldering surface to the case. Subsequently, an aluminum layer 6 is further formed on the surface of the nickel layer 5 (FIG. 2).

このアルミ層6は、その後に行なわれるチツプの表面安
定化処理工程に卦いて、ニツケル表面を保護する作用を
する。すなわち、メタライズ層をアルミーニツケルーア
ルミの三層構造とした後、通常メタライズ工程後に行な
われる種々の処理、例えばパツシペーシヨン、ワツクス
塗布、チツブ切断、ワツクス除去等の処理を行なう。こ
れらの処理で用いられる酸類、レジスト剥離液、アルカ
リ溶液等によつてもニツケル層5は、アルミ層6の存在
によつて、保護される。もちろんアルミ層6は、酸化や
エツチングを受けるので、その厚みを充分厚くして卦く
ことが必要である。通常2〜3μmで充分である。メタ
ライズ工程後に行なわれる各種処理が終了し、チツプを
ケースFlC鑞付けする直前に、最外層のアルミ層6を
除去してニツケル層5を露出させる(第2図))。
This aluminum layer 6 serves to protect the nickel surface during the subsequent chip surface stabilization process. That is, after forming the metallized layer into a three-layer structure of aluminum and aluminum, various treatments normally performed after the metallization step, such as passivation, wax coating, chip cutting, and wax removal, are performed. The presence of the aluminum layer 6 protects the nickel layer 5 from acids, resist stripping solutions, alkaline solutions, etc. used in these treatments. Of course, since the aluminum layer 6 is subject to oxidation and etching, it is necessary to make it sufficiently thick. Usually 2 to 3 μm is sufficient. After the various treatments performed after the metallization step are completed and immediately before the chip is soldered to the case with FlC, the outermost aluminum layer 6 is removed to expose the nickel layer 5 (FIG. 2).

このアルミ層6の除去は、希釈フツ酸によるエツチング
によつて行なわれる。ニツケルは希釈フツ酸では全くエ
ツチングされないので、アルミが完全に除去されるとエ
ツチングが自動的に停止し、清浄なニツケル面が露出す
る。その後、この露出された清浄なニツケル面を鑞材7
によつて、ケース8の面へ鑞付けする(第2図))。こ
の鑞付け工程ではニツケル層5の表面が清浄な面として
確保されているので、鑞材の伸びが良く、従つて、気泡
の発生もほとんどなく、熱抵抗の小さな鑞付けを行なう
ことができる。本発明によれば、半導体チツブをケース
に鑞付けするためのメタライズ層に金を使用しないので
、安価となv、また金を用いることによる不都合即ち、
チツプへの金付着を防止するための特別の配慮や、金付
着による特性の劣化等が解消される。その上、金の代り
にニツケルを用いながら、ニツケルの蒸着をアルミの蒸
着と連続して行なうことができ、しかも、ニツケル鑞付
け面の酸化が防止され、ケースへの完全な鑞付けが行な
われるので、製造上の容易さ、簡略さ、低コスト化を満
しながらチツプのケースへの完全な鑞付けを実現できる
ものである。鑞付け面の酸化等が確実に防止されている
ので、ケースの熱抵抗の小さな完全な鑞付けが行なわれ
る。
The aluminum layer 6 is removed by etching with diluted hydrofluoric acid. Since nickel is not etched at all with dilute hydrofluoric acid, etching automatically stops when the aluminum is completely removed, exposing a clean nickel surface. Then, apply this exposed clean nickel surface to the solder material 7.
(Fig. 2)). In this brazing process, the surface of the nickel layer 5 is ensured as a clean surface, so the solder material spreads well, and therefore there is almost no generation of bubbles, making it possible to perform brazing with low thermal resistance. According to the present invention, since gold is not used in the metallized layer for brazing the semiconductor chip to the case, it is inexpensive and also has the disadvantages of using gold.
Special considerations to prevent gold from adhering to the chip and deterioration of properties due to gold adhesion are eliminated. Moreover, while using nickel instead of gold, the nickel deposition can be carried out sequentially with the aluminum deposition, yet oxidation of the nickel brazed surfaces is prevented and complete brazing to the case is achieved. Therefore, it is possible to completely braze the chip to the case while satisfying the requirements of ease of manufacture, simplicity, and low cost. Since oxidation of the soldering surface is reliably prevented, complete brazing with low thermal resistance of the case can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来のメタライズされた半導体チツプの断面
を示す図で、第2図1)〜)は、本発明によるメタライ
ズおよびケースへの鑞付けの各工程を順を追つて示す断
面図である。 1・・・シリコンチツプ、2・・・アルミ層、4・・・
アルミ−シリコン合金層、5・・・ニツケル層、6・・
・アルミ層、7・・・鑞材、8・・・ケース。
Fig. 1 is a cross-sectional view of a conventional metallized semiconductor chip, and Fig. 2 (1) to 2) are cross-sectional views sequentially showing each step of metallization and brazing to a case according to the present invention. be. 1... Silicon chip, 2... Aluminum layer, 4...
Aluminum-silicon alloy layer, 5...Nickel layer, 6...
- Aluminum layer, 7... Brazing material, 8... Case.

Claims (1)

【特許請求の範囲】[Claims] 1 大電力半導体素子の半導体チップ裏面全面をメタラ
イズした後、該チップに必要な処理を施し、その後該メ
タライズ層をケースに鑞付けして大電力半導体装置を製
造する方法において、該チップ裏面全面にまずアルミ薄
膜を付着してチップシリコンと部分的に合金化させた後
、該アルミ薄膜上にニッケル薄膜を付着し、更に該ニッ
ケル薄膜表面保護膜としてアルミ薄膜を付着して、アル
ミ−ニッケル−アルミの三層構造のメタライズ層を連続
して形成しておき、該チップをケースへ鑞付け固定する
直前に最外アルミ薄膜だけを除去してニッケル層を露出
させ該ニッケル層をケースへ鑞付けすることを特徴とす
ることを特徴とする大電力半導体装置の製造方法。
1. In a method of manufacturing a high power semiconductor device by metallizing the entire back surface of a semiconductor chip of a high power semiconductor element, subjecting the chip to necessary processing, and then brazing the metallized layer to a case, the entire back surface of the chip is metallized. First, an aluminum thin film is deposited and partially alloyed with chip silicon, and then a nickel thin film is deposited on the aluminum thin film, and then an aluminum thin film is deposited as a surface protection film on the nickel thin film, and the aluminum-nickel-aluminum A three-layer metallized layer is formed in succession, and just before brazing and fixing the chip to the case, only the outermost aluminum thin film is removed to expose the nickel layer, and the nickel layer is brazed to the case. A method of manufacturing a high power semiconductor device, characterized in that:
JP53147089A 1978-11-30 1978-11-30 Method for manufacturing high power semiconductor devices Expired JPS592177B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53147089A JPS592177B2 (en) 1978-11-30 1978-11-30 Method for manufacturing high power semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53147089A JPS592177B2 (en) 1978-11-30 1978-11-30 Method for manufacturing high power semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5574146A JPS5574146A (en) 1980-06-04
JPS592177B2 true JPS592177B2 (en) 1984-01-17

Family

ID=15422214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53147089A Expired JPS592177B2 (en) 1978-11-30 1978-11-30 Method for manufacturing high power semiconductor devices

Country Status (1)

Country Link
JP (1) JPS592177B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929791A (en) * 1972-07-18 1974-03-16
JPS527675A (en) * 1975-07-09 1977-01-20 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS5574146A (en) 1980-06-04

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