JPS592184B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a structure in which elements are separated by an isolation oxide film, such as an integrated circuit.

Generally, an integrated circuit has a plurality of circuit elements formed on a single semiconductor substrate so as to be electrically insulated and separated from each other.

As this isolation method, a method of forming an isolation oxide film has been widely used in recent years because it enables high-speed integration and reduction of various parasitic capacitances. FIGS. 1a to 1f are cross-sectional views of a semiconductor device at each step in this conventional semiconductor device manufacturing method.

As a semiconductor device, a bipolar integrated circuit having an npn transistor as an element is used. First, a plurality of n-type collector buried layers 2 as buried semiconductor regions are formed on the surface of a semiconductor substrate 1 made of p-type silicon, separated from each other, and further, an n-type epitaxial layer 3 is formed entirely on this surface. is formed to a predetermined thickness, a silicon oxide film 10 is formed on the surface of this epitaxial layer 3, and a silicon nitride film 20 as an oxidation-resistant film is further formed on the surface of this silicon oxide film 10.

Next, a resist 30 is formed on the surface of the silicon nitride film 20, and after this resist 30 is selectively etched away to form a predetermined pattern, the silicon nitride film 20 is selectively etched away using the resist 30 as a mask. . FIG. 1a shows this situation. Next, resist 30
After completely removing the silicon oxide film 1, using the silicon nitride film 20 patterned by etching as a mask.
0 is selectively etched away. Thereafter, epitaxial layer 3 is selectively etched away to a predetermined depth using silicon oxide film 10 and silicon nitride film 20 as masks. FIG. 1b shows this situation. Note that etching in each step is performed by a well-known dry etching method or wet etching method. Next, isolation oxide film 11 is formed using silicon nitride film 20 as a mask.

FIG. 1c shows this situation. At this time, the thickness of the epitaxial layer 3 is, for example, 1.8 μm? Then, the depth of the epitaxial layer removed by etching is set to about 1.1 .mu.m, and the isolation oxide film 11 is formed as thick as about 1.6 .mu.m, so that it reaches the collector buried layer 2. As a result, the collector buried layers 2 are insulated and separated from each other. Next, after removing the silicon nitride film 20, a resist 31 is formed on the surface and selectively etched away, and then, using the resist 31 as a mask, p-type impurities such as poron are ion-implanted to form an epitaxial layer. A base layer 4 is formed on a portion of layer 3.

FIG. 1d shows this situation. Next, after the resist 31 is completely removed, a resist 32 is formed on the surface and selectively etched away, and then the silicon oxide film 10 is selectively removed using the resist 32 as a mask.

Furthermore, using this resist 32 as a mask, n-type impurities such as phosphorus and arsenic are ion-implanted to form a collector electrode extraction layer 6 in a part of the base layer 4 and a part of the K emitter layer 5 and the epitaxial layer 3, respectively. Form.

FIG. 1e shows this situation. Next, silicon oxide film 10
is selectively removed by etching to form a base electrode outlet 10a at a part of the base layer 4.

Through these steps, an Npn transistor surrounded by the isolation oxide film 11 and insulated from other elements is formed. FIG. 1f shows this situation. However, the integrated circuit manufactured by such a conventional method has a wall emitter structure in which the emitter layer 5 is in contact with the isolation oxide film 11 as shown in FIG. There is a problem that there is a gap leak.

FIG. 2 is a cross-sectional view of a typical transistor configured in an integrated circuit.

In the figures, parts corresponding to those in FIG. 1 are given the same numbers. The thickness of isolation oxide film 11 shown here is T. The distance w between the edge of the emitter layer 5 and the isolation oxide film 11
has a large correlation with the collector-emitter leakage rate and the emitter amplification factor (HFE) of the transistor. Fig. 3 is a graph showing the relationship between the distance W with the thickness t as a parameter and the leakage rate when 100 transistors are arranged in parallel, and Fig. 4 is a graph showing the relationship between the distance w and the emitter with the thickness t as a parameter. It is a graph showing the relationship between amplification factors.

In Figure 3, characteristic a is t = 1.6 μm, characteristic b is t
-1.2 μm is shown. Here, it can be seen that the smaller the distance w and the thicker the thickness t, the higher the leakage rate due to distortion of the isolation oxide film. Also, in FIG. 4, characteristic a is t=1.6 μm, and characteristic b is t=1.6 μm.
The case of 2 μm is shown. Here, as the distance W becomes smaller,
It can also be seen that as the thickness t increases, the emitter amplification factor decreases. Therefore, if the thickness t of the isolation oxide film 11 is as thick as about 1.6 μm, the distance W needs to be 5 μm or more.

Further, if the thickness t of the isolation oxide film 11 is as thin as about 1.2 μm, the distance W may be 2 μm. In Figure 5, the distance w is 5 μm.
The plan view of the transistor in the case of Fig. 6 shows that the distance w is 2μ.
It is a top view in the case of m.

In each figure, parts equivalent to those in Figure 2 are given the same numbers. In FIG. 5, the area of the base layer 4 is 18×14
=252μM2, transistor area is 34×22=74
It is 8 μM2. In addition, in FIG. 6, the base layer 4
The area of the transistor is 15×8=120 μM2, and the area of the transistor is 28×16−448 μM2. Therefore, if the distance w is set to 2 μm, the area of the base layer will be reduced to 48% and the area of the transistor will be reduced to 60%, respectively, compared to the case of 5 μm. However, as explained with reference to FIG. 1c, the isolation oxide film must be formed until it reaches the collector buried layer, so it cannot be made thinner than a predetermined thickness.

Furthermore, if the epitaxial layer is made thinner, the isolation oxide film can also be made thinner, but if the epitaxial layer is made thinner, the breakdown voltage characteristics between the collector base and further between the collector and emitter deteriorate. As described above, in the conventional method for manufacturing semiconductor devices, the distance between the edge of the emitter layer and the isolation oxide film cannot be made small, and therefore it is difficult to increase the degree of integration. It was hot. This invention was made to eliminate these conventional drawbacks, and its purpose is to reduce the device area and increase the integration density without deteriorating the functional characteristics of semiconductor devices. An object of the present invention is to provide a method for manufacturing such a semiconductor device. Hereinafter, this invention will be explained in detail based on examples. FIG. 7 is a cross-sectional view of a semiconductor device at various steps according to an embodiment of the method for manufacturing a semiconductor device according to the present invention.

However, since the process up to the state shown in FIG. 1a is the same as the conventional process, the explanation will be omitted. From the state of FIG. 1a, the resist 30
The silicon oxide film 10 is selectively etched away using the silicon nitride film 20 as a mask while leaving it as it is. 7th
Figure a shows this situation. Next, the silicon nitride film 20 is removed by dry etching using the resist 30 as a mask.

In this case, since the silicon nitride film 20 has already been etched away by the resist 30 in the previous step, further etching in this way causes a so-called side etching phenomenon, which removes the silicon nitride film 20 under the V1 resist 30. is etched, and a wider area is etched away than the area etched away in the previous step. 7th
Figure b shows this situation. Next, after removing the resist 30, the epitaxial layer 3 is selectively etched away to a predetermined depth using the silicon oxide film 10 as a mask.

FIG. 7c shows this state. Next, this wafer is heat-treated in an oxidizing atmosphere to selectively oxidize using the silicon nitride film 20 as a mask to form the isolation oxide film 11.

At this time, the isolation oxide film 11 is formed deeply until it reaches the collector buried layer 2 in order to isolate the elements. 7th
Figure d shows this situation. The oxide film 12 at the end of the isolation oxide film 11 is formed to protrude above the substrate surface because the epitaxial layer 3 in this part is not etched away by the silicon oxide film 10. And about 5 of the oxide film 12
The area of 5% will be formed on the surface of the substrate, and the thickness will be 0.5%, assuming that the thickness of the isolation oxide film 11 is 1.6 μm.
The thickness is about 8 μm9, which can reduce collector-emitter leakage from this part. From now on, as before, Figure 1 d
An Npn type transistor is formed through the process -f.

As a result, the isolation oxide film has a two-tiered structure, consisting of a part that reaches the collector buried layer and a part of the oxide film that surrounds the emitter region at the periphery.Moreover, the part of the thick oxide film that surrounds this emitter region is below the substrate surface. The thickness of the separating oxide film is 4
Since it can be made as thin as about 5%, it is possible to reduce the rate of leakage between the collector and emitter and to reduce the distance between the edge of the emitter layer and the isolation oxide film without reducing the emitter amplification factor.

Therefore, for the same isolation oxide film width, it is possible to reduce the area of the five transistors without reducing the voltage resistance by making the epitaxial layer thinner. You can improve. Furthermore, since the base area can be reduced, the capacitance between the collector and the base can be reduced, and the frequency characteristics of the transistor can be significantly improved. Although Npn type transistors have been described in the above embodiments, the present invention can be applied to Pnp type transistors as well, and can also be applied to single elements as well as integrated circuits.

As described above, according to the method of manufacturing a semiconductor device according to the present invention, by forming the isolation oxide film into a two-stage structure, the distance between the emitter layer and the isolation oxide film can be reduced, so that the integration density is high. This has the effect of improving frequency characteristics.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device at each step in a conventional semiconductor device manufacturing method, FIG. 2 is a cross-sectional view of a general transistor, FIG. 3 is a graph showing the relationship between distance w and leakage rate, and FIG. The figure is a graph showing the relationship between distance w and emitter amplification factor, Figure 5 is a plan view of the transistor when distance w is 5 μm, Figure 6 is a plan view of the transistor when distance W is 2 μm, and Figure 7 is a graph showing the relationship between distance w and emitter amplification factor. FIG. 3 is a cross-sectional view of a semiconductor device at each step according to an embodiment of the method for manufacturing a semiconductor device according to the present invention. Note that the same reference numerals in the figures indicate the same or corresponding parts. 1... Semiconductor substrate, 2... Collector buried layer, 3... Epitaxial layer, 4...
・Base layer, 5... Emitsuta layer, 6...
・Collector electrode extraction layer, 10... Silicon oxide film, 11... Separation oxide film, 12...
Oxide film, 20...Silicon nitride film, 30, 31
, 32...Resist.

Claims (1)

[Claims] 1. An oxide film is formed on the surface of a semiconductor substrate, an oxidation-resistant film is formed on the oxide film, and the oxidation-resistant film is selectively etched away. selectively etching away the oxide film using the oxide film as a mask, etching the oxidation resistant film wider than the etched away portion, selectively etching the semiconductor substrate using the oxide film as a mask, 1. A method of manufacturing a semiconductor device, comprising sequentially performing each step of selectively oxidizing using an oxidation-resistant film as a mask and forming a two-stage isolation oxide film on the etched away portion of the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate has a buried semiconductor region, and the isolation oxide film is formed to a depth that contacts the buried semiconductor region.