JPS5922261B2 - comparison detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparison and detection circuit used in digital arithmetic circuits and the like, and particularly to a comparison and detection circuit that can simplify the circuit configuration for dynamically comparing and detecting data.

Conventionally, a comparison circuit of this type that inputs two types of data one bit at a time sequentially to a digital comparison circuit and detects coincidence or mismatch of the data is known, for example, from Japanese Patent Publication No. 49-34367. It is being

However, in the case of this type, unless the data switching is performed for each bit continuously, that is, with almost no switching interval, the comparison output when the data comparison operation is stopped and the comparison output during the comparison operation are different. Since the coincidence output signal is in the same signal state, if the switching operation is performed intermittently, it will not be possible to determine whether the data match or mismatch simply by detecting the output of this digital comparison circuit. Furthermore, in order to detect whether or not the data of a plurality of consecutive bits match, in the above method, the results of the sequential comparison of each bit are held in a memory means, etc., and the comparison of each bit is performed. It is necessary to determine whether or not a predetermined plurality of consecutive bits of the result are in a consistent state, which poses problems such as requiring a complicated logic circuit configuration. The present invention has been made in view of this point, and includes a first data source (corresponding to A1 to AX-1 in FIG. 1) that outputs multiple bits of digital data.

), a second data source (corresponding to B1 to BX+1 in FIG. 1) that outputs multi-bit digital data, a binary signal input to the first input terminal, and a second input terminal. A first comparison output signal is formed when both signals are in the same signal state, and a second comparison output signal is formed when both signals are in different signal states. A first comparator circuit (corresponding to CC in FIG. 1) and a first input terminal of the first comparator circuit that sequentially switches the binary signal of each bit of the first data source in time series. A first switching means for inputting (corresponding to S1 to SX+1 in FIG. 1);
The binary signal of each bit of the second data source is switched sequentially in time series in synchronization with the switching operation of the first switching means, and the second data source is input to the second input terminal of the first comparison circuit. switching means (corresponding to S/1 to S' ), the output level of the ramp waveform signal generating means is returned to the initial state in response to one comparison output signal of the output of the first comparison circuit, and the change in the output level is started again from this state. The control means (corresponding to Trl in FIG. 1) and the output level of the slope waveform signal generation means are compared with a reference level to determine the output level, L. a second comparator circuit (corresponding to the ICO in FIG. 1) that shifts the output state from the first output state to the second output state when the output state reaches the reference level;
By providing a data comparison circuit between the first data source and the second data source in the output state of the second comparison circuit, the second comparison is always carried out even when there is an interval between zeta switching operations. If the circuit output is detected, the data will match.
It is an object of the present invention to provide a comparison circuit that can determine whether or not there is a mismatch, and can also determine whether or not a plurality of consecutive bits match by simply adjusting the reference level. The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a circuit connection diagram showing an example of a dynamic comparison detection circuit 0 according to the present invention. In the figure, A and B are setting sections for two types of data A and B to be compared, and S1 to S
X+1 and S7l to S/X+1 are data A, respectively.
This is a group of switches for inputting A1 to B.
X+1 and B1 to BX+1 are a group of switches for indicating the presence or absence of data, and when these switches are on, a logical value 11L11 is generated, thereby indicating that data is present. Rl and R2 are pull-up resistors connected in series with appropriate values to the power supply Cc so that the current capacity of the data switch etc. is within the permissible range. D1~DX+
1. D transistor, C
1 and R4 are a capacitor and a resistor that constitute a time constant circuit to obtain the detection speed, CO is a differential amplifier for comparison,
D is a logic output terminal. FIG. 2 is a curve diagram showing an example of a timing chart of the circuit shown in FIG.

The diagram shows the data switches A1-AX+1 and B1-BX+1 in FIG. 1 in the illustrated states. In FIG. 1, switch groups S1 to SX+1 and Sl
When the data switches A1 to S'
When +1 is in the position shown, the output of circuit A will have a waveform as shown in FIG. 2b. Also, data switches B1 to Bx
When +1 is in the position shown, the output of the circuit (B) is as shown in Figure 2c.
It will be like this. These data outputs b and c are applied to both input terminals of a comparison circuit CC and compared there. C.C.
Since this is an EX-0R circuit, when inputs B and c match, an output of 11L1W is produced, and a waveform as shown in FIG. 2d is obtained. That is, the CC output at the position corresponding to the pulses of S4, S'4 and Sx, Sxl becomes 11L11. This CC
The output of is applied via the inverter 11, the resistor R3 and the transistor Trl to a time circuit made up of Cl and R4 connected in parallel. Due to the time constants of Cl and R4, a sawtooth wave as shown in FIG. 2e is generated at its output. The dotted line in the figure indicates the threshold level VTl of an analog comparator circuit which inputs this output and compares the levels. In other words, the ICO constitutes a checkout circuit, and the output is inverted to 11Hj]゛L'' for inputs above and below its threshold level.Therefore, the output of the ICO has a waveform as shown in Figure 2f. A coincidence output 1!Lll is obtained when the phase is below the dotted line.A mismatch is detected at 11H11.As described above, in the comparison detection circuit of the present invention, the coincidence and mismatch between a large number of data A and B are sequentially detected. It can be determined by a single comparison circuit, does not require a complicated circuit such as a memory circuit, and the device configuration can be simplified.In the timing chart in Figure 2, detection can be made by a 1-bit match. The output is now IlLl, but it is also possible to change the threshold level of the detection circuit so that a match output is obtained only when there is a continuous match of 2 or more bits. This is a timing chart of the circuit in Fig. 1 when checking out a match.As shown, the match output 11L11 from the comparator circuit CC continuously outputs pulses 5 to 8, which are detected by the detection circuit and output to the ICO. A coincidence output 1L1T is generated when the threshold level VT2 is lowered.Next, FIG. 4 shows an embodiment in which the comparison detection circuit according to the present invention is used in a timer circuit that repeatedly turns on and off at regular intervals. FIG. 3 is a circuit configuration diagram.

The figure shows a device that compares one unit (for example, one digit of a number) for every four bits and performs this for four digits. In the figure, PS1 to PS4 are preset switches for setting on time, and PS5 to PS8 are preset switches for setting off time. G1 to G8 are gates for dynamic driving of the switch outputs, each consisting of four AND gates, and the gates are sequentially turned on by timing pulses from the ring counter RC. G9
, GlO are AND gates driven by flip-flops. 0SC is a clock pulse generator, and C1 to C5 are counters Gll for dividing the output pulse of 0SC.
~Gl4 is an AND gate that is controlled by a timing pulse and turns on and off the outputs of C2 to C5, MC is a level comparison circuit, DCC is a dynamic comparison detection circuit according to the present invention,
FF is a flip-flop, Set is a FF set circuit,
O is an output circuit, such as a switching circuit.

The operation of the device shown in FIG. 4 is as follows: Initially, the output terminal Q of the flip-flop FF is set to 1Li) by the set circuit, and Q is set to 11H1.
It is set to W.

This output turns gate G9 on and GlO off. In this state, the preset switches PSL to PS
Set to 4. The on-time data is sequentially sent to gate G9 by gates G1 to G4, which are dynamically driven by timing pulses from ring counter RC.
It is input to the level comparator MC through. On the other hand, the output pulse of the clock pulse oscillator 0SC is output from the frequency dividing counters C1 to C1.
The data of C2 to C5 is input to the level comparator MC through gates Gll to Gl4 which are dynamically driven in synchronization with gates G1 to G4. MC is PSL data and C2 data,
Compare the data of PS2 and C3, PS3 and C4, and PS4 and C. When these two groups of data are equal, an 11HI: output is generated at the MC output, which is input to the dynamic comparator check circuit DCC. The DCC has a circuit configuration as shown in Figure 1. When all input data are equal, that is, when there are 4 consecutive matching inputs as shown in the timing chart of Figure 3, the output of the DCC is 11Lli. become. This is input to the FF, the FF is inverted, and the output terminal Q is 11H\Q
becomes 1fL1. This Q output 11H11 turns on the output circuit 0. In addition, the output of the FF turns off the gate G9 and turns on the GLO, and the data of the switches PS5 to PS8, which have set the off time setting data in the same way as above, and the data of C2 to C5 are manually compared in level to the MC. Ru. If these two groups of data are the same, the MC outputs a coincidence signal, and the DCC also outputs a coincidence signal to invert the FF. As a result, the output terminal Q returns from 1L111σ to 1SH11. Qf)1
The LI output inverts the output circuit 0 and turns off the switch. A timer operation can be performed using the on/off operation of this output circuit 0, and the period is the counter C
It depends on the fundamental period of 2 to C5. As described above, in the comparison detection circuit of the present invention, digital comparison and analog comparison are performed with the above-mentioned configuration.
Even when data switching operations are performed intermittently, comparison results can be prevented from being affected by these switching operations, and it can be determined whether consecutive multiple bits of data match with an extremely simple configuration. It is possible to do this.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram showing an embodiment of the dynamic comparison detection circuit according to the present invention, FIGS. 2 and 3 are curve diagrams showing timing charts in the circuit of FIG. 1, and FIG. 4 is a comparison diagram of the present invention. FIG. 2 is a circuit configuration diagram showing an example in which a detection circuit is used as a timer circuit. S1~SX+1, S1~S/x+1...Data switch group) A1ゞAX+17B1ゝBx+BI゜゜゜゛Data A9B preset switch group, D1~DX
+1, D}~D/x+B---Diode, CC・
... Comparison circuit, Trl ... Emitter follower transistor, C1R4 ... Time setting circuit,
ICO...Analog comparator.

Claims (1)

[Claims] 1. A first data source that outputs multiple bits of digital data, a second data source that outputs multiple bits of digital data, a binary signal input to the first input terminal, and a second input terminal A first comparison output signal is formed when both signals are in the same signal state, and a second comparison output signal is formed when both signals are in different signal states. A first comparison circuit and a first data source that sequentially switch the binary signals of each bit of the first data source in time series.
a first switching means inputting the binary signal of each bit of the second data source to the first input terminal of the comparing circuit;
A second switching means inputs the input to the second input terminal of the first comparator circuit in chronological order in synchronization with the switching operation of the switching means, and changes the output level from the initial output state over time. The output level of the slope waveform signal generation means is returned to the initial state in response to the comparison output signal of one of the first comparison circuit outputs, and from this state the output level changes again. and a control means for comparing the output level of the slope waveform signal generating means with a reference level and shifting the output state from a first output state to a second output state when the output level reaches the reference level. 1. A comparison detection circuit comprising: two comparison circuits, and data comparison between a first data source and a second data source is performed based on the output state of the second comparison circuit.