JPS5922993B2 - pattern identification device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a pattern identification device, and particularly a pattern identification device that can reduce the frequency of rejects when identifying recognition target figures such as handwritten characters, and can prevent misreading. It is related to.

Generally, a pattern recognition device for identifying a figure to be recognized has a standard pattern a stored in a dictionary 1 in advance, as shown in FIG.

a0...an are prepared, and feature patterns XOXl... al・
. . . Matching/mismatching with an is detected by the matching circuit 3,
The configuration is such that the figure to be recognized is identified based on the detection result. If a match between the feature pattern and the standard pattern cannot be obtained, that is, the feature pattern is rejected, a new feature pattern is obtained by changing the threshold level or feature extraction method in preprocessing, and the obtained feature pattern is Matching/mismatching between the standard pattern and the standard pattern is detected. Note that this kind of processing is called rescanning.
Conventionally, this type of pattern identification device is known, for example, one that prepares only a very small number of standard patterns for one figure to be recognized, thereby making it possible to sufficiently reduce the probability that the figure to be recognized will be misread. .

Furthermore, a method is known in which a large number of standard patterns are prepared corresponding to one figure to be recognized so that the frequency of rejects can be sufficiently reduced. However, when the figure to be recognized is a handwritten character, the former device can only recognize the target character whose deformation (i.e., shading, blurring, force deviation, etc.) of the character is extremely small, and the deformation is relatively large. It becomes impossible to identify the characters to be recognized. That is, there was a problem in that the overall frequency of rejections was extremely high. On the other hand, the latter device may mistakenly identify the transformed characters as other characters. That is, for example, in the case where a standard pattern for the number "7" with the lower loop in the number [~9] is prepared in advance, the correctly written number "9" is selected as the character to be recognized. In this case, the standard pattern for "8" may be referred to and the recognition target character "9" may be mistakenly labeled as "8". The present invention aims to solve the above-mentioned problems, and aims to sufficiently reduce the frequency of rejects and prevent misreading.

Therefore, the pattern identification device of the present invention includes a first matching circuit that detects whether or not a feature pattern obtained by extracting the features of the recognition target figure matches a standard pattern prepared in advance to identify the recognition target figure. In the pattern identification device, a matching instruction pattern is added in advance to the standard pattern to instruct which rescan the standard pattern should be referred to, and
A rescan control circuit that generates a rescan display pattern corresponding to rescan, and a second matching circuit that detects a match/mismatch between the matching instruction pattern and the rescan display pattern are provided, and the output from the first matching circuit is connected to the rescan display pattern. It is characterized in that it is masked by two matching circuits. Figures 2 to 4 below
This will be explained with reference to Figures A and B. FIG. 2 shows the configuration of one embodiment of the pattern identification device according to the present invention, FIG. 3 shows the circuit configuration of one embodiment of the matching circuit shown in FIG. 2, and FIGS. 4A and B illustrate the circuit operation. Figures are shown respectively.

In Fig. 2, V is a dictionary, 2 is a feature extraction circuit, 3' is a matching circuit, 4 is a rescan control circuit, XOXl...X
n is a characteristic pattern, AOa, . . . An is a standard pattern, AO+1 .
...Wn+k is the second of the matching instruction patterns
The bit patterns Xn+, . . .

The matching instruction pattern consisting of the first bit pattern An+Bi...An+k and the second bit pattern Wn+1...Wn+k is each standard pattern A.

al...An is provided in one-to-one correspondence.
As will be described later, the matching instruction pattern instructs at which scan time the standard pattern should be referred to among a plurality of scan times. The risk indicator patterns XO+bi...Xn+k are given in one-to-one correspondence to each risk, as will be described later. Matching circuit 3'
is configured as shown in FIG. 3, for example.

In FIG. 3, 5 is the first matching circuit, which is the characteristic pattern X. , Xl...Xn and standard pattern A. al...
6 is a second matching circuit that detects a match/mismatch with An, and 6 is a second match circuit that detects a rematching instruction pattern (An+1゜゜゜a
7 is a Noah gate, 8-0, 8-1, . . .
・,8-N,8-(n+k),...,8-(n+k)
9-1, . . . , 9-k each represent an exclusive OR gate, and 9-1, . . . , 9-k each represent an AND gate. Figure 4 A, B
3 shows an explanatory diagram for explaining the circuit operation of the coincidence circuit shown in FIG. 3. FIG.

In FIGS. 4A and 4B, risk scan O corresponds to when the preprocessing is performed at a normal threshold level, and risk scan 1 corresponds to when the preprocessing is performed at a predetermined threshold level, for example higher than the threshold level corresponding to risk scan O. Re-scan 2 corresponds to when the pre-processing is performed at a predetermined threshold level, which is lower, for example, than the threshold level corresponding to the re-scan O.

And the rescan display pattern Xn+1Xn+2 is the fourth
As shown in Figure B, for example, (00), (10), (
01). In the case of this embodiment, as shown in FIG. 4A, for example, the correctly written number "2" [8]
, "9".

Ctala...AnaaOβ a1β...AOβ,
A matching instruction pattern in which the second bit patterns Wn+1 and W0+2 are "00" is added to AO5alξ...Anξ. Also, standard pattern A corresponds to the number "8" where some of the letters are faded. ,al,
...For Anγ, the first bit pattern An+
Standard pattern A corresponds to the number "house" with the lower loop collapsed, with the addition of a matching instruction pattern in which 1an+2 is "*1" and the second bit pattern Wn+1Wn+2 is "O1". δa1δ...For AOδ, the first bit pattern AO+, AO+, is "1'+l" and the second bit pattern Wn+
A matching instruction pattern in which 1Wn+2 is "10" is added.The circuit operation of the matching circuit 3' in each case when risk is 0, risk 1, and risk 2 will be explained below.(1) Risk scan When O, as mentioned above, rescan C display pattern Xn+1
Xn+2 is given as "00".

In this case (1) Correctly written numbers “2” and “8”
, each standard pattern A corresponding to "9".

al...For AO, the second bit pattern W
Since n+1 and Wn+2 are given as "00" as described above, the outputs of the AND gates 9-1 and 9-2 in the second coincidence circuit 6 both become logic [0]. Therefore each exclusive-OR gate 8 in the first matching circuit 5
The output of the NOR gate 7 is determined based on the outputs of -0, 8-1, . . . , 8-n. In other words, the standard pattern A corresponds to correctly written numbers "2", "8", and "9", respectively. aala...AOOaOβ a1β...
・AOβ, AO8alξ...Anξ is referenced when risk scan O. (2) Standard pattern A corresponding to the number "8" with some of the letters blurred. γ a1γ・
...For AOγ, the first bit pattern A. +
, each standard pattern A corresponding to.

al...AO is referred to in the same way as in the case of risk scan O described above. (5) Regarding the standard pattern AO7Salγ13a1γ corresponding to the number “8”)
Since the output of the AND gate 9-2 in the second matching circuit 6 becomes logic "1", it is not substantially referred to.

(6) Standard pattern AOδ corresponding to “But number 1”
Regarding a1δ...AOδ, the output of each AND gate 9-1, 9-2 in the second coincidence circuit 6 is the logic “o
”, so it is referenced.

) At the time of rescan 2, as described above, the rescan display pattern XO+1Xn+2 is given as "01".

In this case (7) Correctly written numbers “2” “8”,
Each standard pattern A corresponding to [9].

al...AO is referred to in the same way as in the case of risk scan 0 described above. (8) Regarding the standard pattern AOralγ...Anγ corresponding to the number "8",
Each AND gate 9-1, 9 in the second matching circuit 6
Since the output of -2 becomes logic "o", it is referred to.

(9) Standard pattern AOξ corresponding to “But number 1”
As for A, ξ, .

In this way, in the case of the present invention, for example, correctly written numbers "
Standard pattern 1 AO corresponding to 2, 8, and 9
aalα10ana′AOβ a1β13anβ,AO
ξ a1ξ . . . Anξ is a standard pattern A that is referred to in any of the risk scans, including risk scan 01, risk scan 1, and risk scan 2, and corresponds to the number "8" with some of the characters blurred.

ra, γ...Anγ are referenced only in the case of Riskan 2, that is, when the threshold level is set to a low level and preprocessing is performed, and the lower loop is a standard pattern corresponding to the number 1. A. aalδ...An
δ is referenced only in the case of risk scan 1, that is, when the threshold level is set to a high level and preprocessing is performed. Therefore, if the character to be recognized is the number "2" written correctly, the number "2" is
" Feature pattern XOXl... Standard pattern A corresponding to Xn and the number "8". ,,al,...AO, are not undesirably matched. That is, it is possible to prevent the number "2" from being mistakenly identified as the number "8".
Further, when the character to be identified is the correctly written number "9", the characteristic pattern X of the number "9" is determined when risk scan is 0. Xl . . . In other words, the number "9" above was mistakenly changed to the number "8".
” can be prevented from being identified as such. Also, the above numbers [
If "a" and "I" are characters to be recognized, they can be correctly identified as the number "8" in risk scan 2 and risk scan 1, respectively. As described above, in the present invention, the output of the first matching circuit 5 is masked by the output of the second matching circuit 6, and it is set in advance at which rescanning time each standard pattern should be referred to.

Therefore, it is possible to prevent the recognition target figure from being misread and to reduce the frequency of rejects.

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional pattern identification device, FIG. 2 shows an embodiment of the pattern identification device according to the present invention, FIG. 3 shows its main circuit diagram, and FIGS. 4A and 4B show diagrams explaining its operation. In the figure, 4 is a rescan control circuit, 5 is a first coincidence circuit,
6 is a second matching circuit, 8-0 to 8-(n+k) are respective exclusive OR gates, 9-1 to 9-k are respective AND gates, XOXl...Xn is a characteristic pattern, AO
al...AO is standard pattern, An+1...An+
k is the first bit pattern, Wn+1...Wn+k
The first one. 2 bit patterns, Xn+1...Xn+k
represents a rescan display pattern.

Claims (1)

[Scope of Claims] 1. A pattern for identifying the recognition target figure, which includes a first matching circuit that detects a match or mismatch between a feature pattern obtained by extracting features of the recognition target figure and a standard pattern prepared in advance. In the identification device, a matching instruction pattern is added in advance to the standard pattern to indicate which rescan the standard pattern should be referred to, and a rescan control circuit generates a rescan display pattern corresponding to the rescan; A second matching circuit is provided for detecting a match/mismatch between the matching instruction pattern and the rescan display pattern, and the output from the first matching circuit is masked by the second matching circuit. Pattern identification device. 2 The matching instruction pattern is composed of a first bit pattern and a second bit pattern, and the first matching circuit is configured to match each bit information of the feature pattern and the above corresponding to the feature pattern bit information. It is configured to compare each bit information of the standard pattern, and the second
The matching circuit is configured to compare the bit information of the rescan display pattern with the bit information of the first bit pattern and the bit information of the second bit pattern. The pattern identification device according to scope 1.