JPS592420B2 - Synchronous demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modulation/demodulation device for code transmission, and particularly to a synchronous demodulation method thereof.

Modulation methods for transmitting high-speed codes include phase shift keying (PSK) and quadrature amplitude modulation (QAM).
(plitudeModulation) is often used.

Since the PSK or QAM described above is well known, a general explanation thereof will be omitted, but in general, codes are transmitted by subcarriers, and in PSK, the phase of the subcarriers is set to an integer multiple of, for example, 900 in accordance with the code. In QAM, the phase and amplitude of subcarriers are simultaneously modulated and transmitted in accordance with the code. Therefore, in order to synchronously demodulate such a modulated signal, a phase synchronized subcarrier having the same frequency and phase as the above subcarrier is generated within the demodulation device, and this phase synchronized subcarrier and the above modulated signal are combined. must be multiplied. For example, code level “1”
When the modulated signal has a phase of cosωct and a phase of Slflωct corresponding to ``0'', multiplying the phase of the phase synchronized subcarrier as COS(jCt) yields (C
OS(De)2■1/2(1~C0S2ωct) and cos(!)s slnωct=1/2sln2ωc
Obtain the product of t, and pass these products through a low-pass filter (hereinafter LP).
(abbreviated as F), a constant output is obtained in the former case, and 0 in the latter case, so the original code can be reproduced. In addition, the phase of the phase synchronized subcarrier is set to Sl
If nωct, the above products are each slnωctco
sωct■1/2s1n2ωct, (51nC1)Ct
)2=1/2(1+cos2ωct), and the purpose of synchronous demodulation can be achieved in the same way. Generally, in the case of synchronous demodulation, two subcarriers (for example, COS(l)Ct and Sln(j)Ct) having a phase difference of 900 are generated simultaneously, and the phase is adjusted by multiplying the same modulated signal separately. It is well known that it is possible to synchronously demodulate signals whose amplitude and amplitude are modulated at the same time. This phase-synchronized subcarrier must be regenerated from the received signal, but it is difficult to directly regenerate the phase-synchronized subcarrier from a signal whose amplitude and phase are modulated at the same time, such as QAM, so it is usually used as an input signal to a sign determination circuit. A method is used in which phase error information is obtained from the output and the phase synchronization subcarrier and the phase of the phase synchronization subcarrier is corrected.

FIG. 1 is a plot diagram showing an example of a conventional synchronous demodulation device, and FIG. 2 is a plot diagram showing another example of a conventional synchronous demodulation device. In these figures, 1 indicates the input of the modulated signal. Terminals 2 and 3 are multipliers, 4 is a subcarrier generation circuit for synchronous demodulation, a VCO (voltage controlled oscillator) is used in the example shown in the figure, LPF17 is a timing extraction circuit, and 8 is a sampling circuit. 9 is a code determination circuit, 10 and 11 are output terminals for each determined code,
12 is a phase error detection circuit, 13 is a phase correction circuit, and 14 is a fixed frequency subcarrier generation circuit for synchronous demodulation.

Multiplier 2 receives the modulated signal from terminal 1 and COS (!).

A multiplier with a phase-locked subcarrier signal having a phase of t, multiplier 3 outputs the modulated signal and Slnω. It is a multiplier with a phase synchronized subcarrier signal having a phase of t, and the possible phases of the modulated signal are COSC! ). If t and c, then by passing the outputs of multipliers 2 and 3 through LPGs 5 and 6, respectively, baseband signals of the in-phase and quadrature components of QAM can be obtained. The timing extraction circuit 7 extracts a sampling pulse 5 from the baseband signal, that is, the demodulated signal obtained in this way, and applies this sampling pulse to the sampling circuit 8. The sampling circuit 8 includes LPF5 and LPF6.
The baseband signals output from the baseband signals are input, and each of these baseband signals is sampled by a sampling pulse. Codes 1, 2, 3, . 5, 6, 7
, 8 are the same in both the example of FIG. 1 and the example of FIG. In the example shown in FIG. 1, the output of the sampling circuit 8 is applied to a sign determination circuit 9, and determination outputs of the in-phase component and quadrature component are output from output terminals 10 and 11, respectively.

The signal to be transmitted is constructed based on a code having only two values: a logic "1" state and a logic "0" state. Therefore, the signals output from terminals 10 and 11 also have a logic "1" state.
Since it is constructed based on a code having two values of "and logic 0", the code determination circuit 9 can be constructed using this fact 4. For example, when the signal at the input terminal 1 of the modulated signal is in phase COs(!)Ct, the multiplier 2,
The phases of the phase-locked subcarriers input to 3 are COsO)Ct, sln(!), respectively. If t, LPF5,
The outputs of 6 will be logic "1" and logic "O" respectively, but if the phase of the phase synchronized subcarrier is shifted and the outputs of C
When Os(ωCt-△φ) and Sln(ω0t-△φ), the outputs of LPFs 5 and 6 are COsΔφ and Sl, respectively.
It is proportional to n△φ, resulting in a deviation from the logical levels of “1” and “0”. For example, in the example mentioned above, the sign determination circuit 9 sets the level of COsΔφ to logic ゜“1”.
The level of Sln△φ is determined as logic ゜“O゛.The input and output of the sign determination circuit 9 are also applied to a phase error detection circuit 12 to detect the phase error between the input baseband signal and the determination output. Information (in the above example a signal related to the angle Δφ) is output.

The phase error information is fed back to the VCO of the subcarrier generation circuit 4, and the phase of the phase synchronized subcarrier is corrected in a direction to reduce the phase error. In the example shown in FIG. 2, the synchronization subcarrier generation circuit 14 generates a fixed frequency phase synchronization subcarrier, and a phase correction circuit 13 is provided between the sampling circuit 8 and the sign determination circuit 9 to generate the phase synchronization subcarrier. Corrects the error caused in the demodulated signal due to phase shift,
At the output point of the phase correction circuit 13, the error remaining in the demodulated signal is automatically controlled to always have a value close to O.

For example, if the phase of the output voltage of the subcarrier generation circuit 14 is shifted by φ with respect to the modulated signal input from the human input terminal 1, the demodulated signal that should be “11,” O” becomes “COsφ”.
”, “Slnφ”, input these baseband signals and respectively output “COs(φ−φ”)”
It is output as a signal corresponding to Sln(φ-(!/)゛.

Therefore, the input of the phase error detection circuit 12 in FIG.
The signal corresponding to "n(φ-φ")" and the signal corresponding to "1", "0" of the output of the sign determination circuit 9, the error is equivalent to the phase error △φ=φ1φ" In the phase correction circuit 13, for example, φ5(n)=φ″(n-1)+β△φ
(n-1) (where n is the sampling time point NT of the sampling circuit 8 (
T is an integer representing the sampling period). β is a positive constant. ), this negative feedback loop operates as a so-called first-order PLL (PhaseLOckLOOp) with loop gain β/(j(l)T), and φ″(n)′− Automatic control is performed so that φ(n) is achieved.Actually, in a demodulator for high-speed code transmission of 4,800 bits/second or more, two-dimensional transversal equalization is performed after the sampling circuit 8. In addition, as disclosed in Patent Application No. 18317 of 1972 filed by the applicant, the two-dimensional transversal equalizer and the phase correction circuit 13 are designed to be integrated. However, a two-dimensional transversal equalizer with a phase correction function may be used in place of the phase correction circuit 13 in FIG. 2, but such an equalizer has no direct relation to the present invention. Therefore, its explanation will be omitted.

By the way, due to recent advances in digital IC technology, the circuit shown in FIG. 1 or 2 is often constructed from a digital circuit.

In this case, the modulated signal is digitally encoded using an A/D converter and applied to input terminal 1. In such a digital demodulator, the circuits of the multipliers 2 and 3 can be simplified by synchronizing the sampling frequency for A-D conversion and the subcarrier frequency for digitally encoding the modulated signal. It has the advantage of being able to For example, when the subcarrier frequency Fc is Fc=ωo/2π, the sampling period is Ts=π/2ωc, and the sampling time is t=NTs (n is an integer), then at the sampling time ωCt= It becomes nπ6, [(-1)1-1)i?
Since n=odd number, the only possible values for COs(!)Ct and SlnωCt are O and ±1, and it is easy to understand that the multiplier circuits 2 and 3 can be simplified.

In this case, the phase jitter of the sampling frequency of the digitally encoded modulated signal inputted from the input terminal 1 is required to be as small as possible.

In the method shown in Figure 1, if the subcarrier follows the phase jitter of the line, the phase jitter of the subcarrier becomes large, and in order to suppress the phase jitter of the subcarrier, it does not follow the phase jitter of the line, but only its average phase. This has the drawback that the phase error increases and code errors are more likely to occur. In the system of FIG. 2, the above-mentioned drawbacks of the system of FIG. 1 are eliminated, and errors due to line phase jitter are corrected by the phase correction circuit 13. Therefore, although the circuit shown in FIG. 2 is a circuit in which the synchronization subcarrier generation circuit 14 and the multipliers 2 and 3 can be simplified using a digital method, there is still room for improvement in terms of circuit simplification. Shortcomings remain.

The drawback is that the sampling pulse output from the timing extraction circuit 7 is not synchronized with the sampling frequency of the input signal, so each time point at which the input baseband signal should be sampled by the sampling circuit 8 is determined from the LPFs 5 and 6. The time point at which the baseband signal is output (this time point coincides with the time point at which the input signal is sampled by the above-mentioned A-D converter) does not necessarily coincide with the time point at which the baseband signal is output, and therefore the sampling circuit 8 It is necessary to perform interpolation calculations for estimating the value of the baseband signal at the time of sampling from the input baseband signals before and after the time of sampling, which complicates the sampling circuit 8. It is an object of the present invention to provide a demodulator which eliminates the above-mentioned drawbacks of conventional synchronous demodulators, eliminates the need for the interpolation calculations in the sampling circuit 8, and simplifies the circuitry of the demodulator.

The above objective can be achieved by synchronizing the output of the synchronization subcarrier oscillator (generally a signal for phase synchronization demodulation) with the sampling pulse that is the output of the timing extraction circuit 7. An example will be described. FIG. 3 is a block diagram showing an embodiment of the present invention, in which the same symbols as in FIG. 2 indicate the same parts, and 15 is a frequency divider/multiplier.

The frequency divider/multiplier 15 inputs the sampling pulse, which is the output of the timing extraction circuit 7, and receives one of its frequencies (here, M, N
is a synchronization subcarrier generator 15 that generates a voltage with a frequency of (each is a positive N integer) and applies it to the multipliers 2 and 3 as a phase synchronization subcarrier.

Therefore, the frequency divider/multiplier 15 may generate an output frequency by multiplying the input frequency by M or by N, or may synchronize the oscillation frequency of M independent oscillators with one of the input frequencies.

In this specification, the phase synchronization demodulation signal is referred to as being synchronized by the sampling pulse using a general expression, but the multiplication,
Needless to say, this also includes the case of frequency division. The circuit in FIG. 3 differs from the circuit in FIG. 2 in that instead of the fixed frequency demodulation subcarrier generation circuit 14, a frequency divider/multiplier 15 generates a phase synchronized subcarrier synchronized with the output frequency of the timing extraction circuit 7. This is the point.

For example, if the frequency of the output of the timing extraction circuit 7, that is, the sampling pulse, is 2,400 Hz and the subcarrier frequency is 1,800 Hz, M=3 and N=4 may be set in the frequency divider/multiplier 15.

When configuring a digital demodulator in this way, the subcarrier frequency Fc-ωo/2π-1,800
Hz, the sampling period for A-D conversion is T as described above.
If 8-π/2ωc-1/4fc, then COS (!).
t and Slnω. The possible values of t are O or ±1, and the synchronization subcarrier generation circuit 15 and multipliers 2 and 3
is extremely simplified, and the sampling period T of the sampling circuit is T-2400=3TS, an integer multiple of Ts, and Ts
is always synchronized with T, so there is no need to perform interpolation calculations in the sampling circuit 8, and the output signals of LPFs 5 and 6 are simply sampled (one pulse is extracted for every three consecutive input signal pulses). ), and the sampling circuit 8 is also extremely simplified. As can be easily understood from the above numerical example, it is advantageous for the values of M and N in the frequency divider/multiplier 15 to be both small integers for the purpose of simplifying the circuit of the synchronous demodulator.

As another numerical example, the frequency of the sampling pulse is 2,400H.
z, and the subcarrier frequency of the modulated signal input from terminal 1 is 1,700 Hz.
In this case, the output frequency Fc of the synchronization subcarrier oscillation circuit 15 is set to Fc-2400HzX-17141{z.

In this case, if the sampling period Ts for A-D conversion is chosen to be Ts=1, the sampling period T of sampling times 7fc conversion 8 is T=5
Ts, and no interpolation calculation is required.

ω at the sampling time t=NTs for the tampered AD conversion. t-2πn/7, and COS(!)Ct and S
There are 14 possible values for ln(1)Ct, and the subcarrier generation circuit 15 and multipliers 2 and 3 are slightly more complicated than in the case where the subcarrier is 1,800Hz, but ω0t
This is considerably simpler than the case where takes an arbitrary value. Generally, in the case of high-speed code transmission, the timing frequency for generating codes on the transmitting side is generated from a crystal oscillator and is extremely stable, and the timing extraction circuit 7 on the receiving side cannot follow such a stable timing frequency on the transmitting side. Since the output frequency of the frequency divider/multiplier 15 is good, the phase jitter can be sufficiently suppressed, and the phase jitter of the output frequency of the frequency divider/multiplier 15 is also sufficiently suppressed. Therefore, the operation of the phase correction circuit 13 in FIG. In the phase correction circuit 13 shown in the figure, the synchronization subcarrier oscillation circuit 1
4 is a fixed frequency phase synchronization subcarrier multiplication circuit 2
When added to , 3, the operation is similar to that of a tenon, and the performance is equivalent to that of a tenon.

As described above, according to the present invention, when constructing a digital synchronous demodulator, the circuit can be simplified without deteriorating the performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional synchronous demodulator, FIG. 2 is a block diagram showing another example of a conventional synchronous demodulator, and FIG. 3 is a block diagram showing an embodiment of the present invention. It is a diagram. In the figure, 1 is a manual terminal for the modulated signal, 2 and 3 are multipliers, and 4 is a subcarrier generation circuit for synchronous demodulation (VC
0), 5 and 6 are LPFs, 7 is a timing extraction circuit, 8 is a sampling circuit, 9 is a sign determination circuit,
10 and 11 are output terminals of the determined codes, respectively, and 12
13 is a phase error detection circuit, 13 is a phase correction circuit (or two-dimensional transversal equalizer with phase correction function), 14 is a subcarrier generation circuit for synchronous demodulation (using a fixed frequency oscillator), and 15 is a subcarrier for synchronous demodulation. This is a generation circuit (using a frequency divider/multiplier).

Claims (1)

[Claims] 1. In a synchronous demodulation device that extracts a sampling pulse from a demodulated signal that is synchronously demodulated by multiplying a modulated signal by a subcarrier for phase synchronous demodulation, and samples the demodulated signal using this sampling pulse, the synchronous demodulation device is given as a digital signal digitally encoded at a predetermined sampling period, and the means for multiplying this digital signal by the phase synchronization demodulation subcarrier is configured to multiply the value of the digital signal at each sampling point of the digital signal by the above-mentioned value. The subcarrier for phase synchronization demodulation includes means for multiplying the cosine and sine of the phase of the subcarrier for phase synchronization demodulation at the relevant point in time by digital numbers representing the cosine and sine of the phase of the subcarrier for phase synchronization demodulation. A synchronous demodulation device characterized by comprising means for synchronizing the number of digital numbers to be represented by a small number of types and to make the numbers simple.