JPS5924454B2 - light pen device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in light pen devices used in cathode bare tube display devices and the like.

As is well known, a light pen device is used to detect raster light from a cathode ray tube and read or write the contents stored in a refresh memory at an address corresponding to the screen coordinate position where the pen is applied.

The present invention provides an improvement in the case where the above-mentioned refresh memory is written in order to draw an arbitrary line on the screen by continuously moving such a light pen device to an arbitrary position on the screen coordinates. Regarding.

Generally, when performing such writing, the light pen is continuously moved on the screen in the horizontal (hereinafter referred to as X) or vertical (hereinafter referred to as Y) direction, and the write address in the refresh memory corresponds to this operation. It changes from moment to moment. Therefore, even when attempting to draw a line vertically or horizontally on the screen, the write address in the refresh memory may change due to slight shaking of the hand or errors in detecting the position of the line due to the characteristics of the light pen. , it was not easy to draw straight lines. The present invention has been made in view of these points,
The purpose of this device is to use a light pen device that can always draw in a straight line even when there is slight shaking of the hand when trying to draw handwritten lines on a cathode ray tube screen in the X or Y direction of the screen using a light pen. Our goal is to provide the following.

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the main parts of the device according to the embodiment of the present invention. For convenience of explanation, only the circuit that draws a straight line in the X direction of the screen will be described. In FIG. 1, reference numeral 1 denotes a well-known light pen, which has a built-in first switch, a photoelectric conversion circuit, etc., and operates the first switch by pressing it against the screen of a cathode ray tube (not shown), thereby activating the photoelectric conversion circuit, etc. , thereby converting the detected raster light into an electrical signal and outputting a light pen pulse LTPEN as shown in FIG. 2C.

Reference numeral 2 denotes a well-known X address counter, which outputs a count value indicating the position in the X direction of the screen (not shown) by counting the horizontal synchronizing signal HD.

Reference numeral 3 denotes an X latch circuit which latches the count value output from the X address counter by a latch pulse applied from an AND gate 4, which will be described later.

The count value latched by the latch circuit 3 is output to a well-known refresh memory or the like as address data indicating the X position coordinate of the screen. Reference numeral 5 denotes a gate circuit showing the main part of the present invention, which includes first, second, and third flip-flops 5 of D type.
1, 52, 53 and a NAND gate 54.

Further, SW2 is a manual second switch, which fixes the address data output from the X latch circuit 3 when in the on mode, and updates the latch data every vertical scanning period of the screen 1, that is, every field when in the off mode. The above-mentioned gate circuit 5 receives a vertical synchronizing signal VD as shown in FIG. 2A and a pen switch pulse PENSW as shown in FIG. The pen switch pulse PENSW is generated while the first switch built in the light pen 1 is activated and the photoelectric conversion circuit is activated to output the light pen pulse LTPEN, that is, when the light pen 1 is pressed against the screen. During this period, the level is maintained as shown in the opening of FIG. Note that 56 is a terminal to which the above-mentioned vertical synchronizing signal is input, and the symbols in the drawings below b1 and the overlines attached to the symbols indicating each signal indicate that they are significant at low level. The apparatus according to the embodiment of the present invention having the above-mentioned configuration generates a light pen pulse LT as shown in FIG. 23C when the light pen 1 is pressed against the screen.
PEN is applied to the latch circuit 3 via the AND gate 4, and the latch circuit 3 takes in the count value of the X address counter 2, whose count value is updated every horizontal scan of the screen, and the above-mentioned light pen pulse LTPEN is applied. Latch and output the count value when

The output of the latch circuit 3 is generally used as address data for the refresh memory and as data indicating the position coordinate in the X direction of the screen. Since these are well known in this type of device, details will be omitted. Next, the operation of the gate circuit 5, which is the main part of the present invention, will be explained. Now, when the second switch SW2 is in the off mode as shown in FIG. 1, one input terminal of the NAND gate 54 is maintained at the high level.
On the other hand, when the pen switch pulse PENSW shown at the beginning of FIG.
Since it is input to K, its output Q is inverted as shown in FIG. 2 at VD after the pen switch pulse PENSW rises. This output is input to the data input terminal D of the second flip-flop 52. Second flip-flop 52
Since the clock input terminal CK of the flip-flop 51 is supplied with VD in the same way as the first flip-flop 51, its output Q is determined by VD one field after the timing at which the first flip-flop 51 takes in data, as shown in FIG. Flip as shown. This output is input to the clock input terminal CK of the third flip-flop 53. Since the high-level pen switch pulse PENSW is applied to the clear input terminal CLR of the third flip-flop 53, its output Q
V1 is a low level output as shown in FIG. 2 and is applied to the other input terminal of the NAND gate 54. Since the second switch SW2 is in the off mode, the output of the NAND gate 54 is not at a high level and is applied to the clear input terminal CLR of the first flip-flop 51. As a result, the output Q of the first flip-flop 51 is not cleared and remains at the blank level as shown by the solid line in FIG. This output is branched and given to AND gate 4, which opens the gate. Therefore,
The light pen pulse LTPEN shown in FIG.
The signal is applied to the latch circuit 3 through the. This means that, as mentioned above, while the light pen 1 is pressed against the screen, the latch count value of the latch circuit 3 is updated for each vertical scanning period, in other words, for every field. It works the same way. Therefore, when the light pen 1 is removed from the screen, the pen switch pulse PENSW
falls as shown in the opening of Figure 2, so V immediately after this point
D is the clock input terminal CK of the first flip-flop 51
At the timing given to , the output Q is inverted to a low level as shown by the solid line in FIG.

The second flip-flop 52 inverts its output Q by being supplied with the next VD after the inverted output Q of the first flip-flop 51. On the other hand, since the pen switch pulse PENSW is applied to the clear input terminal CLK of the third flip-flop 53, PEN
It is cleared when SW is inverted to low level, and its output Q is inverted to low level as shown in FIG. At this time, since the output of the NAND gate 54 is output at the high level, the first flip-flop 51 is not cleared, and as mentioned above, the output Q is controlled by VD applied immediately after the pen switch pulse PENSW falls. It will be reversed. As a result, AND gate 4 closes the gate. Next, the case when the second switch SW2 is in the on mode will be explained.

At this time, one input terminal of the NAND gate 54 is maintained at a low level. When the light pen is pressed against the screen and a pen switch pulse PENSW is applied to the terminal 55, each of the first, second and third flip-flops 51
, 52, and 53 operate as described above. At this time, as the output Q of the third flip-flop 53 is inverted to low level, the output of the NAND gate 54 becomes low level and Clear. Therefore, the output Q remains at a high level only for one field period, and the AND gate 4 is opened. As a result, the X latch circuit 3 receives only one of the light pen pulses LTPEN output from the light pen 1 that passed while this gate was open, and the
Even if topen 1 continues to be pressed against the screen, the count value latched by the X latch circuit is not updated.

When the second switch SW2 is set to the on mode as described above, the count value output from the X address counter 2 is the light pen pulse of the next field when the first switch (not shown) of the light pen 1 is activated. LTPEN causes the latch circuit 3 to latch it once, and after that, the contents are held as they are.

Therefore, if the light pen 1 is moved in the Y direction at this time, the X position coordinate is initially fixed at the position where the light pen is applied, and only the Y direction position coordinate is changed from the circuit shown in FIG. It is updated by another equivalent circuit, not shown. As a result, a vertical straight line can be drawn on the screen by writing into the refresh memory corresponding to the picture element displayed on the screen based on the latch circuit outputs in the X and Y directions.

Furthermore, if the count value in the Y direction is fixed in exactly the same way as above, when the light pen is moved in the X direction, a horizontal straight line can be drawn.

In this way, the present invention provides a light pen device that can draw a straight line in a direction that is not fixed on the screen without causing camera shake by fixing either the X or Y position coordinates. It is something.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the main parts of a device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram of the main parts of the circuit shown in FIG. 2... Address counter, 1... Light pen (photoelectric conversion circuit, first switch), 3... Latch circuit, 5...
...Gate circuit, 4, SW2...second switch.

Claims (1)

[Claims] 1. A pair of address counters that rewrite horizontal and vertical address data representing coordinate positions on the screen of the cathode ray tube in synchronization with horizontal and vertical synchronization signals, respectively, and a light pen that is applied to the screen of the cathode ray tube. a cathode ray tube display comprising: a photoelectric conversion circuit that creates a pulse signal corresponding to the raster scanning light detected by the camera; and a latch circuit that latches the address data that is successively rewritten by the address counter using the pulse signal. In the apparatus, a first switch that operates the photoelectric conversion circuit; and a first switch that captures the vertical synchronization signal while the photoelectric conversion circuit is operated, and converts the first captured vertical synchronization signal to the next vertical synchronization signal. a gate circuit that extracts only the pulse signal of the photoelectric conversion circuit during a field period; and a gate circuit that selectively supplies either the pulse signal extracted by the gate circuit or the pulse signal of the photoelectric conversion circuit to the latch circuit. A light pen device comprising a second switch.