JPS5924543B2 - How to form electrode leads - Google Patents
How to form electrode leadsInfo
- Publication number
- JPS5924543B2 JPS5924543B2 JP54121154A JP12115479A JPS5924543B2 JP S5924543 B2 JPS5924543 B2 JP S5924543B2 JP 54121154 A JP54121154 A JP 54121154A JP 12115479 A JP12115479 A JP 12115479A JP S5924543 B2 JPS5924543 B2 JP S5924543B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- protrusion
- eutectic
- temperature
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/077—Connecting of TAB connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
近年、LSIの機能増大にしたがい、LSIの半導体素
子から導出されるリード端子の数も40〜80個におよ
び、従来の如く一本づつAU、At線によつて接続する
ワイヤボンディング方法では、ボンディングに使用され
る時間が前記電極端子数の増加とともに増大し、LSI
のコストを高めるばかDでなく、接続の信頼性も低下さ
せるものであつた。Detailed Description of the Invention In recent years, as the functions of LSIs have increased, the number of lead terminals derived from the semiconductor elements of LSIs has increased to 40 to 80, and they are no longer connected one by one by AU and At lines as in the past. In the wire bonding method, the time used for bonding increases as the number of electrode terminals increases.
Not only did it increase the cost of the connection, but it also reduced the reliability of the connection.
この様なワイヤボンディングの欠点を一掃するために、
ギャングボンディング法が開発され、実用化されてきた
、一般的な方法を第1図で説明する。In order to eliminate these drawbacks of wire bonding,
The general method by which the gang bonding method has been developed and put into practical use will be explained with reference to FIG.
ポリイミド樹脂フィルム1上に形成されたCuリード(
厚さ35μm)には0.2〜0.6μmの厚さにSnメ
ッキ層2が形成されている。Cu lead formed on polyimide resin film 1 (
A Sn plating layer 2 is formed to a thickness of 0.2 to 0.6 μm.
半導体基板4(44まSiO2膜)の電極端子上にはC
r(u、Th−Cu等の複数個からなる金属膜5(バリ
ヤメタルと呼ばれる)が真空蒸着法やスパッター蒸着法
等により形成され、更に前記金属膜5上に電解メッキ法
によりAu突起物6が10〜201Lmの厚さに形成さ
れる。前記Au突起物6は半導体素子の電極端子の位置
に電極端子の数だけ形成され、更に前記ポリイミド樹脂
フィルム上のCuリードは前記電極端子に合致する位置
まで延在されるものである。第1図の如く構成されたA
u突起物6と、Cuリード2とは互いに位置合せされC
uリード2側から480℃程度に加熱した治具で全Cu
リード2を一度に押えればAu−Snの共晶物(約28
0℃で発生)が発生し、前記治具を取り除けば、Au突
起物6とCuリード2とは完全に接続されることになる
。ところがこの様なAu・Snを用いる接続方法は接続
の強度や、高い信頼性を期特出来るものの、後述する第
2図に示す問題が発生する。なお、第1図においてb図
は、加熱治具50(例えばパルス的にボンディング時の
み加熱する治具もしくは、ヒーターを内蔵し、常時加熱
されている治具等がある。C on the electrode terminal of the semiconductor substrate 4 (SiO2 film 44)
A metal film 5 (referred to as a barrier metal) consisting of a plurality of materials such as r(u, Th-Cu, etc.) is formed by vacuum evaporation, sputter evaporation, etc., and Au protrusions 6 are further formed on the metal film 5 by electrolytic plating. The Au protrusions 6 are formed to have a thickness of 10 to 201 Lm.The Au protrusions 6 are formed at the positions of the electrode terminals of the semiconductor element by the number of electrode terminals, and the Cu leads on the polyimide resin film are formed at positions corresponding to the electrode terminals. A configured as shown in Figure 1.
The u protrusion 6 and the Cu lead 2 are aligned with each other.
All Cu is heated from the u-lead 2 side using a jig heated to about 480℃.
If lead 2 is pressed at once, Au-Sn eutectic (approximately 28
If the jig is removed, the Au protrusion 6 and the Cu lead 2 will be completely connected. However, although such a connection method using Au/Sn can ensure high connection strength and high reliability, problems occur as shown in FIG. 2, which will be described later. In FIG. 1, diagram b shows a heating jig 50 (for example, a jig that heats only during bonding in a pulsed manner, or a jig that has a built-in heater and is constantly heated).
)が降下してきて、Cuリード2とAu突起物6を加圧
し、前記Cuリード2とAu突起物6とを圧接した状態
である。次いで前記加熱治具50にパルス電流51を流
すと、前記加熱治具50は所定の温度までに瞬時に達す
る。この時、前記加熱治具50の温度はCuりード2か
ら、熱伝導率の良いAu突起物6を介して半導体基板4
の方へ逃ける事になる(矢印52)。このためにAu突
起物6と接しているCuリード2の部分53の温度は前
記加熱治具50で発生した温度よりも低くなるが、Au
突起物6と接していないCuリード2の部分54,54
′の温度はほぼ前記加熱治具50の温度と等しくなる。
すなわ′ち、Cuリードの部分53と54,54との間
に温度差が発生する。) descends and pressurizes the Cu lead 2 and the Au protrusion 6, bringing the Cu lead 2 and the Au protrusion 6 into pressure contact. Next, when a pulse current 51 is passed through the heating jig 50, the heating jig 50 instantly reaches a predetermined temperature. At this time, the temperature of the heating jig 50 is increased from the Cu lead 2 to the semiconductor substrate 4 via the Au protrusion 6 having good thermal conductivity.
(arrow 52). Therefore, the temperature of the portion 53 of the Cu lead 2 in contact with the Au protrusion 6 becomes lower than the temperature generated by the heating jig 50, but
Portions 54, 54 of the Cu lead 2 that are not in contact with the protrusion 6
The temperature of ' is approximately equal to the temperature of the heating jig 50.
That is, a temperature difference occurs between the Cu lead portions 53 and 54, 54.
この状態が瞬時(約500mS以内)に発生するために
Au−Snの共晶物はAu突起物6の端55,55′で
発生し、次いでAu突起物6の上53でこの部分の温度
がAu−Snの共晶温度(280℃)に達した後、発生
する。ところがAu突起物6上に発生した共晶物56は
第1図cの如くAu突起物6上のみに存在するが、瞬′
時に大量に出来たAu突起物6,7端55,55の共晶
物は第2図A,bに示した如く半導体基板4上に流れ落
ちる。Since this state occurs instantaneously (within about 500 mS), Au-Sn eutectic is generated at the ends 55, 55' of the Au protrusion 6, and then the temperature of this part increases at the top 53 of the Au protrusion 6. It occurs after reaching the Au-Sn eutectic temperature (280°C). However, the eutectic 56 generated on the Au protrusion 6 exists only on the Au protrusion 6 as shown in Fig.
At times, a large amount of the eutectic formed at the ends 55, 55 of the Au protrusions 6, 7 flows down onto the semiconductor substrate 4 as shown in FIGS. 2A and 2B.
これが共晶物により発生するクラツクの原因である。し
たがつてCuリード2上のSn層がAu突起物6よりは
み出すことがクラツクを発生させる原因である。これに
対し、′Au突起物6の端55,55で発生する共晶物
の発生量を極力押えるためにSnメツキの厚さを調整す
ることが容易に考えられる。This is the cause of cracks caused by eutectics. Therefore, the Sn layer on the Cu lead 2 protruding from the Au protrusion 6 is the cause of cracks. On the other hand, it is easy to consider adjusting the thickness of the Sn plating in order to suppress the amount of eutectic material generated at the ends 55, 55 of the Au protrusions 6 as much as possible.
一般に共晶物の発生量はSnメツキ厚さが厚く、加熱治
具50の温度が高い程発生しやすい。In general, the amount of eutectic generated is more likely to occur as the Sn plating thickness increases and the temperature of the heating jig 50 increases.
したがつて、Snメツキの厚さと、加熱温度の2つを制
御することが必要であるが、最も問題となることは、加
熱治具の温度分布の不均一性である。例えば加熱治具5
0のCuリードを加圧する側の寸法が2.4X6.0?
m(例えば4KbitRAMの寸法)とすれば、この様
な微少面積において、480℃の温度を前記2.4×6
.0mの全領域において均一にする事は著しく困難であ
る。加熱治具の端部においては放熱が激しく急激な温度
勾配を示す。第1図dは2.4×6.0mのパルスツー
ルでの実測値を示したものである。最初のAu−Sn共
晶を発生させるボンデイング条件が480℃であつたと
すれば中央附近では良いが周辺附近では余ジにも温度差
がありすぎる。周辺附近の温度415℃を480℃にす
るためには少なくとも、中央附近の温度を550〜56
0℃に高くしなければならない。この場合、加熱治具の
中央附近にあるAu突起物上では共晶物の発生量が著し
く大きくなシ、過剰の共晶物は、半導体基板4へ流れ落
ちクラツクの発生をまねくものである。又、第1図dの
如くの温度分布の場合、Snメツキ厚を厚くして、低い
温度でも共晶を作らせる事が出来るが、415℃附近で
は適量の共晶物が出来ても、480℃附近では、Snメ
ツキ厚さが厚いから、その分だけ共晶物の量が多くなつ
てしまい、結果的に、クラツクの発生をまねくものであ
る。すなわち、Snメツキ厚さを調整するにしても加熱
治具の温度分布を度外視する事が出来ないので、根本的
な解決策とはならない。第2図AVC}いて、Au突起
物6とCuリード2とはAu・Snの共晶物7′によつ
て接続されているが、前記共晶物7′/)く発生する瞬
間に余剰に発生した共晶物7は半導体基板4のSiO2
膜4′1,に瞬′間的に落下する。Therefore, it is necessary to control the thickness of the Sn plating and the heating temperature, but the biggest problem is the non-uniformity of the temperature distribution of the heating jig. For example, heating jig 5
The dimensions of the side that pressurizes the Cu lead of 0 are 2.4X6.0?
m (for example, the dimensions of a 4Kbit RAM), in such a small area, the temperature of 480°C is
.. It is extremely difficult to achieve uniformity over the entire 0 m area. At the end of the heating jig, heat radiation is intense and a sharp temperature gradient is exhibited. FIG. 1d shows actual measured values using a 2.4 x 6.0 m pulse tool. If the bonding conditions for generating the initial Au--Sn eutectic were 480 DEG C., it would be fine near the center, but there would be too much temperature difference near the periphery. In order to increase the temperature near the periphery from 415°C to 480°C, the temperature near the center must be at least 550-56°C.
The temperature must be raised to 0°C. In this case, the amount of eutectic produced is extremely large on the Au protrusion near the center of the heating jig, and the excess eutectic flows down onto the semiconductor substrate 4, causing cracks. In addition, in the case of the temperature distribution as shown in Figure 1 d, it is possible to increase the Sn plating thickness and form a eutectic even at a low temperature, but at around 415°C, even if a suitable amount of eutectic is formed, the ℃, the Sn plating is thick, so the amount of eutectic increases accordingly, which results in the occurrence of cracks. That is, even if the Sn plating thickness is adjusted, the temperature distribution of the heating jig cannot be ignored, so this is not a fundamental solution. Fig. 2 AVC}, the Au protrusion 6 and the Cu lead 2 are connected by the Au/Sn eutectic 7', but at the moment the eutectic 7'/) is generated, the red The generated eutectic 7 is SiO2 of the semiconductor substrate 4.
It falls instantaneously onto the film 4'1.
この時に前記SiO2膜4、半導体基板4あるいはバリ
ヤメタル5との熱膨張の差により瞬時にクラツク8を発
生せしめる。前記クラツク8はCuリード2の引張強度
を著しく低下する一方、半導体基板4内に形成されてい
るP・N接合を損傷してしまい、電気的特性の低下をま
ねくものであつた。又、前記Au突起物6と半導体基板
4の端が比較的接近している様な構成にあつては、第2
図bに示す如く共晶物9が、半導体基板4の端まで流れ
出し、半導体基板4と接触(矢印10で示した)してし
まい、電気的に短絡する問題を発生させていた。本発明
はAu−Sn共晶によつて接続を行なうギャングボンデ
イングに}いて、前述した如くの共晶物の余剰物による
半導体基板のクラツクや、共晶物と半導体基板との短絡
を積極的に防止した信頼性の高いリード形成方法を提供
せんとするものである。At this time, cracks 8 are instantaneously generated due to the difference in thermal expansion between the SiO2 film 4, the semiconductor substrate 4, or the barrier metal 5. The cracks 8 significantly reduced the tensile strength of the Cu lead 2, and also damaged the P/N junction formed in the semiconductor substrate 4, leading to a decrease in electrical characteristics. In addition, in a configuration where the Au protrusion 6 and the edge of the semiconductor substrate 4 are relatively close to each other, the second
As shown in FIG. b, the eutectic 9 flows out to the edge of the semiconductor substrate 4 and comes into contact with the semiconductor substrate 4 (indicated by arrow 10), causing an electrical short circuit problem. The present invention actively prevents cracks in the semiconductor substrate caused by excess eutectic material and short circuits between the eutectic material and the semiconductor substrate in gang bonding that uses Au-Sn eutectic material for connection. It is an object of the present invention to provide a highly reliable lead formation method that prevents the above problems.
第3図で本発明の構成を示す。FIG. 3 shows the configuration of the present invention.
ポリイミド樹脂1上にCuリード2が形成された後、0
.2〜0.8μmの厚さにSnメツキ3が施こされる。After Cu lead 2 is formed on polyimide resin 1, 0
.. Sn plating 3 is applied to a thickness of 2 to 0.8 μm.
前記Cuリード2は半導体素子11上の電極端子と合致
する位置に設けられるものである。前記Cuリードの成
型は凹部をもつメス金型4と凸部をもつオス金型5とを
押圧することによつて第3図bの如くCuリード2の先
端をL字形に成形出来る。凹部をもつメス金型4の巾A
は第3図bの相対するAu突起物12と12仙の長さB
よりも小さく作られるものである。又凸部をもつオス金
型5の巾Cは成形後のCuリード間隔Dと等しくなる。
成形後のCuリード2の寸法でFは相対するAu突起物
12,12′の内側の寸法Gよりも大きく、寸法HはA
u突起物12,12′の外側の寸法Bよりも小さく設計
されるものである。更に成形前のCuリード2間の寸法
Eは、成形後の寸法Fよりも小さく設計されているもの
である。又、第3図BVC卦いて半導体素子11のAu
突起物12は10〜20μmの厚さにAuメツキ法で形
成され、Cr−Cu,Th−Cu等の複数層で形成した
バリヤメタル13上に設けられるものである。第3図c
において、成形されたCuリード2の先端の寸法1は、
Au突起物12の寸法Jよりも小さく形成されるもので
ある。例えばJが100μmであればIは70〜80μ
mに成形される。更にAu突起物12に成形したCuリ
ード2を位置合せする場合には、前記成形したCuリー
ドの先端が、Au突起物よりはみ出すことなく行なわれ
、加熱(480℃程度)した治具で加圧すればAu−S
nの共晶物14を発生させ、前記Cuりード2とAu突
起物12とが接続されるものである。前記共晶物14は
形成されたCuリード2の寸法1がAu突起物の長さJ
よりも短いので、余剰のAu−Sn共晶物14が発生せ
ず殆んど前記Au突起物12の上で止まつてしまう。共
晶物が半導体基板へ流れ出し、従来発生していた、半導
体基板のクラツクの発生による電気的特性の低下や、流
れ出した共晶物と半導体基板との接触する事故が発生し
ない。このために信頼性の高いリード接続を行なう事が
出来るものである。The Cu lead 2 is provided at a position that matches the electrode terminal on the semiconductor element 11. To mold the Cu lead, the tip of the Cu lead 2 can be molded into an L-shape as shown in FIG. 3b by pressing a female mold 4 having a concave portion and a male mold 5 having a convex portion. Width A of female mold 4 with recess
is the length B of the opposing Au protrusions 12 and 12 in Fig. 3b.
It is made smaller than. Further, the width C of the male mold 5 having the convex portion is equal to the Cu lead interval D after molding.
The dimension F of the Cu lead 2 after molding is larger than the inner dimension G of the opposing Au protrusions 12, 12', and the dimension H is A.
It is designed to be smaller than the outer dimension B of the u projections 12, 12'. Furthermore, the dimension E between the Cu leads 2 before molding is designed to be smaller than the dimension F after molding. In addition, the BVC diagram in FIG.
The protrusion 12 is formed by Au plating to a thickness of 10 to 20 μm, and is provided on a barrier metal 13 formed of multiple layers of Cr-Cu, Th-Cu, and the like. Figure 3c
In, the dimension 1 of the tip of the molded Cu lead 2 is:
It is formed to be smaller than the dimension J of the Au protrusion 12. For example, if J is 100 μm, I is 70 to 80 μm.
It is formed into m. Furthermore, when positioning the molded Cu lead 2 to the Au protrusion 12, the tip of the molded Cu lead should not protrude from the Au protrusion, and be pressed with a heated jig (approximately 480°C). Then Au-S
The Cu lead 2 and the Au protrusion 12 are connected by generating n eutectic 14. The eutectic 14 is such that the dimension 1 of the formed Cu lead 2 is the length J of the Au protrusion.
Since the Au--Sn eutectic 14 is shorter than the above-mentioned Au protrusion 12, the surplus Au--Sn eutectic 14 is not generated and almost stops on the Au protrusion 12. The eutectic flows out onto the semiconductor substrate, and the deterioration of electrical characteristics due to the generation of cracks in the semiconductor substrate, which conventionally occur, and accidents where the flowing eutectic comes into contact with the semiconductor substrate do not occur. For this reason, highly reliable lead connections can be made.
第1図A,b,cは従来例の構成断面図、同図dは温度
分布を示す図、第2図A,bは従来例のボンデイングに
よる問題を示す断面図、第3図A,b,cは本発明の一
実施例における工程断面図である。
1・・・・・・ポリイミド樹脂、2・・・・・・Cuリ
ード、3′・・・・・・Snメツキ、11・・・・・・
半導体素子、12,12・・・・・・Au突起物。Figures 1A, b, and c are cross-sectional views of the structure of the conventional example, Figure d is a diagram showing the temperature distribution, Figures 2A and b are sectional views showing problems caused by bonding in the conventional example, and Figures 3A, b. , c are process sectional views in one embodiment of the present invention. 1...Polyimide resin, 2...Cu lead, 3'...Sn plating, 11...
Semiconductor element, 12, 12...Au protrusion.
Claims (1)
フィルムテープ上に設けたSnメッキしたCuリードと
をギャングボンディングする方法において、前記Cuリ
ードの延在方向の先端領域で、厚み方向に折曲げて段部
を設け前記Au突起物と接する前記Cuリードの折曲げ
た先端領域を前記Au突起物の長さよりも小さく成形し
た後、前記Cuリードの折曲げた先端領域が、前記Au
突起物からはみ出すことなくギャングボンディングする
ことにより電極リードを形成することを特徴とする電極
リードの形成方法。1. In a method of gang bonding an Au protrusion provided on an electrode terminal on a semiconductor element and a Sn-plated Cu lead provided on a resin film tape, the Cu lead is folded in the thickness direction at the tip region in the extending direction. After forming a bent tip region of the Cu lead which is bent to form a step and is in contact with the Au protrusion to be smaller than the length of the Au protrusion, the bent tip region of the Cu lead is formed into the Au protrusion.
A method for forming an electrode lead, characterized in that the electrode lead is formed by gang bonding without protruding from a protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54121154A JPS5924543B2 (en) | 1979-09-19 | 1979-09-19 | How to form electrode leads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54121154A JPS5924543B2 (en) | 1979-09-19 | 1979-09-19 | How to form electrode leads |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5645042A JPS5645042A (en) | 1981-04-24 |
| JPS5924543B2 true JPS5924543B2 (en) | 1984-06-09 |
Family
ID=14804179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54121154A Expired JPS5924543B2 (en) | 1979-09-19 | 1979-09-19 | How to form electrode leads |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5924543B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6386534A (en) * | 1986-09-30 | 1988-04-16 | Toshiba Corp | Film carrier and manufacture thereof |
-
1979
- 1979-09-19 JP JP54121154A patent/JPS5924543B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5645042A (en) | 1981-04-24 |
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