JPS5924628B2 - Switching stabilized power supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching stabilization power supply circuit suitable for use as a power supply for various electronic devices, and in particular to a switching stabilization power supply circuit that can be used over a wide range of input voltages and that keeps switching elements within a safe operating range. It is designed to operate internally to prevent damage to switching elements, etc.

2. Description of the Related Art Conventionally, a switching stabilization power supply circuit as shown in FIG. 1 has been proposed, which is used as a power source for various electronic devices.

That is, in FIG. 1, 1 indicates a commercial power source, one end of which is grounded, and the other end is grounded via a series circuit of a rectifying diode 2a and a capacitor 2b that constitute a rectifying circuit 2. The grounding points of the diode 2a and the capacitor 2b are connected to one end of the primary winding 3a of the output transformer 3, and the other end of the primary winding 3a of the output transformer 3 is connected to the ground point of the npn type transistor 4 constituting the switching element. The emitter of this transistor 4 is grounded.

Further, one end of the secondary winding 3b of this output transformer 3 is connected to the common terminal 5, and the other end is connected to a rectifying diode 6a), a smoothing coil 6b, and a smoothing capacitor 6 that constitute a rectifying circuit 6.
It is connected to the common terminal 5 through a series circuit of c, and an output terminal T is derived from the mutual connection point of the coil 6b and capacitor 6c.

Further, the output DC voltage obtained at the output terminal T is supplied as a detected voltage to one input terminal of the error amplifier 8, and a reference voltage is supplied from the reference voltage supply circuit 9 to the other input terminal of the error amplifier 8. . In this case, a voltage corresponding to the difference between the detected voltage and the reference voltage supplied from the output terminal of the error amplifier 8 to one and the other input terminals of the error amplifier 8, that is, the output voltage obtained at the output terminal 7. A voltage corresponding to the voltage is output. Further, the output terminal of this error amplifier 8 is connected to a modulation signal input terminal 10a of a pulse width modulation circuit 10, and the input terminal 10b of this pulse width modulation circuit 10 is connected to the positive electrode of a battery 11 that supplies a predetermined voltage Vo. This battery 1
1 is connected to the common terminal 5.

In this case, the pulse width modulation circuit 10 is constructed as shown in FIG. That is, in FIG. 2, 10d indicates a sawtooth wave generation circuit that generates a sawtooth wave signal of a predetermined frequency, and the sawtooth wave signal output from this sawtooth wave generation circuit 10d is sent to a level detection circuit 10e and The modulation signal input terminal 10a is connected to the reference voltage supply terminal of the level detection circuit 10e, and the input terminal 10b is connected to the reference voltage supply terminal of the level detection circuit 10f. Connect to the terminal.

Further, the output terminal of this level detection circuit 10e is connected to one input terminal of an AND circuit 10g, and the output terminal of this level detection circuit 10f is connected to the other input terminal of the AND circuit 10g via an inverter circuit 10h. An output terminal 10c is derived from the output terminal of this AND circuit 10g. In this case, the level of the sawtooth wave signal supplied from the sawtooth wave generation circuit 10d is supplied from the output terminal of the level detection circuit 10e to the reference voltage supply terminal of the level detection circuit 10e from the modulation signal input terminal 10a. outputs a high level signal 11' only when the level is higher than the level of the reference voltage Ve,
During the other periods, it is configured to output a low level signal "O", and the level detection circuit 10f is configured by, for example, a monostable multivibrator, and normally the low level signal 60" is output.
When the level of the sawtooth wave signal supplied from the sawtooth wave generation circuit 10d exceeds the level of the predetermined voltage o supplied from the input terminal 10b to the reference voltage flood terminal of the level detection circuit 10f. High level signal 6 triggered by
1", and outputs a pulse signal (a pulse signal whose falling edge is synchronized with the lowest level of the sawtooth signal) having a predetermined pulse width γ. In this way,
The pulse width modulation circuit 10 is constructed, and its operation will be explained below using FIG. First, level detection circuit 1
When the voltage Vel corresponding to the output voltage obtained at the output terminal 7 is supplied to the reference voltage supply terminal 0e, the voltage Vel shown in FIG.
A sawtooth wave signal as shown in FIG. 1 is supplied to the level detection circuit 10f, and since the reference voltage VO is supplied to the reference voltage supply terminal of this level detection circuit 10f, the output terminal of this level detection circuit 10f is The pulse width γ sets the falling timing as shown in FIG. 3B. It is possible to obtain a pulse signal having . Further, a sawtooth wave signal as shown in FIG. is supplied to the output terminal of the level detection circuit 10e, a signal as shown by the solid line C1 in FIG. 3C can be obtained at the output terminal of the level detection circuit 10e. Therefore, one input terminal of the AND circuit 10g is supplied with a signal as shown by the solid line C1 in FIG. 3C, and the other input terminal of the AND circuit 10g is supplied with an inverted signal as shown in FIG. 3B. Since a signal as shown in FIG. 3D is supplied, a pulse signal having a pulse width γ1 whose falling edge is at a constant position P1 as shown by the solid line e1 in FIG. 3E is obtained at the output terminal 10c. Further, the value of the reference voltage supplied to the reference voltage supply terminal of the level detection circuit 10e is Ve2(
Ve2 (Vel), a signal as shown by the broken line C2 in FIG. 3C is obtained at the output terminal of this level detection circuit 10e, and therefore, a signal as shown by the broken line C2 in FIG. 3E is obtained at the output terminal 10c. A pulse signal having a pulse width γ2 (γ2>γ1) with a falling edge at a constant position P1 as shown in E2 is obtained. In this way, the output terminal 1 of this pulse width modulation circuit 10
0c is the input terminal 10a of this pulse width modulation circuit 10.
Depending on the output voltage obtained at the output terminal 7 supplied to
A pulse signal whose pulse width is variable can be obtained. That is, when the output voltage is smaller than the reference voltage supplied from the reference voltage supply circuit 9, the level of the voltage e supplied from the error amplifier 8 to the input terminal 10a becomes small, so that the pulse width modulation circuit 10 The pulse width of the pulse signal obtained at the output terminal 10c becomes wider, and conversely, when the output voltage is greater than the reference voltage, the level of the voltage e supplied from the error amplifier 8 to the input terminal 10a becomes large. The pulse width of the pulse signal obtained at the output terminal 10c of the pulse width modulation circuit 10 becomes narrower. Further, the output terminal 10c of the pulse width modulation circuit 10 is connected to the input terminal of the pulse transformer drive circuit 12, and the pulse signal obtained at the output side of the pulse transformer drive circuit 12 is transmitted to one of the pulse transformers 13.
One end of the secondary winding 13b of this pulse transformer 13 is grounded, and the other end of the secondary winding 13b of this pulse transformer 13 is connected to the base of the transistor 4.

The operation of the conventional example shown in FIG. 1 will be explained below.

When the power is turned on, a pulse signal is supplied from the output terminal 10c of the pulse width modulation circuit 10 to the pulse transformer drive circuit 12. The transistor 4 is turned on and off by FhI, and at this time, the output signal of the transistor 4 turns the output transformer 3 on and off.
is driven, so the secondary winding 3b of this output transformer 3
By rectifying this output signal via the rectifier circuit 6, an output DC voltage can be obtained at the output terminal 7.

In this case, the output DC voltage obtained at the output terminal 7 is supplied to one input terminal of the error amplifier 8, and the error amplifier 8 supplies this output DC voltage and a reference voltage to the other input terminal of the error amplifier 8. An error voltage corresponding to the difference from the reference voltage supplied from the circuit 9 is output, and the pulse width modulation circuit 1
0 input terminal 10a, a pulse signal having a pulse width corresponding to the output DC voltage is output from the output terminal 10c of this pulse width modulation circuit 10, and the transistor 4 is turned on and off according to this pulse signal. Since the output terminal 7 has the Fjl leg, a stable DC voltage of a predetermined value determined by the reference voltage from the reference voltage supply circuit 9 can be obtained from the output terminal 7. If the switching stabilization power supply circuit as shown in FIG. 1 is used, when the input voltage is high, the output DC voltage will also increase accordingly. Since the width becomes narrower, the on-time of the transistor 4 is controlled to be shorter, and the output DC voltage is lowered, and when the input voltage is low, the output DC voltage is also lowered accordingly. As a result, the pulse width of the output pulse signal of the pulse width modulation circuit 10 becomes wider, so that the transistor 4
Since the leg is operated in the direction of increasing the output DC voltage so that the ON time of the
Even if the voltage is OO to AC26OV, a stable DC voltage of a predetermined value can be obtained from the output terminal 7.

Therefore, the same general-purpose switching stabilization power supply circuit as shown in FIG. 1 can be used in countries around the world where the voltage values of commercial power sources are different. However, when the input voltage is high, for example AC 26O', and the ON time of the transistor 4 is short, for example, if the load becomes abnormally heavy,
Since the output DC voltage drops rapidly, in order to maintain the output DC voltage at a predetermined value, the current must first increase within the allowable range of the current amplification block Fe determined by this transistor 4. If the value of the output voltage does not reach the predetermined value even if this current exceeds the allowable range, the ON time of the transistor 4 is lengthened (the output of the pulse width modulation circuit 10 is The output DC voltage is controlled to a predetermined value (by widening the pulse width of the pulse signal output from the terminal 10c).

Therefore, in this case, a high voltage is applied to the transistor 4, and the current flows for a long time, and the power supplied to the transistor 4 becomes large, exceeding the safe operating area of the transistor 4, and causing the transistor 4 to fail. There was a risk that it would be destroyed.

In view of this, the present invention is designed to prevent the switching element from being destroyed even when the input voltage is high. Hereinafter, an embodiment of the switching stabilized power supply circuit of the present invention will be described with reference to FIG.

In FIG. 4, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In FIG. 4, the mutual connection point of the diode 6a and the coil 6b is connected to the common terminal 5 through a series circuit of a diode 14a and a capacitor 14b that constitute a peak value detection circuit 14 for detecting the input voltage value. , the connection point of this diode 14a and capacitor 14b is connected to the cathode of a Zener diode 15 for level shifting, the anode of this Zener diode 15 is connected to the anode of a backflow prevention diode 16, and the cathode of this diode 16 is connected to the cathode of a Zener diode 15 for level shifting. Connected to the modulation signal input terminal 10a of the pulse width modulation circuit 10. In this case, since the peak value detection circuit 14 is configured by the diode 14a and the capacitor 14b, a voltage corresponding to the input voltage of the commercial power supply 1 can be obtained at the connection point between the diode 14a and the capacitor 14b. The modulation signal input terminal 10a of the pulse width modulation circuit 10 receives a voltage drop due to the Zener diode 15 and a forward voltage drop due to the diode 16 from the voltage obtained at the connection point of the diode 14a and the capacitor 14b. A voltage i corresponding to the input voltage is supplied. In this case, a Zener diode 15 with an appropriate Zener voltage value is selected for each input voltage, and the diode 14a is
A voltage V is supplied from the connection point of the capacitor 14b to the input terminal 10a of the pulse width modulation circuit 10 through the series circuit of the Zener diode 15 and the diode 16.
The value of i can be chosen appropriately.

As this voltage Vi, the level detection circuit 10e of the pulse width modulation circuit 10 uses this voltage Vi as a reference voltage.
When supplying the reference voltage to the reference voltage supply terminal of
The Noddles signal having the maximum pulse width γMax, which is controlled on and off in the same manner, is set to such a value as to be output from the output terminal 10c of the pulse width modulation circuit 10. Also, the error amplifier 8
The voltage Ve corresponding to the output voltage supplied to the modulation signal input terminal 10a of the pulse width modulation circuit 10 and the diode 1
When the voltage Vi supplied to the modulation signal input terminal 10a of the pulse width modulation circuit 10 from the connection point of the 4a and the capacitor 14b through the series circuit of the Zener diode 15 and the diode 16 has a relationship of Vi≦Ve, The value of the reference voltage supplied to the reference voltage supply terminal of the level detection circuit 10e as shown in FIG. 2 is Ve, and when the relationship i>Ve exists, the reference voltage of the level detection circuit 10e as shown in FIG. The value of the reference voltage supplied to the supply terminal is Vi.

The rest of the structure is the same as in FIG. 1. The operation of FIG. 4 will be explained below with reference to FIGS. 5 and 6.

That is, when Vi≦Ve (when the output voltage fluctuates within a steady range with respect to the input voltage and the transistor 4 attempts to operate only within the safe operating area), the level detection circuit 1
Since the value of the reference voltage supplied to the reference voltage input terminal 0e is the voltage Ve corresponding to the output voltage supplied from the error amplifier 8, the pulse of the pulse signal output from the output terminal 10c of the pulse width modulation circuit 10 The width is controlled by the voltage Ve supplied from the error amplifier 8 to the modulation signal input terminal 10a of the pulse width modulation circuit 10.

That is, a sawtooth wave signal as shown in FIG. 5A is supplied to the level detection circuits 10e and 10f, and the level detection circuit 10
f is the pulse width γ for setting the falling timing as shown in FIG. 5B. Since the level detection circuit 10e outputs a pulse signal as shown in FIG. 5C according to the voltage e, the output terminal 10c receives a pulse signal as shown in FIG. A pulse signal having a controlled pulse width γ3 is thus obtained. Therefore, in this case, the embodiment shown in FIG. 4 is similar to the conventional example shown in FIG. The transistor 4 is turned on and off by the pulse signal, and a stable DC voltage of a predetermined value can be obtained from the output terminal 7. Also, when Vi>Ve (when the load becomes abnormally heavy, the output DC voltage abnormally decreases with respect to the input voltage,
In order to set the output DC voltage to a predetermined value, a pulse width modulation circuit 1 is used.
When attempting to operate beyond the safe operating area of the transistor 4 by increasing the pulse width of the pulse signal output from the output terminal 10c of the transistor 4 to increase the on-time of the transistor 4, the level detection circuit 10e is used. Since the value of the reference voltage supplied to the reference voltage input terminal of the pulse width modulation circuit 10 is Vi, the pulse width of the pulse signal output from the output terminal 10c of the pulse width modulation circuit 10 is equal to Pulse width modulation circuit 1 via a series circuit of Zener diode 15 and diode 16
It is controlled by the voltage Vi corresponding to the input voltage supplied to the modulation signal input terminal 10a of 0. In other words,
Is the sawtooth wave signal as shown in FIG. 6A? le detection circuit 10
e and 10f, and from this level detection circuit 10f, a pulse width γ for setting the fall timing as shown in FIG. 6B is supplied. Since the level detection circuit 10e outputs a pulse signal as shown in FIG. 6C according to the voltage Vi, the output terminal 10c has a voltage Vi as shown in FIG. 6D. Therefore, the controlled pulse width γM
A pulse signal of ax (maximum pulse width that is controlled on and off so that transistor 4 does not exceed the safe operating area with respect to the input voltage at that time) is obtained. Therefore, when the output voltage drops abnormally, Even if the voltage Ve becomes small and the pulse width of the pulse signal output from the pulse width modulation circuit 10 is increased to lengthen the ON time of the transistor 4 and the output voltage is set to a predetermined value, Ve<Vi (safety of the transistor 4) When the pulse width of the pulse signal output from the pulse width modulation circuit 10 becomes γNla (maximum pulse width that controls on/off of transistor 4), and transistor 4 will never operate outside its safe operating area. Furthermore, when the input voltage becomes higher, the voltage i increases accordingly, so the safe operation area is determined according to the input voltage. As mentioned above, when the input voltage is high and the load becomes abnormally heavy and the output voltage drops abnormally, in the conventional example shown in FIG. 1, the on-time of the transistor 4 becomes longer than necessary.
In other words, this transistor 4 would operate outside the safe operating area, and there was a risk that this transistor 4 would be destroyed, but according to the present invention, this transistor 4 would operate outside the safe operating area. Since the on-time of this transistor 4 is controlled according to the input voltage so that it operates at
Since this transistor 4 always operates within the safe operating area, there is no risk of it being destroyed, and even when the load becomes abnormally heavy and the output voltage drops abnormally, this transistor 4
can be protected.

According to the invention, therefore, a wide range of eg AClOOV-AC
It can also be used for an input voltage of 26OV, and has the advantage that the same general meter can be used in many countries around the world. Note that the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations may be adopted without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an example of a conventional switching regulated power supply circuit, FIGS. 2 and 3 are diagrams for explaining the same, and FIG. 4 shows an embodiment of the switching regulated power supply circuit of the present invention. The configuration diagrams shown in FIGS. 5 and 6 are diagrams for explaining the present invention, respectively. 1 is a commercial power supply, 3 is an output transformer, 4 is a transistor,
5 is a common terminal, 6 is a rectifier circuit, 7 is an output terminal, 10 is a pulse width modulation circuit, 14 is a detection circuit, and 15 is a Zener diode.

Claims (1)

[Claims] 1. A switching element that intermittents the input DC current, an output transformer driven by the output signal of this switching element, a rectifier circuit that rectifies the output signal of this output transformer, and the difference between the output voltage of this rectifier circuit and a reference voltage. It has an error amplifier that generates an output according to the output of the error amplifier, and a pulse width modulation circuit that generates a pulse width modulation signal with a pulse width that corresponds to the output of the error amplifier. In the switching stabilized power supply circuit, the switching stabilized power supply circuit controls the on/off of the switching element so that the on period of the switching element becomes longer when the output of the switching element decreases, wherein the pulse width modulation circuit has a predetermined pulse width of the pulse width modulation signal. A pulse width limiting circuit is provided to prevent the width from exceeding the pulse width limiting circuit, and input voltage detecting means is provided to detect the input voltage and to further narrow the predetermined width determined by the pulse width limiting circuit as the input voltage increases. A switching stabilized power supply circuit characterized in that: