JPS5925226B2 - Character graphic display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character and graphic display device equipped with means for pseudo-parallel processing of the contents of a plurality of series of memories.

In recent years, with the advancement of highly integrated semiconductor technology, LSIs (hereinafter abbreviated as MPUs), which form the central processing unit of electronic computers on one chip, have become available in large quantities at low prices. Ultra-compact electronic computers that are equipped with memory input/output devices and operate independently have become available for personal and small-scale business use.

These generally have a key port as an input device and a cathode ray tube display device (hereinafter abbreviated as CRT) as an output device, and display information input from a keyboard and characters and figures created by a program on the CRT screen. These relatively small-sized computers generally use MPUs capable of 8-bit parallel processing in terms of processing power, memory, and other costs. However, 8-bit parallel data is sometimes insufficient for display purposes.

For example, the character codes for alphabets, numbers, kana, etc. specified by JIS are represented by 8 bits. If you try to color this character by character and display it in color on a CRT screen, for example, if you try to display only the character part in 16 colors, it will be 10g2
16 = 4 bits, and if you want to display the background and characters in 16 colors each, add 4 x 2 = 8 bits of color memory in parallel with the display memory, and when displaying, use 12 or 16 bits together with the character code. Must be read as parallel data. A case in which the above-mentioned functions are configured using conventional technology will be explained using FIG. 1. Figure 1 shows
1 is a block diagram showing the configuration of a character/graphics display device using a two-series memory read/write method according to the prior art; FIG.

In FIG. 1, 1 is MPU12 a data bus, 3 is an address bus, 4 is a main memory for display, 5 is a color memory for display,
6 is a flip-flop, 7 and 8 are bidirectional bus buffers,
9 is a character generation circuit, 10 is a color CRT, 11 is a display readout address generation circuit, and 12 is a switching circuit. Here, the principle of character/graphic display operation of the display device will be briefly explained. Assume now that an 8-bit character code to be displayed in the display main memory 4 has already been recorded with 8-bit color information at an address corresponding to the main memory 4 in the color memory 5. These characters. The address where the color information is recorded is the CRT
Corresponds to the character display position on the screen. During the display information read period, the switching circuit 12 switches from the address bus 3 of the MPU1 to the display read address generation circuit 11 side, and outputs addresses to the display main memory 4 and color memory 5. When the read address is given, the character code of the given address is input from the main memory 4, and the color information from the color memory 5 is input to the character generation circuit 9, where they are synthesized and colored on the screen of the color CRTlO. Displayed as text. Here, a procedure for recording information desired to be displayed in the main memory 4 and color memory 5 will be described. First, at t1, the flip-flop 6 is set to enable the main memory 4 and the bidirectional buffer 7 (for example, the Q of the flip-flop 6 is
During a period other than the display period (when the output is turned on), that is, when the switching circuit 12 is connected to the address bus 3 side, the data to be written is sent to the address specified by the address bus 3 via the data bus 2 and the bidirectional buffer 7. The data is recorded in the main memory 4 at the time. Next, the MPU1 inverts the flip-flop 6 (turns on the Q output) to enable the color information memory 5 and the bidirectional buffer 8, and then the MPU1 stores the color information memory 5 corresponding to the accessed address in the main memory 4. The address is placed on the address bus 3, the color information to be recorded thereon is placed on the data bus 2, and recorded in the color information memory 5 via the switching circuit 12 or the buffer 8. Reading is also performed in much the same way. The flowchart in FIG. 2 shows the procedure for raising the screen display content (hereinafter referred to as "scroll up") using software in the circuit configuration shown in FIG. In the same figure, B
indicates the number of characters in one line. As is clear from Figure 2, to scroll up the screen using software, move the contents at the beginning of the second line to the beginning of the first line, and move the contents of the second character of the second line to the second character of the first line. , and so on, each character from the beginning to the end of the second line can be transferred to the next line above. In the circuit configuration shown in FIG. 1, three operations are required each time one character is transferred: switching between the main memory 4 and color memory 5, transferring the contents of the main memory, and transferring the contents of the color memory. . In this case, it takes about three times as long as when just transferring the normal character code. As a way to speed up this process a little more, it is possible to first transfer only the character codes of main memory 4 for the entire screen, and then switch to color memory 5 and transfer only the color information for the entire screen. Because it only needs to be done twice, it takes about twice as long as transferring only the character code, but the disadvantage is that the screen looks unnatural and difficult to read because the characters and colors are transferred at different times for each line. There is. Also, if there are a large number of displayed characters, or if the MPUl driving clock is not very fast, or if the transfer speed is more than twice that of transferring only character codes, the screen will appear to wave every time it is scrolled up. It was a problem. The following methods have been considered to overcome these drawbacks.

In other words, a data storage means is provided in the data input/output section of the color memory, and data is written from the MPU to the color memory.
Reading. The extraction is always done through the temporary storage means, and when an address in the main memory is read or written, the address in the color memory corresponding to that address is read or written at the same time, so that if t is now a certain address on the display screen. When a read operation is performed, the character code in the main memory is taken into the MPU, color information from the color memory is taken into the temporary storage means, and when the MPU performs a write operation to another address on the display screen, the MPU The character code held by is written to the specified address in the main memory, and the color information currently held in the temporary storage means, that is, the content read earlier, corresponds to the write address in the main memory of the color memory. By writing to the specified address, the color information is also transferred at the same time with the software processing as if only the character code was transferred.
This is a method for speeding up the transfer of display contents on the screen.

This configuration and operating principle will be explained in more detail below using the block diagram of FIG. In this figure, block numbers 1 to 5, 7, and 9 to 12 are the same as the blocks with the same numbers in FIG.

The structure shown in FIG. 3 is obtained by newly replacing the register 13 with the bidirectional buffer 8 shown in FIG. 1 and further removing the flip-flop 6. Register 13 uses bi-directional tri-state 8-bit parallel latches. Next, the operation will be explained. The method of reading out the character information and color information already recorded in the main memory 4 and color memory 5 and displaying them on the CRT screen is as described above. Here, the main memory 4 and color memory 5 are
We will explain the operation of reading and writing from. When MPUl performs a read operation of display memory 4 and color memory 5,
Based on the address information given via the address bus 3 and the switching circuit 12, the main memory 4 and the color memory 5
outputs data. The data output from the main memory 4 is transferred to the data bus 2 via the bidirectional buffer 7,
Loaded into PUl. On the other hand, data output from the memory 5 is recorded in the register 13. If the MPUl wants to know the information, it reads the contents of the register 13 and the information is transferred to the data bus 2 and read into the MPUl.
In the case of writing, the content to be written into the color memory 5 is set in the register 13 in advance. The setting method is to directly write to the register 13 from MPU1,
Two methods can be considered: reading out from the color memory 5 an address having the same color information as the color desired to be set on the display screen. In this way, after setting the register 13, MPU1
When the character code is written into the main memory 4 via the data bus 2 and the bidirectional buffer 7, the color memory 5 is written at the same time.
is given the same address information and write enable signal,
Since the data bus is connected to the register 13, the contents of the register 13 are written into the color memory 5. Although this method is effective for high-speed processing of star roll-up, it has the following problems.

That is, each time the color memory 5 reads an address in the main memory 4 that exists in parallel, the data in the color memory 5 is taken into the register 13, and the color data held until then is destroyed. For example, even if the MPU1 reads a program recorded in the main memory 4 in an area where the color memories 5 exist in parallel in order to interpret it, or reads data temporarily saved in the same area, the register The contents of will be destroyed. Therefore, the method of resetting the register 13 immediately before writing into the display area is useless in an area where the color memory 5 exists in parallel. If the color memory area is limited to a fixed display area, the above problems will not occur, but it is necessary to have a multi-page display screen called paging, and to save the display screen together with the color information. It becomes difficult.

It is an object of the present invention to eliminate the drawbacks of the prior art as described above, and to provide a character/figure system that allows the contents of the necessary registers to be retained without being destroyed even when the main memory area having the color memories in parallel is read out. The purpose of this invention is to provide a display device.

In order to achieve the above-mentioned object, the present invention adds at least one more bit to the above-mentioned register and sets one bit, for example, "1" from M[)U, to record color information, and the color memory and main memory are parallel Even if the address of the area is read, the color information is retained; conversely, if "0" is recorded in the 1 bit, the color information is retained as before.Each time the address of the main memory parallel area is read, the color information is retained. By setting the contents of the color memory to the register, the contents of the register change only when moving the display contents such as scrolling up, or when you want to read the contents of the color memory. The current data is retained until new data is written.

Next, the present invention will be explained in detail with reference to FIG.

FIG. 4 is a block diagram showing one embodiment of the present invention. In FIG. 4, 1 to 5 and 7, 11, and 12 indicate the same blocks as the same numbered blocks in FIG. Newly, as parts corresponding to the register 13 in FIG.
9, memory address bus 20, gate circuits 21, 22
, 23 are provided. Next, the operation will be explained.

The latch 14 captures data at its data input terminal at the rising edge of the signal applied to the CK terminal.
The number of bits in the latch 14 is one bit greater than the number of bits in the color memory 5. This one bit is hereinafter referred to as a mask bit. The mask bit is the MPUl mentioned above.
In this embodiment, the number of bits in the color memory 5 is 7 bits or less, and the color memory 5 is allocated to the same location as the latch 14. The signal on the high impedance control signal path 18 is normally at the H2 level, at which time the output of the 3-state buffer 15 is in the high impedance state, and becomes the L2 level only at the moment the MPU1 reads out the contents of the latch 14. The contents of the latch 14 are output onto the data bus 2. Similarly, the signal on the high-impedance control signal path 17 goes to the L'' level only at the moment when data is written from the MPU1 to the latch 14.The signal on the previous color memory read signal path 19 goes to the L'' level only at the moment when data is written from the MPU1 to the latch 14. The moment the existing area is read out, the level becomes ``L''. The gate 21 is a negative logic AND, that is, it provides an output at the L/' level only during the period when both of the two inputs are at the L'' level.The gate 22 is a negative logic OR, that is, at least one of the two inputs. The output is at the L'' level during the period when the output is at the L'' level.The gate 23 is a positive logic AND;
In other words, both inputs are "SH" only during the period when they are at H2 level.
Gives level output. In the circuit configured as described above, first, a case will be described in which color data with the master bit set to the "L" level is written into the latch 14 from the MPU 1 via the 3-state buffer 16.

Since the color memory read signal on the signal path 19, which is one of the inputs to the gate 23, is always at the ``H'' level while the high impedance control signal on the signal path 17 is at the ``L2 level,''
An L'' level signal is output from the gate 23 to the input terminal of the latch 14 of the mask bit.
The output of gate 21 is connected to the CK terminal of 4 as a color memory readout. Since the output signal is at the "H" level regardless of the other input level, the high impedance control signal is input as is through the gate 22, and becomes the "L" level during the write operation. The rising edge of the trailing edge of the signal is captured into latch 14. With this, the mask bit outputs the "L" level until new data is written. Next, we will discuss the case where an operation is performed to read out an area where the color memories 5 exist in parallel in this state. The input on the mask bit side is L.
〃level, the same signal as the color memory read signal is obtained at the output terminal of the gate 21. On the other hand, since the aforementioned high impedance control signal is always at the H7 level during this period, the color memory readout signal is input to the CK terminal of the aforementioned latch 14, and at the rising edge of the color memory readout signal, the color memory 5
Import the color data that was output from. At this time, the input to the mask bit is one input of the gate 23, which is the color memory readout. Since the overflow signal is at the ``L'' level, the output of the gate 23 also goes to the ``L'' level, and the ``L'' level is maintained. Next, the case where the H2 level is written to the mask bits will be explained.

The operation itself for writing a H7 level signal to the mask bit from the MPU1 is the same as the case of writing an L'' level signal, so the explanation will be omitted.Now, with the mask bit holding the H2 level, the color memory 5 When the MPU1 reads out the area in which are present in parallel, the color memory read signal goes to the L/7 level, but the output of the gate 21 remains at the H'' level, so the CK terminal of the latch 14 goes to the HI level. ! Since the level remains unchanged, the output data from the color memory 5 is not taken into the latch 14.

That is, when the mask bit is set to the ``H'' level and color data is written to the latch 14 from the MPU1, the color data does not change until new data is written from the MPU1. L
``When the level is set, the color data is reset every time the color memory 5 reads an area that exists in parallel. Therefore, when scrolling up or transferring the contents of the screen,
Only when it is desired to know the contents of the color memory, the mask bit may be set to the "L" level, and in other cases, the mask bit may be set to the "H" level. In this embodiment, the mask bit and the latch 14 are provided at the same address, but it will be easily understood that the same processing can be performed even if only the mask bit is provided at a single address.

As described above, according to the present invention, it has been possible to provide color memory in parallel only in the display-only area, but now color memory can be provided in parallel in areas used as normal program areas and work addresses. It has become possible to provide a memory, and as a result, it has become extremely easy to save display contents including color information to other addresses, to switch between multiple pages, to change the number of displayed characters, etc.

Also, there is almost no increase in cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a character/figure display device using a two-line memory read/write method according to the prior art;
The figure is a flowchart illustrating the procedure for scrolling up on the screen using the conventional two-series memory read/write method, and FIG. , and FIG. 4 are block diagrams showing one embodiment of the present invention. 14... Latch, 15, 16... 3-state buffer, 21, 22, 23... Gate circuit.

Claims (1)

[Claims] 1. It has a plurality of series of memories and display devices in which at least some of the addresses correspond to each other, and among the main information and accompanying information about characters and figures to be displayed on the display device, the main information is based on the plurality of series. In the character/figure display device, the accompanying information is written as data in the main sequence memory of one of the main sequence memories and in the other subsidiary sequence memories at corresponding addresses, and is read from there and displayed on the display device. A data temporary storage means provided in the data input/output section for sending and receiving data to and from the auxiliary series memory, and when a certain address of the main sequence memory is read, the data at the corresponding address of the auxiliary series memory is transferred to the auxiliary series memory. an acquisition control means for importing the data into the temporary storage means; and a write control means for writing the data stored in the temporary storage means to the corresponding address of the auxiliary sequence memory when data is written to a certain address of the main sequence memory. the acquisition control means, the data temporary holding means that outputs either the first or second data control signal, and the acquisition control means is enabled or disabled in accordance with the data control signal output from the data temporary holding means. 1. A character and graphic display device comprising: selection means for selecting one of the following.