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JPS5925229B2 - Driving method of liquid crystal display element - Google Patents
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JPS5925229B2 - Driving method of liquid crystal display element - Google Patents

Driving method of liquid crystal display element

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Publication number
JPS5925229B2
JPS5925229B2 JP14639675A JP14639675A JPS5925229B2 JP S5925229 B2 JPS5925229 B2 JP S5925229B2 JP 14639675 A JP14639675 A JP 14639675A JP 14639675 A JP14639675 A JP 14639675A JP S5925229 B2 JPS5925229 B2 JP S5925229B2
Authority
JP
Japan
Prior art keywords
liquid crystal
signal
time
scanning
display element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14639675A
Other languages
Japanese (ja)
Other versions
JPS5270794A (en
Inventor
英昭 川上
雅明 北島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14639675A priority Critical patent/JPS5925229B2/en
Publication of JPS5270794A publication Critical patent/JPS5270794A/en
Publication of JPS5925229B2 publication Critical patent/JPS5925229B2/en
Expired legal-status Critical Current

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  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Description

【発明の詳細な説明】 本発明は、マトリクス伏の電極構造をもつ液晶表示素子
、もしくはセグメントがマトリクス伏に接続された表示
素子の、駆動方法に係り、特に輝度の立上り応答時間を
早める、駆動方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving method for a liquid crystal display element having a matrix-facing electrode structure or a display element in which segments are connected in a matrix-facing manner, and particularly relates to a driving method that speeds up the brightness rise response time. Regarding the method.

マトリクス伏の電極構造をもつ液晶表示素子では、一般
に線順次走査による、駆動方法が用いられる。これは、
マトリクスの一方を構成する走査電極を一本ずつ順次選
択し、これと同期して他方の信号電極のうち必要なもの
を時分割に選択して電圧を印加し、マトリクスの交点に
位置する絵素のうち点灯するものを時分割に選択状態と
し、この間の平均電圧で表示を得るものである。また、
数字表示用の液晶表示装置等でも、セグメントがマトリ
クス状に接続された素子が用いられるが、この場合にも
上記と全く同様な駆動方法がとられる。
In a liquid crystal display element having a matrix facing electrode structure, a driving method using line sequential scanning is generally used. this is,
The scanning electrodes constituting one side of the matrix are sequentially selected one by one, and in synchronization with this, the necessary signal electrodes on the other side are selected in a time-division manner and voltage is applied to the picture elements located at the intersections of the matrix. Among them, those that are turned on are selected in a time-division manner, and the average voltage during this period is used to obtain a display. Also,
Elements in which segments are connected in a matrix are also used in liquid crystal display devices for displaying numbers, and in this case, the same driving method as described above is used.

ここでは一例として、1文字が7セグメントで構成され
、それぞれの桁ごとにデシマルポイントを有する4桁の
数字表示用の液晶表示素子に1/3バイアス電圧平均化
法と呼ばれる、駆動方法を適用したものを説明する。第
1図は、数字表示素子の構成図である。
Here, as an example, a driving method called the 1/3 bias voltage averaging method was applied to a liquid crystal display element for displaying 4-digit numbers in which one character is composed of 7 segments and each digit has a decimal point. explain something FIG. 1 is a block diagram of a numeric display element.

ディジット電極A9B9C9Dと、接続線a、b9c、
d、e、f、g)及びD、P、で接続されたセグメント
電極とが液晶層をはさんで対向し、マトリクスが構成さ
れる。この例のような4桁の数字表示装置では、通常、
ディジット電極A−Dを走査電極、引出線a−fおよび
D、Pを信号電極として線順次走査が行なわれる。第2
図は、1/3バイアス電圧平均化法を説明する状態図で
、VX、VYはそれぞれ走査電極、および信号電極への
印加電圧、VX−VYはマトリクスの交点の絵素に印加
される電圧を示す。
Digit electrode A9B9C9D and connection wires a, b9c,
d, e, f, g) and segment electrodes connected by D and P face each other with a liquid crystal layer in between, forming a matrix. For a 4-digit numeric display like this example, typically
Line sequential scanning is performed using digit electrodes A-D as scan electrodes and leader lines a-f, D, and P as signal electrodes. Second
The figure is a state diagram explaining the 1/3 bias voltage averaging method, where VX and VY are the voltages applied to the scanning electrode and signal electrode, respectively, and VX-VY is the voltage applied to the picture element at the intersection of the matrix. show.

この図に示されるとおり、選択状態、すなわち信号電極
と走査電極の両方向から選択された状態の絵素には士V
oの電圧が印加され、他の状態では±1/3Voの印加
電圧となる。第3図は、実際に絵素に印加される電圧の
波形図で、aは非点灯状態から点灯状態へ移る絵素、を
は非点灯状態のままの絵素を示す。
As shown in this figure, the picture element in the selected state, that is, the state where it is selected from both the signal electrode and the scanning electrode, has a
o voltage is applied, and in other states, the applied voltage is ±1/3Vo. FIG. 3 is a waveform diagram of a voltage actually applied to a picture element, where a indicates a picture element that changes from a non-lighting state to a lighting state, and "a" indicates a picture element that remains in a non-lighting state.

このように点灯状態では、時分割に選択状態とされて(
ここでは4走査線による時分割)この間の平均電圧で液
晶を励起させて表示を得る。ここで以上のような従来の
駆動方法で問題となるのは、表示内容の変化に対して液
晶の輝度特性の応答に遅れを生じ、メリハリのある表示
ができない点である。
In this way, in the lit state, the selected state is time-divided (
In this case, the liquid crystal is excited by the average voltage during this period (time division using four scanning lines) to obtain a display. The problem with the conventional driving method described above is that there is a delay in the response of the brightness characteristics of the liquid crystal to changes in display content, making it impossible to provide a sharp display.

特に低温時での輝度立上り応答時間の遅れは問題となる
。これまで、スタテイツク5駆動方法をとるものでは、
絵素を点灯させる際に、輝度が飽和するまで通常より高
い直流電圧を印加して応答時間を単縮する方法等が提案
されてきた。しかしながら、このような電圧を変化させ
る方法を先に述べた電圧平均化法による時分割駆動方法
に適用すると、クロストーク電圧を平均化することがで
きなくなり、表示にムラが生ずる。本発明の目的は、従
来の時分割駆動方式の長所を損なうことなく、液晶の輝
度の立上りに応答時間を短縮した新たな駆動方法を提供
するにある。
In particular, the delay in brightness rise response time at low temperatures becomes a problem. Until now, the static 5 drive method was
A method has been proposed to shorten the response time by applying a DC voltage higher than usual until the brightness is saturated when lighting a picture element. However, if such a method of changing the voltage is applied to the time-division driving method using the voltage averaging method described above, it becomes impossible to average the crosstalk voltage, resulting in uneven display. An object of the present invention is to provide a new driving method that shortens the response time to the rise in brightness of a liquid crystal without sacrificing the advantages of the conventional time-division driving method.

本発明の特徴は、第1段階では表示内容の変更を知らせ
る信号の入力により全絵素を液晶応答遅れ時間のあいだ
選択状態とし、第2段階では走査電極を順次走査しなが
ら信号電極を時分割に駆動することにより点灯すべき絵
素を時分割に選択状態とするという2段階の1駆動方法
にある。すなわち、本発明では、これまで非点灯であり
次に点灯させる絵素の輝度立上りは、全絵素への連続選
択電圧印加により早められ、絵素の点灯状態の維持は線
順次の時分割駆動にて行う。以下、本発明の実施例を説
明する。
A feature of the present invention is that in the first stage, all picture elements are set to a selected state during the liquid crystal response delay time by inputting a signal notifying the change of display content, and in the second stage, the signal electrodes are time-divided while scanning the scanning electrodes sequentially. This is a two-step driving method in which picture elements to be turned on are brought into a selected state in a time-division manner by driving. That is, in the present invention, the rise in brightness of picture elements that have not been lit and will be lit next is accelerated by continuous selection voltage application to all picture elements, and the lighting state of picture elements is maintained by line-sequential time-division driving. It will be held at Examples of the present invention will be described below.

第4図は、マトリクス型の表示素子の等価回路図である
FIG. 4 is an equivalent circuit diagram of a matrix type display element.

ここでは4X4のマトリクスが示されており、3−1,
3−2,3−3,3−4は走査電極、4−1,4−2,
4−3,4−4は信号電極を示す。これらの電極の交点
にはそれぞれ液晶セル5が接続され、これがそれぞれ液
晶表示素子の絵素となる。第1図に示したような、セグ
メントがマトリクス状に接続された液晶表示素子でも等
価回路は第4図と同様になる。第1図の場合は4×8の
マトリクスとなるが、今後の説明は4X4のマトリクス
で行う。第5図に、第4図に示したマトリクス表示素子
を,駆動する時のシステムのプロツク図を示す。
A 4X4 matrix is shown here, with 3-1,
3-2, 3-3, 3-4 are scanning electrodes, 4-1, 4-2,
4-3 and 4-4 indicate signal electrodes. A liquid crystal cell 5 is connected to each intersection of these electrodes, and each becomes a picture element of a liquid crystal display element. Even in a liquid crystal display element in which segments are connected in a matrix as shown in FIG. 1, the equivalent circuit is similar to that shown in FIG. 4. In the case of FIG. 1, it is a 4×8 matrix, but the following explanation will be based on a 4×4 matrix. FIG. 5 shows a block diagram of a system for driving the matrix display element shown in FIG. 4.

第5図の9は、走査電極3−1〜3−4を順々に走査す
る信号を発生する走査信号発生回路である。また8は第
4図に示した絵素Cll〜C44のいずれを表示させる
かを選択するための表示信号発生回路であり、走査電極
の順次走査に同期して、各信号電極ごとに選択信号を発
する。また、8からはその内容の変更を知らせる信号S
Pが出力される。10は、この表示内容の変更を知らせ
る信号SPが入力された時にのみ一定時間出力されるホ
ールド信号TPを発するホールド信号発生回路である。
Reference numeral 9 in FIG. 5 is a scanning signal generating circuit that generates a signal to sequentially scan the scanning electrodes 3-1 to 3-4. Further, 8 is a display signal generation circuit for selecting which of the picture elements Cll to C44 shown in FIG. emanate. In addition, from 8 onwards, a signal S indicating a change in the content is sent.
P is output. Reference numeral 10 denotes a hold signal generating circuit that generates a hold signal TP that is output for a certain period of time only when a signal SP notifying a change in display content is input.

また11はこのホールド信号TPが入力されない時には
表示信号発生回路8からの選択信号をそのまま出力し、
ホールド信号TPが入力されると総ての選択信号を11
″レベルにホールドして出力する選択信号ホールド回路
、12は同様にしてホールド信号TPの入力により走査
信号をホールドする走査信号ホールド回路である。6−
1〜6一8は、11および12を通して得られる選択信
号AP5〜AP8、および走査信号APl〜AP4に基
づき、各走査電極を駆動する電圧を発生する駆動回路で
ある。
Further, when this hold signal TP is not input, 11 outputs the selection signal from the display signal generation circuit 8 as it is,
When the hold signal TP is input, all selection signals are set to 11.
12 is a scanning signal hold circuit that similarly holds the scanning signal by inputting the hold signal TP. 6-
1 to 6-8 are drive circuits that generate voltages for driving each scan electrode based on selection signals AP5 to AP8 obtained through 11 and 12 and scan signals AP1 to AP4.

第6図は、第5図の動作を示す各部波形図で、時刻Ta
で第4図の絵素C,lのみを点灯させようとする時を例
として示している。
FIG. 6 is a waveform diagram of each part showing the operation of FIG.
4 shows an example in which only picture elements C and l in FIG. 4 are to be lit.

走査信号APl〜AP4は、通常は一定周期で順次レベ
ル11゛とされるが、時刻Taからは一定時間Tbだけ
発せられる信号TPが出力される間レベル01゛にホー
ルドされる。選択信号AP5〜AP8も同時にレベル8
1゛にホールドされ、これによりこの期間は全絵素が連
続して選択状態とされる。時刻t 以後は、選択信号A
P5のみが走査信号APelと同期してレベル61″と
され、これにより絵素Cllのみが時分割で選択状態と
されて点灯状態になる。
The scanning signals AP1 to AP4 are normally set to level 11' sequentially at a fixed period, but are held at level 01' while the signal TP is output for a fixed time Tb from time Ta. Selection signals AP5 to AP8 are also level 8 at the same time.
It is held at 1, so that all the picture elements are continuously selected during this period. After time t, selection signal A
Only the pixel P5 is set to level 61'' in synchronization with the scanning signal APel, so that only the picture element Cll is time-divisionally selected and turned on.

第7図は、第5図符号10のホールド信号発生回転の回
路図で、りセツト・セツトフリップフロツプ13、J−
Kフリツプフロツプ14、ANDゲート15、カウンタ
ー16、および反転ゲート17より成る。
FIG. 7 is a circuit diagram of the hold signal generation rotation indicated by reference numeral 10 in FIG.
It consists of a K flip-flop 14, an AND gate 15, a counter 16, and an inverting gate 17.

また、第8図は、第7図の回路の動作を示す各部波形図
である。ここで信号PAは、第5図、符号9の走査信号
発生回路より、各走査電極の走査信号が発せられるごと
に送られるパルス信号で、ホールド信号TPは、表示内
容の変更を示す信号SPが入力した後の信号APの立上
りに同期して立上る。信号TPの継続時間Tbは、カウ
ンター16の計数値で設定する。第9図は、第5図、符
号6−1〜6−8の駆動回路の回路図で、トランジスタ
18,19,20,N0Rゲート21,22,23、反
転ゲート24および各抵抗より成る。
Further, FIG. 8 is a waveform diagram of each part showing the operation of the circuit of FIG. 7. Here, the signal PA is a pulse signal sent from the scanning signal generation circuit 9 in FIG. 5 every time a scanning signal is generated for each scanning electrode, and the hold signal TP is a pulse signal sent from the scanning signal generation circuit 9 in FIG. It rises in synchronization with the rise of signal AP after input. The duration Tb of the signal TP is set by the count value of the counter 16. FIG. 9 is a circuit diagram of the drive circuits 6-1 to 6-8 in FIG. 5, which are composed of transistors 18, 19, 20, N0R gates 21, 22, 23, an inverting gate 24, and each resistor.

この駆動回路は、1/3バイアス電圧平均化法を適用す
るためのもので、走査信号APl〜AP4もしくは選択
信号AP5〜AP8の入力に応じて信号CPもしくはC
Pの入カクロツクに基きVO,2/3V0,1/3V0
およびOボルトの組合せによる各電極の駆動信号VOU
Tを発する。第10図は、以上説明した実施例により各
絵素に加わる印加電圧を示したもので、aは既に点灯伏
態にあつた絵素、bは非点灯伏態のままの絵素、cは非
点灯状態から点灯状態へ移る絵素への印加゛電圧を示す
This drive circuit is for applying the 1/3 bias voltage averaging method, and the signal CP or C is applied according to the input of the scanning signals APl to AP4 or the selection signals AP5 to AP8.
Based on the input clock of P, VO, 2/3V0, 1/3V0
The drive signal VOU for each electrode is a combination of
Emits a T. FIG. 10 shows the applied voltages applied to each picture element according to the embodiment described above, where a is a picture element that is already in the lighting state, b is a picture element that is still in the non-lighting state, and c is a picture element that is in the non-lighting state. It shows the voltage applied to a picture element that changes from a non-lit state to a lit state.

また、第11図は、従来の時分割1駆動方式をとるとき
の非点灯状態から点灯状態へ移る絵素への印加電圧波形
と絵素の輝度の応答波形を示したもので、第12図は、
本実施例の印加電圧波形と絵素の輝度の応答波形を示し
たものである。このように、本実施例によれば、時間T
bの間、±VOの電圧が連続して印加され、これがプリ
バイアスとなつて液晶の輝度立上り時間T,が短縮する
。しかしながら、第10図で示されるとおり、このプリ
バイアスの期間中、点灯させない絵素にも士VOの電圧
が印加される。したがつて、第7図のカウンター16で
設定するホールド信号TPの継続時間Tbを、第12図
にT,で示した液晶の応答遅れ時間以下にすることによ
り、必要のない絵素が瞬時に点灯することのないように
することが望ましい。以上、1/3バイアス電圧平均化
法を用いたときの本発明の実施例を説明したが、他の駆
動法にも本発明を適用することができ、本発明の採用に
より、必要のない絵素が瞬時に点灯することがなく、液
晶の輝度の立上り応答時間の短縮が可能となる。
Furthermore, Fig. 11 shows the voltage waveform applied to the picture element and the response waveform of the luminance of the picture element as it changes from the non-lighting state to the lighting state when using the conventional time-division single driving method. teeth,
3 shows the applied voltage waveform and the response waveform of the luminance of the picture element in this example. In this way, according to this embodiment, the time T
During period b, a voltage of ±VO is continuously applied, which serves as a pre-bias and shortens the brightness rise time T of the liquid crystal. However, as shown in FIG. 10, during this pre-bias period, the voltage of VO is applied even to picture elements that are not turned on. Therefore, by making the duration Tb of the hold signal TP set by the counter 16 in FIG. 7 equal to or less than the response delay time of the liquid crystal indicated by T in FIG. 12, unnecessary picture elements can be instantly removed. It is desirable to prevent it from lighting up. Although the embodiment of the present invention using the 1/3 bias voltage averaging method has been described above, the present invention can also be applied to other driving methods. Since the element does not turn on instantly, the response time for rising the brightness of the liquid crystal can be shortened.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、数字表示素子の構成図、第2図はバイアス電
圧平均化法の電圧状態図、第3図は従来の時分割駆動方
式を説明する液晶セグメントへの印加電圧波形図、第4
図は本発明の実施例に用いるマトリクス表示素子の等価
回路図、第5図は本発明の一実施例のシステムのプロツ
ク図、第6図は第5図の各部波形図、第7図は、第5図
のプロツク10の回路図、第8図は第7図の信号波形図
、第9図は、第5図のプロツク6−1〜6−8の回路図
、第10図は本発明の実施例による各液晶セグメントへ
の印加電圧波形図、第11図は従来の駆動方法で駆動し
た時の液晶の応答波形図、第12図は本発明の実施例に
よる液晶の応答波形である。 符号の説明、3−1〜3−4・・・・・・走査電極、4
−1〜4−4・・・・・・信号電極、5・・・・・・絵
素、6−1〜6−8・・・・・・駆動回路、8・・・・
・・表示信号発生回路、9・・・・・・走査信号発生回
路、10・・・・・・ホールド信号発生回路、11・・
・・・・表示信号ホールド回路、12・・・・・・走査
信号ホールド回路。
Fig. 1 is a configuration diagram of a numeric display element, Fig. 2 is a voltage state diagram of the bias voltage averaging method, Fig. 3 is a voltage waveform diagram applied to the liquid crystal segment to explain the conventional time division driving method, and Fig. 4 is a diagram of the voltage applied to the liquid crystal segment.
The figure is an equivalent circuit diagram of a matrix display element used in an embodiment of the present invention, FIG. 5 is a block diagram of a system according to an embodiment of the present invention, FIG. 6 is a waveform diagram of each part of FIG. 5, and FIG. 5 is a circuit diagram of block 10, FIG. 8 is a signal waveform diagram of FIG. 7, FIG. 9 is a circuit diagram of blocks 6-1 to 6-8 of FIG. 5, and FIG. FIG. 11 is a diagram of the voltage waveforms applied to each liquid crystal segment according to the embodiment. FIG. 11 is a diagram of response waveforms of the liquid crystal when driven by a conventional driving method. FIG. 12 is a diagram of response waveforms of the liquid crystal according to the embodiment of the present invention. Explanation of symbols, 3-1 to 3-4...Scanning electrode, 4
-1 to 4-4... Signal electrode, 5... Picture element, 6-1 to 6-8... Drive circuit, 8...
...Display signal generation circuit, 9...Scanning signal generation circuit, 10...Hold signal generation circuit, 11...
...Display signal hold circuit, 12...Scanning signal hold circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 走査電極と信号電極との交点に複数の絵素が形成さ
れる液晶表示素子を駆動するものにおいて、第1段階で
表示内容の変更を知らせる信号により全絵素を液晶の応
答遅れ時間以下のあいだ選択状態とし、第2段階で該走
査電極の線順次走査に同期して必要な信号電極を時分割
に駆動することにより、点灯すべき絵素を時分割に選択
状態とすることを特徴とする液晶表示素子の駆動方法。
1. In a device that drives a liquid crystal display element in which a plurality of picture elements are formed at the intersections of scanning electrodes and signal electrodes, in the first step, all picture elements are controlled by a signal that notifies a change in display content to a time that is less than or equal to the response delay time of the liquid crystal. In the second step, necessary signal electrodes are driven in a time-division manner in synchronization with the line-sequential scanning of the scanning electrodes, thereby bringing the picture elements to be lit in a time-divisionally selected state. A method for driving a liquid crystal display element.
JP14639675A 1975-12-10 1975-12-10 Driving method of liquid crystal display element Expired JPS5925229B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14639675A JPS5925229B2 (en) 1975-12-10 1975-12-10 Driving method of liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14639675A JPS5925229B2 (en) 1975-12-10 1975-12-10 Driving method of liquid crystal display element

Publications (2)

Publication Number Publication Date
JPS5270794A JPS5270794A (en) 1977-06-13
JPS5925229B2 true JPS5925229B2 (en) 1984-06-15

Family

ID=15406745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14639675A Expired JPS5925229B2 (en) 1975-12-10 1975-12-10 Driving method of liquid crystal display element

Country Status (1)

Country Link
JP (1) JPS5925229B2 (en)

Also Published As

Publication number Publication date
JPS5270794A (en) 1977-06-13

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