JPS5925319B2 - semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device provided with a test terminal for screening.

With the progress of high-density integration technology of semiconductors, the application of semiconductors to memory devices is progressing, and there is a trend toward increasingly larger capacities.

FIG. 1 is a block diagram showing the configuration of a conventional semiconductor memory device. In the figure, 1 is a memory cell section, and a row line 2 is a selection line in the row direction, and a column line 3 is a selection line in the column direction. Although not shown, memory semiconductor elements are provided at all intersections between each row line 2 and each column line 3. 4 is a row selection circuit, 5 is a column selection circuit, 6 is a signal supply terminal to the row line, and 1 is a signal supply terminal to the column line.

Although not shown in the figure, the row selection circuit 4 and the column selection circuit 5 are usually provided with an input terminal for address information specifying a selected address. Now, the operation of this device will be explained.

The row selection circuit 4 selects one of the row lines 2, and the row drive signal from the signal supply terminal 6 is supplied to the selected row line 2. On the other hand, the column selection circuit 5 selects one of the column lines 3, and the column drive signal from the signal supply terminal 7 is supplied to the selected column line 3. In this way, the memory semiconductor element located at the intersection of the selected row line and column line is accessed, and a predetermined write or read operation is performed. by the way,
2. Description of the Related Art Failures called so-called bit defects often occur in semiconductor memory devices.

In particular, in a memory cell containing a manufacturing defect, the characteristics deteriorate as the defective portion is accessed several times, resulting in bit defects. Therefore, in order to ship a highly reliable product, it is necessary to access the semiconductor elements of all bits constituting the memory cell a certain number of times and to perform screening by deteriorating those that should deteriorate. Since conventional semiconductor memory devices only have the configuration shown in Figure 1, there is no other way to perform this screening than to sequentially access each bit one by one using the usual method. A very long operation was required to access the required number of times. The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor memory device that can perform access operations on all bits of a memory cell at the same time, and can significantly shorten the time required for screening. It is something. FIG. 2 is a block diagram showing an embodiment of the present invention.
This is an example when an integrated circuit is used.

In the figure, 8 is provided on each row line 2 and each column line 3,
A MOS transistor for switching between a normal access operation and a simultaneous access operation for screening, 9 is the switching signal supply terminal, and 10 and 11 are signal supply terminals to the row line and column line during the simultaneous access operation for screening, respectively. It is. In this embodiment, when all the MOS transistors 8 are cut off by the switching signal supplied to the switching signal supply terminal 9, the result is exactly the same as the conventional device shown in FIG. Then, row and column drive signals are applied to the selected row line 2 and column line 3 to perform normal access operations.

However, when screening the memory cells, all the MOS transistors 8 are made conductive by the switching signal supplied to the switching signal supply terminal 9, and all the rows are By applying drive signals to line 2 and all column lines 3 simultaneously, all bits are accessed at once. Therefore, if the bit capacity of a memory cell is N, in the conventional device, N access operations were required to complete one access operation for all bits, but in the embodiment of the present invention, Effects equivalent to those described above can be obtained with a single access operation, and the time required for screening can be reduced to 1/N of that of the conventional method.

In the above embodiment, a case is shown in which a MOS integrated circuit is used, but it can also be realized using a bipolar integrated circuit.

As detailed above, in the present invention, all row lines and all column lines of the memory cell section used in a semiconductor memory device can be simultaneously row driven and column driven. Screening operations for degrading and eliminating manufacturing defects can be carried out in a very short time, contributing to overall reductions in manufacturing costs and improved product reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional semiconductor memory device, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a memory cell section, 2 is a row line, 3 is a column line,
4 is a row selection circuit, 5 is a column selection circuit, 8 is a switching element (MOS transistor), 9 is a switching element switching signal supply terminal, and 10 and 11 are signal supply terminals to the row line and column line, respectively, during simultaneous access operation. It is.

Claims (1)

[Claims] 1 A plurality of row lines, one of which is selectively driven by a row selection circuit, a plurality of column lines, one of which is selectively driven by a column selection circuit, and a connection between each row line and each column line. In a device having memory semiconductor elements arranged at intersections, switch elements on the row line side are directly connected to each of the row lines, and a row drive signal is supplied to each of the row lines through the switch elements on the row line side. row signal supply terminal for
A column line side switch element directly connected to each column line, a column signal supply terminal for supplying a column drive signal to each column line through these column line side switch elements, and a column line side switch element connected directly to each column line. A semiconductor memory device comprising means for simultaneously opening and closing switch elements on a column line side.