JPS5925383B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5925383B2 JPS5925383B2 JP54039049A JP3904979A JPS5925383B2 JP S5925383 B2 JPS5925383 B2 JP S5925383B2 JP 54039049 A JP54039049 A JP 54039049A JP 3904979 A JP3904979 A JP 3904979A JP S5925383 B2 JPS5925383 B2 JP S5925383B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- recess
- semiconductor chip
- wiring board
- fiber material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は配線基板に組み立てられた薄型構造の半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with a thin structure assembled on a wiring board.
電子式腕時計、電子式卓上計算機等で薄型化、小型化が
商品の付加価値を高めるための重要な開発要素となつて
おり、従つてこの種の電子機器に組込まれる半導体装置
等の部品に対しても同様に薄型化、小型化が強く望まれ
ている。Making electronic wristwatches, electronic desktop calculators, etc. thinner and more compact has become an important development element for increasing the added value of products, and therefore, the semiconductor devices and other parts that are incorporated into these types of electronic devices are becoming more and more important. Similarly, there is a strong desire for thinner and smaller devices.
また商品のコストダウンも開発時の重要な要因であり、
これ等の関点から電子式腕時計などでは回路基板がセラ
ミック基板からガラスエポキシ基板へ、封止方法がハー
メチックシールから樹脂ポツテイングによる封止へと変
化してきている。ガラスエポキシ等のプラスチック基板
を用いた半導体装置には、第1図aに示すように配線基
板1上に半導体チップ2を固定し、ワイヤボンディング
等の電気的接続の処置が施こされた後樹脂3をポツテイ
ングした構造のものと、第1図bに示すように薄型化し
たいとの要望から、配線基板1に予め半導体チップ収納
用の凹部4を設け、該凹部4に半導体チップ2を固定し
、ワイヤボンディングを行つた後に樹脂3をポツテイン
グした構造のものがある。Reducing product costs is also an important factor during development.
Due to these considerations, the circuit boards of electronic wristwatches and the like have changed from ceramic substrates to glass epoxy substrates, and the sealing method has changed from hermetic sealing to resin potting. In a semiconductor device using a plastic substrate such as glass epoxy, a semiconductor chip 2 is fixed on a wiring board 1 as shown in FIG. 3 in a potted structure and a desire to make it thinner as shown in FIG. There is a structure in which the resin 3 is potted after wire bonding.
しかし、上記いずれの構造の半導体装置においても次の
ような欠点があつた。即ち、樹脂ポツテイングを行う場
合、液状樹脂をポツテイングするか或いは半硬化ペレッ
ト樹脂をチップ上に乗せて加熱溶融し、硬化させている
が、いずれも液状を経て硬化されるため、固まつた状態
の形状は図に示す如く樹脂の表面張力により半球状に脹
らんで製品の厚みが増す。また液状になつた樹脂は流動
性があるため、基板の水平度、樹脂の粘度、基板の微妙
な表面状態の影響を受け易く、(のため固化された形状
は不安定で、かつ必要以上に占有面積を取ることにより
、薄型化、小型化の目的を達成し得ない。本発明は上記
従来装置の欠点に鑑みてなされたJ もので、繊維材を
重ね合せてなるほぼ平板状樹脂シートを配置することに
より、樹脂の表面張力によつて凸状に脹らむ現象を抑制
し、かつ樹脂の流動性による不安定な流出を繊維成分に
゛よつて規制することにより、薄型、小型でかつ定形に
近い構門 造の半導体装置を提供するものである。However, semiconductor devices having any of the above structures have the following drawbacks. In other words, when resin potting is performed, liquid resin is potted or semi-hardened pellet resin is placed on a chip and heated to melt and harden. As shown in the figure, the product swells into a hemispherical shape due to the surface tension of the resin, increasing the thickness of the product. In addition, since the liquid resin has fluidity, it is easily affected by the horizontality of the substrate, the viscosity of the resin, and the subtle surface condition of the substrate. The purpose of thinning and downsizing cannot be achieved due to the occupying area.The present invention was made in view of the above-mentioned drawbacks of the conventional device. This arrangement suppresses the phenomenon of convex swelling due to the surface tension of the resin, and controls unstable outflow due to the fluidity of the resin using the fiber components, making it thin, small, and shaped. This provides a semiconductor device with a similar structure.
以下本発明を実施例を挙げて詳細に説明する。第2図に
於て、半導体チップ2は該半導体チップ2を収納し得る
凹部4が刻設された配線基板1に固定され、配線基板面
の凹部4周辺に設けられた導体5とチツプ上の覗極との
間がワイヤ6で亀気的接続されている。The present invention will be described in detail below with reference to Examples. In FIG. 2, a semiconductor chip 2 is fixed to a wiring board 1 in which a recess 4 is carved into which the semiconductor chip 2 can be housed, and a conductor 5 provided around the recess 4 on the wiring board surface and a conductor 5 on the chip are connected to each other. A wire 6 is used to connect the viewing pole to the viewing pole.
配線基板1に組立てられた半導体チツプ2は、凹部開口
が樹脂シート7で封止されて外部から遮断されている。
ここで上記樹脂シート7は樹脂成分単独から構成される
ものではなく繊維材が含有されている。繊維材として例
えばポリエステル、ポリエチレン等のブラスチツク繊維
、またはガラス金属等の無機質繊維からなる織布或いは
不織布が用いられる。樹脂シート7は、繊維材と樹脂材
が積層混合される力法によつて次のような2通りの製造
工程を経ることができる。The recessed opening of the semiconductor chip 2 assembled on the wiring board 1 is sealed with a resin sheet 7 and isolated from the outside.
Here, the resin sheet 7 is not composed of a resin component alone, but contains a fiber material. As the fiber material, for example, a woven fabric or a non-woven fabric made of plastic fibers such as polyester or polyethylene, or inorganic fibers such as glass metal is used. The resin sheet 7 can be manufactured through the following two manufacturing processes using the force method in which the fiber material and the resin material are laminated and mixed.
即ち、凹部開口4の封止工程に供給するより前の段階で
予め樹脂と繊維をなじませてシート状に積層し、上記素
材より成る織布或いは木織布に樹脂を含浸させて樹脂を
半硬化状能にしたものを、凹部開口を考慮した所望寸法
に裁断して半導体チツブの封止工程に供給される。ここ
で繊維材の厚さは0.05〜0.20wrm程度に形成
され、含浸された樹脂厚も含めてシート7の厚さは0.
1〜1.5m程度に形成される。比較的厚みが薄い0.
1〜0.3Tvn程度のシート7は通常のブリブレグ製
造方法によつて作製することができ、第2図に示す如く
半導体チツプ収納空間を特に樹脂充填して封止する必要
がない場合に適用される。また板厚が厚い0.47m以
上のシート7は、半硬化状態の樹脂粉末を繊維材上に乗
せ、ロール等の間隙を通過させて一定厚みとし、加熱溶
融させて繊維材中に一部含浸させて作製し、凹部空間を
比較的多重の樹脂成分で封止する必要がある装置に用い
られる。上記製造力法によつて作裂された樹脂シート1
は半導体チツプ2が既に固定された凹部に蓋をする状態
で乗せられ、加熱炉中等で半硬化状態の樹脂を加熱溶融
させ、硬化させて封止する。上記実施例は予め樹脂と繊
維材を積層混合したものを凹部開口に設置する場合につ
いて述べたが、液状樹脂を用いて、半導体チツプと配線
基板を組立てる工程中に繊維材と樹脂を混合させること
ができる。即ち、第3図に示す如く配線基板1の凹部4
にダイボンド及びワイヤボンドされたチツブ2表面に封
止用の液状樹脂7aを滴下し、その上に所望サイズにカ
ツトされた繊維材Rbを乗せて樹脂を硬化させる。樹脂
は繊維材中及び面上に広がつて繊維材と樹脂の親和力に
より繊維材を基板に引き寄せて固定され、前記実施例と
同様に樹脂が含浸されたシートによつてチツプは封止さ
れる。硬化された状態で樹脂は周辺に異常に拡がること
もなく、また上表面はほぼ平坦に仕上げられる。尚、上
記両実施例において、配線基板にダイボンドされた半導
体チツブは表面をエポキシ、シリコーンまたはポリイミ
ド等の樹脂を予めアンダーコートして耐湿性の改善が計
られたチツプを用いることもできる。以上本発明によれ
ば、板状の繊維材を混合してなる封止用樹脂シートを用
いて半導体チツプを封止することにより、従来装置の如
く樹脂が半球状に脹らむことを防止することができ、更
に半導体チツプを配線基板に形成した凹部底面にダイボ
ンドしているため、配線基板の厚さを利用することがで
き、より一層薄型の装置を得ることができる。That is, before supplying the recess opening 4 to the sealing process, the resin and fibers are blended in advance and laminated in a sheet form, and a woven fabric or wood fabric made of the above material is impregnated with the resin to half the resin. The cured product is cut into desired dimensions taking into account the opening of the recess and supplied to the semiconductor chip sealing process. Here, the thickness of the fiber material is approximately 0.05 to 0.20 wrm, and the thickness of the sheet 7 including the thickness of the impregnated resin is 0.05 to 0.20 wrm.
It is formed to about 1 to 1.5 m. Relatively thin 0.
The sheet 7 having a thickness of about 1 to 0.3 Tvn can be produced by a normal blibreg manufacturing method, and is applied when there is no need to specifically fill and seal the semiconductor chip storage space with resin, as shown in FIG. Ru. In addition, for sheet 7 with a thickness of 0.47 m or more, semi-hardened resin powder is placed on the fiber material, passed through gaps such as rolls to a constant thickness, heated and melted, and partially impregnated into the fiber material. It is used in devices in which the recessed space needs to be sealed with relatively multiple resin components. Resin sheet 1 torn by the above manufacturing method
The recess to which the semiconductor chip 2 has already been fixed is placed with a lid on it, and the semi-hardened resin is heated and melted in a heating furnace or the like, and then hardened and sealed. The above embodiment describes the case where a layered mixture of resin and fiber material is installed in the recess opening, but it is also possible to mix the fiber material and resin during the process of assembling the semiconductor chip and the wiring board using liquid resin. I can do it. That is, as shown in FIG.
A sealing liquid resin 7a is dropped onto the die-bonded and wire-bonded surface of the chip 2, and a fibrous material Rb cut to a desired size is placed thereon to harden the resin. The resin spreads in the fiber material and on the surface, and the affinity between the fiber material and the resin draws the fiber material to the substrate and fixes it, and the chip is sealed with a resin-impregnated sheet as in the previous embodiment. . In the cured state, the resin does not spread abnormally to the periphery, and the upper surface is finished almost flat. In both of the above embodiments, the semiconductor chip die-bonded to the wiring board may be a chip whose surface is previously undercoated with a resin such as epoxy, silicone, or polyimide to improve moisture resistance. As described above, according to the present invention, by sealing a semiconductor chip using a sealing resin sheet made of a mixture of plate-shaped fiber materials, it is possible to prevent the resin from swelling into a hemispherical shape as in conventional devices. Furthermore, since the semiconductor chip is die-bonded to the bottom of the recess formed in the wiring board, the thickness of the wiring board can be utilized, making it possible to obtain an even thinner device.
また繊維サイズが決定されれば、樹脂と繊維材の漏れに
より繊維が樹脂の広がりを防いで所望形状の半導体装置
を得ることができる。Further, once the fiber size is determined, the fibers can prevent the resin from spreading due to leakage of the resin and the fiber material, and a semiconductor device having a desired shape can be obtained.
第1図A,bは従来装置の断面図、第2図は本発明によ
る実施例の断面図、第3図は本発明による他の実施例の
断面図である。
1・・・・・・配線基板、2・・・・・・半導体チツプ
、4・・・・・・凹部、5・・・・・・配線導体、6・
・・・・・ワイヤ、7・・・・・・封止樹脂シート。1A and 1B are cross-sectional views of a conventional device, FIG. 2 is a cross-sectional view of an embodiment according to the present invention, and FIG. 3 is a cross-sectional view of another embodiment according to the present invention. DESCRIPTION OF SYMBOLS 1...Wiring board, 2...Semiconductor chip, 4...Recess, 5...Wiring conductor, 6...
... wire, 7 ... sealing resin sheet.
Claims (1)
部上面に導体端子が形成された配線基板と、該配線基板
の上記凹部底面にダイボンドされ、導体端子との間が導
体によつて電気的接続された半導体チップと、上記凹部
開口を封止し且つ繊維材を含有する平板状樹脂シートと
からなる半導体装置。1. An electrical connection is established between a wiring board in which a recess for accommodating a semiconductor chip is formed and a conductor terminal is formed on the top surface of the recess, and a conductor terminal that is die-bonded to the bottom surface of the recess of the wiring board. 1. A semiconductor device comprising: a semiconductor chip having a molded structure; and a flat resin sheet containing a fiber material and sealing an opening of the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54039049A JPS5925383B2 (en) | 1979-03-30 | 1979-03-30 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54039049A JPS5925383B2 (en) | 1979-03-30 | 1979-03-30 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55132058A JPS55132058A (en) | 1980-10-14 |
| JPS5925383B2 true JPS5925383B2 (en) | 1984-06-16 |
Family
ID=12542263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54039049A Expired JPS5925383B2 (en) | 1979-03-30 | 1979-03-30 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5925383B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62127185A (en) * | 1985-11-26 | 1987-06-09 | Ishikawajima Harima Heavy Ind Co Ltd | Bar joining method |
| WO2011149339A1 (en) | 2010-05-26 | 2011-12-01 | Netherlands Organisation For Scientific Research (Advanced Chemical Technologies For Sustainability) | Preparation of caprolactone, caprolactam, 2,5-tetrahydrofuran-dimethanol, 1,6-hexanediol or 1,2,6-hexanetriol from 5-hydroxymethyl-2-furfuraldehyde |
| WO2019021945A1 (en) | 2017-07-26 | 2019-01-31 | 国立大学法人北陸先端科学技術大学院大学 | Photoresponsive nucleotide analog capable of photocrosslinking in visible light region |
-
1979
- 1979-03-30 JP JP54039049A patent/JPS5925383B2/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62127185A (en) * | 1985-11-26 | 1987-06-09 | Ishikawajima Harima Heavy Ind Co Ltd | Bar joining method |
| WO2011149339A1 (en) | 2010-05-26 | 2011-12-01 | Netherlands Organisation For Scientific Research (Advanced Chemical Technologies For Sustainability) | Preparation of caprolactone, caprolactam, 2,5-tetrahydrofuran-dimethanol, 1,6-hexanediol or 1,2,6-hexanetriol from 5-hydroxymethyl-2-furfuraldehyde |
| WO2019021945A1 (en) | 2017-07-26 | 2019-01-31 | 国立大学法人北陸先端科学技術大学院大学 | Photoresponsive nucleotide analog capable of photocrosslinking in visible light region |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55132058A (en) | 1980-10-14 |
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