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JPS5925386B2 - Mounting body and mounting method - Google Patents
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JPS5925386B2 - Mounting body and mounting method - Google Patents

Mounting body and mounting method

Info

Publication number
JPS5925386B2
JPS5925386B2 JP55031211A JP3121180A JPS5925386B2 JP S5925386 B2 JPS5925386 B2 JP S5925386B2 JP 55031211 A JP55031211 A JP 55031211A JP 3121180 A JP3121180 A JP 3121180A JP S5925386 B2 JPS5925386 B2 JP S5925386B2
Authority
JP
Japan
Prior art keywords
chip
openings
insulating film
polyimide resin
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55031211A
Other languages
Japanese (ja)
Other versions
JPS56129356A (en
Inventor
賢造 畑田
勇 北広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55031211A priority Critical patent/JPS5925386B2/en
Publication of JPS56129356A publication Critical patent/JPS56129356A/en
Publication of JPS5925386B2 publication Critical patent/JPS5925386B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07173Means for moving chips, wafers or other parts, e.g. conveyor belts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/10Configurations of laterally-adjacent chips

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 ラジオ、テレビ、ビデオテープレコーダ等の電子機器は
、小型、薄型化の方向にある。
DETAILED DESCRIPTION OF THE INVENTION Electronic devices such as radios, televisions, and video tape recorders are becoming smaller and thinner.

このために、これら電子機器を構成する電子部品も、例
えば抵抗器にあつては両端にリード線を有したソリッド
抵抗から数n角のセラミック基板に抵抗体層を印刷した
チップ抵抗へと変つていつた。更にコンデンサにしても
同様の数u角の電解層を積層したチップコンデンサに変
つた。又、工Cの実装においてもDILタイプのパッケ
ージから薄型、小型化されたフラットパック型のパッケ
ージが使用される様になつてきた。これら小型、薄型化
された電子部品を用いた実装によつて電子機器は徐々に
小型、薄型化が実現されてきているが、近年ICの実装
個数が増大するにつれて、前記ICの実装方法は問題視
されてきた。
For this reason, the electronic components that make up these electronic devices, for example, in the case of resistors, have changed from solid resistors with lead wires at both ends to chip resistors, in which a resistor layer is printed on a ceramic substrate several nanometers square. It was. Furthermore, capacitors also changed to chip capacitors, which were made by laminating electrolytic layers several square meters in size. Also, in the packaging of engineering C, flat pack type packages, which are thinner and smaller, have come to be used instead of DIL type packages. Electronic devices are gradually becoming smaller and thinner through mounting using these smaller and thinner electronic components, but as the number of ICs mounted has increased in recent years, the method of mounting the ICs has become problematic. has been looked at.

ICそのものはSiチップ上に回路機能が半導体技術に
よつて組み込まれたものであつて、前記Siチップの大
きさが、実際のICの大きさである。このIC(例えば
Siチップ)の大きさでは、プリント基板等に実装する
時に、取扱いが著しく困難であるから前記Siチップに
設けられた電極端子を拡大し、取扱いが容易な様にDI
Lノ 型やフラットパック型が用いられるのである。と
ころが、このために実装面積が前記Siチップよりも著
しく大きくなる。例えば5nで60ピン程度のLSIの
場合、フラットパック型でパッケージすると、その実装
面積は22X22nの大きさとj なりSiチップの約
20倍にも達して、ICの実装個数の増大に伴ない、電
子機器の実装平面積が増大する事になる。本発明は、I
Clチツプ抵抗、チツプコンデンサ等の電子部品を高密
度にしかも薄型に実装する事を目的とする。
The IC itself has circuit functions built into a Si chip using semiconductor technology, and the size of the Si chip is the actual size of the IC. The size of this IC (for example, a Si chip) makes it extremely difficult to handle when mounted on a printed circuit board, etc., so the electrode terminals provided on the Si chip were enlarged to make it easier to handle.
L-shaped and flat pack types are used. However, for this reason, the mounting area becomes significantly larger than that of the Si chip. For example, in the case of a 5n LSI with about 60 pins, if it is packaged in a flat pack type, its mounting area will be 22 x 22n, which is about 20 times that of a Si chip. This results in an increase in the mounting area of the device. The present invention is based on I
The purpose is to mount electronic components such as Cl chip resistors and chip capacitors in a high density and thin manner.

第1図は従来の実装方法で比較的高密度と思われる実装
方法を説明する。
FIG. 1 illustrates a conventional mounting method that is considered to have relatively high density.

第1図では特にICの実装を主体に詳述する。厚さ1〜
3mmのセラミツク基板1上にスクリーン印刷法により
Au.Agあるいは銀・パラジウムの配線体2を形成す
る(第1図a)。
In FIG. 1, the details will be mainly focused on the implementation of the IC. Thickness 1~
Au. A wiring body 2 of Ag or silver/palladium is formed (FIG. 1a).

次にCu層3を形成する(第1図b)。前記Cu層3は
抵抗加熱、スパツタ一等の真空蒸着法や電気メツキ法に
より数10〜数100μmの厚さに形成されるものであ
る。前記Cu層3を光蝕刻法により任意の形状パターン
jを設ける(第1図c)。次に電極端子5を有するIC
チツプ4を前記セラミツク基板1上に導電性接着剤等で
固定する(第1図d)。Cuパターン3′およびICチ
ツプ4が載置されたセラミツク基板上にポリイミイド樹
脂層6を設ける(第1図e)。前記ポリイミイド樹脂層
6の形成は、前記1Cチツプよりも厚いポリイミイド樹
脂フイルムを前記1Cチツプ上より加熱、加圧する事に
よつて第1図eの構造を得るか、他の形成方法として液
状のポリイミイド樹脂を、回転塗布する事によつて形成
しても良い。次に前記1Cチツプ4の電極端子5上およ
びCuパターンj上の前記ポリイミイド樹脂6を開孔し
て開孔部7,8を形成する(第1図f)。
Next, a Cu layer 3 is formed (FIG. 1b). The Cu layer 3 is formed to a thickness of several tens to several hundred micrometers by resistance heating, vacuum deposition such as sputtering, or electroplating. A pattern j having an arbitrary shape is formed on the Cu layer 3 by photoetching (FIG. 1c). Next, an IC having an electrode terminal 5
The chip 4 is fixed onto the ceramic substrate 1 with a conductive adhesive or the like (FIG. 1d). A polyimide resin layer 6 is provided on the ceramic substrate on which the Cu pattern 3' and the IC chip 4 are mounted (FIG. 1e). The polyimide resin layer 6 can be formed by heating and pressurizing a polyimide resin film thicker than the 1C chip from above the 1C chip to obtain the structure shown in FIG. The resin may be formed by spin coating. Next, holes are opened in the polyimide resin 6 on the electrode terminal 5 of the 1C chip 4 and on the Cu pattern j to form openings 7 and 8 (FIG. 1f).

開孔部7,8の形成は、前記ポリイミイド樹脂6上に感
光性樹脂を塗布し光蝕刻法によつて実施できる。開孔部
7,8が形成された面に蒸着法によりCr・Cu膜を被
着し、前記開孔部7,8同志を接続する様に光蝕刻法に
より配線パターン9を形成する事により第1図gの構造
を得る。
The openings 7 and 8 can be formed by applying a photosensitive resin onto the polyimide resin 6 and performing photoetching. A Cr/Cu film is deposited by vapor deposition on the surface where the openings 7 and 8 are formed, and a wiring pattern 9 is formed by photoetching to connect the openings 7 and 8. Obtain the structure shown in Figure 1g.

第1図の製法による実装方法では、ICチツプの実装が
チツプの状態で実施されるので高密度の実装が実現でき
るが、次の様な欠点がある。
In the mounting method using the manufacturing method shown in FIG. 1, since the IC chip is mounted in the chip state, high-density mounting can be achieved, but it has the following drawbacks.

1万一、ICチツプが不良の場合1Cチツプの交換が出
来ない。
In the unlikely event that the IC chip is defective, the 1C chip cannot be replaced.

2第1図gの構造を得るのにプロセスの工数が多すぎて
、歩留りが低下する。
2. The number of process steps required to obtain the structure shown in FIG. 1g is too large, resulting in a low yield.

3更にセラミツク基板の厚みを必要とするために実装体
の厚みが増加する事になる。
3. Furthermore, since the thickness of the ceramic substrate is required, the thickness of the mounted body increases.

本発明は従来のこの様な欠点を一掃せんとするものであ
る。
The present invention aims to eliminate these conventional drawbacks.

第2図において本発明を詳述する。例えば35m1L巾
の長尺のポリイミイド樹脂フイルム11にあらかじめ複
数の開孔部12を形成する(第2図a)。前記ポリイミ
イド樹脂フイルム11の板厚は約125μm程度で、前
記開孔部12にはICおよびチツプ抵抗、チツプコンデ
ンサ等の電子部品が挿入されるためのものである。次い
で35μm厚さのCu箔13を貼りつけ(第2図b)、
前記複数の開孔部12に突出すると同時に前記複数の開
孔部12間を選択的に接続するCuリード配線13/を
光蝕刻法で形成する(第2図c)。前記Cuリード配線
13′は後述するICやチツプ部品の電極端子に相応す
る部分に形成されるものである。前記開孔部12とほぼ
合致する複数の開孔部を有するNi板(厚さ0.1〜0
.2μm)14を接着剤15によつて前記ポリイミイド
樹脂フイルム11上に貼りつける(第2図d)。次にチ
ツプ部品17の電極端子上には半田バンプ16を形成し
ておき、前記開孔部12に挿入し、加熱治具20を30
0〜400℃に加熱し、Cuリード配線1S上から加圧
21すれば、前記チツプ部品17の電極端子はCuリー
ド配線に半田づけ固定される事になる。又1C18の場
合も同様に電極端子上に半田バンプ19あるいはAuバ
ンプを形成しておき、前記Cuリード配線131とを位
置合せし、加熱治具2σにより加熱加圧217する事に
より、ICの電極端子は前記Cuリード配線13′に半
田づけあるいは、前記α リード配線13′上にSnメ
ツキを施しておけばAu−Snの共晶を形成させ、接続
する事が出来るものである(第2図e)。最後にエポキ
シ樹脂あるいはシリコーン樹脂等の保護膜22,2グを
塗布し、硬化させれば第2図fの構造を得る事が出来る
The invention is explained in detail in FIG. For example, a plurality of openings 12 are formed in advance in a long polyimide resin film 11 having a width of 35 m1L (FIG. 2a). The thickness of the polyimide resin film 11 is approximately 125 μm, and the openings 12 are for inserting electronic components such as ICs, chip resistors, and chip capacitors. Next, a 35 μm thick Cu foil 13 was pasted (Fig. 2b),
Cu lead wires 13/ that protrude into the plurality of openings 12 and selectively connect between the plurality of openings 12 are formed by photolithography (FIG. 2c). The Cu lead wiring 13' is formed in a portion corresponding to an electrode terminal of an IC or chip component, which will be described later. A Ni plate (thickness 0.1 to 0.0
.. 2 μm) 14 is pasted onto the polyimide resin film 11 using an adhesive 15 (FIG. 2d). Next, solder bumps 16 are formed on the electrode terminals of the chip component 17, and the solder bumps 16 are inserted into the openings 12, and the heating jig 20 is
By heating to 0 to 400 DEG C. and applying pressure 21 from above the Cu lead wiring 1S, the electrode terminals of the chip component 17 are soldered and fixed to the Cu lead wiring. In the case of 1C18, solder bumps 19 or Au bumps are similarly formed on the electrode terminals, aligned with the Cu lead wiring 131, and heated and pressurized 217 using a heating jig 2σ to form the IC electrodes. The terminal can be connected by soldering to the Cu lead wiring 13' or by applying Sn plating to the α lead wiring 13' to form an Au-Sn eutectic (see Fig. 2). e). Finally, a protective film 22, 2 made of epoxy resin or silicone resin is applied and cured to obtain the structure shown in FIG. 2f.

更に本発明の場合、前記したNi板を用いクロスオーバ
の配線を実施する事が出来る。
Furthermore, in the case of the present invention, crossover wiring can be implemented using the above-mentioned Ni board.

第3図でこれを説明する。ポリイミイド樹脂フイルム1
1を開孔し、Nl板14/を露出させ、Cuリード配線
231と23!′ とを前記露出しているNi板147
上に半田づけ固定すればNi板14′によつて、前記0
1リード配線23′と23″とを接続する事が出来る。
第3図においてNi板14′上には前記Cuリード配線
231,23″と交叉する配線131がポリイミイド樹
脂フイルム1『上に形成されている。本発明において、
樹脂フイルムとして、ポリイミイドを用いてきたが、ポ
リエチレン、ポリエステル、人造マイラ一等のフイルム
でも良いし、Ni板はFe板、Bs板等の導電性を有し
、機械的強度を有するものであれば、Ni板に限定され
るものではない。
This will be explained in FIG. Polyimide resin film 1
1 is opened to expose the Nl plate 14/, and the Cu lead wirings 231 and 23! ' and the exposed Ni plate 147
If the Ni plate 14' is soldered and fixed to the top, the 0
1 lead wires 23' and 23'' can be connected.
In FIG. 3, on the Ni plate 14', a wiring 131 that intersects with the Cu lead wirings 231, 23'' is formed on the polyimide resin film 1''. In the present invention,
Polyimide has been used as the resin film, but films of polyethylene, polyester, artificial mylar, etc. may also be used, and the Ni plate may be a Fe plate, Bs plate, etc. as long as it has conductivity and mechanical strength. , is not limited to Ni plates.

第4図は第2図の平面図である。FIG. 4 is a plan view of FIG. 2.

ポリイミイド樹脂フイルム11上には、あらかじめIC
l8やチツプ部品17を挿入するための開孔部12を有
している。
An IC is placed on the polyimide resin film 11 in advance.
It has an opening 12 for inserting a tip 18 and a chip part 17.

前記ポリイミイド樹脂フイルム11上には、CuI]−
ド配線13′が形成される。前記Cuリード配線13′
は前記開孔部12において挿入されるCl8やチツプ部
品17の電極端子と対応する位置まで、配線を延在した
構造であり、更にCuリード配線13〃の如く、開孔部
12を横断した構造に形成されるものである。前記開孔
部12に延在したCuリード配線はICl8の電極端子
上のバンプ19やチツプ部品17の電極端子上のバンプ
16と接合されている。又、前記ポリイミイド樹脂フイ
ルム11のCuリード配線13′の形成されていない反
対面に機械的強度を増すための基体と構成された回路を
外部回路と接続するための端子とを一体に構成したNi
板14が貼りつけられている。
On the polyimide resin film 11, CuI]-
A field wiring 13' is formed. The Cu lead wiring 13'
is a structure in which the wiring extends to a position corresponding to the electrode terminal of the Cl 8 or chip component 17 inserted in the opening 12, and furthermore, a structure that crosses the opening 12, such as the Cu lead wiring 13. It is formed in The Cu lead wire extending into the opening 12 is connected to the bump 19 on the electrode terminal of the ICl 8 and the bump 16 on the electrode terminal of the chip component 17. Further, on the opposite side of the polyimide resin film 11 on which the Cu lead wiring 13' is not formed, a Ni film is formed, which integrally has a base for increasing mechanical strength and a terminal for connecting the constructed circuit to an external circuit.
A board 14 is attached.

前記Ni板は前記ポリイミイド樹脂フイルム11の開孔
部12とほぼ同じ寸法の開孔部を有する一方、外部回路
と接続するための外部端子35を有していて、前記外部
端子35には、延在したCuリード配線13′7が半田
づけ固定されている。点線36は前記Ni板14の不要
部分を切断する位置を示すものである。外部端子35は
前記ポリイミイド樹脂フイルム11に接着固定されてい
る。本発明の更に効果的な製法として、例えば第5図に
示す如くポリイミイド樹脂フイルム11の開孔部12に
延在したCuリード配線13′が折れ曲がつてしまい、
ICやチツプ部品のバンブと接続出来ないという事故を
妨ぐために、第6図に示す如く〜例えば0.1〜0.3
11程度の絶縁板35を前記へ リード配線13′上に
置き、接着剤36で固定すれば、前述した如くの事故を
防止できるものである。
The Ni plate has an opening having approximately the same size as the opening 12 of the polyimide resin film 11, and has an external terminal 35 for connection to an external circuit. The existing Cu lead wiring 13'7 is fixed by soldering. A dotted line 36 indicates the position where the unnecessary portion of the Ni plate 14 is cut. The external terminal 35 is adhesively fixed to the polyimide resin film 11. As a more effective manufacturing method of the present invention, for example, as shown in FIG. 5, Cu lead wiring 13' extending into the opening 12 of the polyimide resin film 11 is bent.
In order to prevent accidents such as not being able to connect with the bumps of IC or chip parts, as shown in Figure 6,
By placing about 11 insulating plates 35 on the lead wiring 13' and fixing them with adhesive 36, the above-mentioned accident can be prevented.

第7図はチツプ部品を半田づけした場合の断面図を示し
たものである。次に本発明の第2図の実施例を量産的に
生産する場合の概略を第8図で説明する。
FIG. 7 shows a cross-sectional view of the chip parts soldered. Next, an outline of mass production of the embodiment of the present invention shown in FIG. 2 will be explained with reference to FIG. 8.

あらかじめ送り用の穴50を形成したポリイミイド樹脂
フイルム51はガイドローラ52によつてステツプ15
3に送りこまれ、所望の形状をしたパンチングマシン5
4によつてIC、チツプ部品を挿入するための開口部5
5を形成する。次のステツプ56においで例えば35μ
m厚の接着剤を塗布したCu箔57をガイドローラ58
と59の間を通過させる事により前記ポリイミイド樹脂
フイルム51と貼り合せる。ステツプ60においては感
光性樹脂61をノズル62より隣接させたガイドローラ
63,63′に滴下し、前記Cu箔57上に一定の膜厚
を塗布せしめ、ステツゾ64で前記感光性樹脂膜を赤外
線ランプ65で乾燥させる。ステツプV66はマスク露
交工程で、Cuリード配線を形成させるためのパターン
67を有するマスク68を前記感光性樹脂を塗布したポ
リイミイド樹脂フイルム51上に接着せしめ、紫外線ラ
ンプ69によつて紫外光70を照射させる。ガイドロー
ラ71によつて露光された感光性樹脂膜を有するポリイ
ミイド樹脂フイルム51はステツプ72へ送りこまれる
。前記ポリイミイド樹脂フイルム51は現像液73を満
したタンク74中を通過する事により、感光性樹脂によ
るCuリード配線のパターン75を現出させ、ステツプ
76において、現像により膨潤した前記感光性樹脂パタ
ーン75を赤外線ランプJモVより硬化せしめる。次にス
テツプ78において前記感光性樹脂パターン75を蝕刻
用のマスクとして、露出しているCu箔をエツチング除
去する。エツチング用の液はノズル79より噴射される
ものである。ステツプ80によつて補強用のNi板81
をガイドローラ82,82′によつて圧着し、接着剤等
で貼り合せる。
The polyimide resin film 51 with feeding holes 50 formed in advance is moved to step 15 by the guide roller 52.
3, the punching machine 5 forms the desired shape.
4 opens an opening 5 for inserting IC and chip components.
form 5. In the next step 56, for example, 35μ
A Cu foil 57 coated with m-thick adhesive is placed on a guide roller 58.
and 59 to bond it to the polyimide resin film 51. In step 60, the photosensitive resin 61 is dropped from the nozzle 62 onto the adjacent guide rollers 63, 63' to coat the Cu foil 57 to a certain thickness, and the photosensitive resin film is exposed to an infrared lamp using the stepper 64. Dry at 65°C. Step V66 is a mask exposure process in which a mask 68 having a pattern 67 for forming Cu lead wiring is adhered onto the polyimide resin film 51 coated with the photosensitive resin, and ultraviolet light 70 is irradiated with an ultraviolet lamp 69. irradiate. The polyimide resin film 51 having the exposed photosensitive resin film is sent to step 72 by the guide roller 71 . The polyimide resin film 51 passes through a tank 74 filled with a developer 73 to reveal a Cu lead wiring pattern 75 made of photosensitive resin, and in step 76, the photosensitive resin pattern 75 swelled by development is removed. harden it using an infrared lamp JMoV. Next, in step 78, the exposed Cu foil is etched away using the photosensitive resin pattern 75 as an etching mask. The etching liquid is sprayed from a nozzle 79. Ni plate 81 for reinforcement by step 80
are pressed together by guide rollers 82, 82' and bonded together with adhesive or the like.

前記Ni板81は長尺の板であつて、前記ポリイミイド
樹脂フイルム51に設けてあるチツプ部品を挿人するた
めの開孔部55′と外部端子83を設けてある。ステツ
プX84は、IClチツプ部品の電極端子上に設けた半
田バンプとCuリード配線85とを半田づけする工程で
ある。IC86、チツプ抵抗87、チツプコンデンサ8
8は各々専用のトレイ86/,87/,881上に搭載
されており、前記トレイ86′,87′,88′は各々
の開孔部55下に搬送され、加熱した治具89が降下し
、半田づけを行なうものである。C、チツプ部品の半田
づけされたものは、ステップ190の工程へと運ばれ、
型抜き用のパンチングマシン91により、92の如く最
終的な形状に切断されるものである。この様に本発明の
構成は、一貫した量産システムを構成する事が出来るも
のである。次に本発明の効果を実施例の効果を説明しつ
つのべる。
The Ni plate 81 is a long plate, and is provided with an opening 55' into which a chip component provided on the polyimide resin film 51 is inserted, and an external terminal 83. Step X84 is a process of soldering the Cu lead wire 85 to the solder bump provided on the electrode terminal of the ICl chip component. IC86, chip resistor 87, chip capacitor 8
8 are mounted on dedicated trays 86/, 87/, and 881, respectively, and the trays 86', 87', and 88' are conveyed below the respective openings 55, and the heated jig 89 is lowered. , for soldering. C. The soldered chip components are transported to step 190,
It is cut into the final shape as shown in 92 by a punching machine 91 for die cutting. As described above, the configuration of the present invention allows a consistent mass production system to be configured. Next, the effects of the present invention will be described while explaining the effects of Examples.

本発明の主要構成材料であるポリイミイド樹脂フイルム
が0.125m11補強用のNi板が0.1〜0.3m
1Lであるから構成される基板自体の厚みは、大体0.
4〜0.5mm程度であるから、薄型に実装出来るもの
である。
The polyimide resin film, which is the main constituent material of the present invention, is 0.125 m11 The Ni plate for reinforcement is 0.1 to 0.3 m
Since the thickness of the substrate is 1L, the thickness of the substrate itself is approximately 0.
Since it is about 4 to 0.5 mm, it can be mounted thinly.

更に本発明は前記ポリイミイド樹脂フイルムとNi板と
を主体とした基板配線の工程が終了してからIC5チツ
プ部品を半田づけする工程であるから、完成した基板配
線の良品とIClチツプ部品の良品同志を接続するもの
であるから、従来例に比べて著しく歩留りが高くなる。
Furthermore, since the present invention is a process in which IC5 chip components are soldered after the process of wiring the board mainly consisting of the polyimide resin film and the Ni plate is completed, there is no difference between the good finished board wiring and the good ICl chip parts. Since this method connects the two, the yield is significantly higher than that of the conventional example.

IClチツプ部品の電極端子上のバンプ材料を半田で構
成すると、万一前記1Cやチツプ部品の不良品を搭載し
たとしても、再度加熱治具で加熱する事により容易に着
脱し、良品と交換出来る等のシステムを構成する事がで
きるものである。
If the bump material on the electrode terminal of the ICl chip component is made of solder, even if a defective 1C or chip component is installed, it can be easily attached and detached by heating it again with a heating jig and replaced with a good one. It is possible to configure a system such as

本発明は基板配線の作成工程とチツプ部品を前記基板配
線に固定する工程とが全く別々の工程で行なわれるいわ
ゆる並列工法である。第1図に示した例は、基板にチツ
プ部品を載置し、ポリイミイド樹脂で哩設、次いで前記
チツプ部品の電極端子上を開孔し、全面に金属膜を蒸着
、光蝕刻法により配線パターンを形成する事によつて、
完成する、いわゆる直列工法である。例えば、2つの工
程からなる場合の歩留り(各々の工程の歩留りを90(
Lと仮定する)を比較すれば、直列工法の場合、0.9
×0.9=0.81で最終81(Ff)の歩留りとなる
のに対し、並列工法の場合、1−(0.1X0.1)二
0.99で最終歩留りは99(fl)となる。この様に
本発明の構成では、著しく高い歩留りを提供出来るもの
である。第1図の従来例の構成にあつては、万一、前記
ICやチツプ部品の不良品を搭載した場合、不良品のチ
ツプのみを取りはずし、交換する事が出来ない、何故な
らば、前記1Cやチツプ部品を交換するためには、ポリ
イミイド樹脂から前記1Cやチツプ部品を堀り起こさね
ばならない。
The present invention is a so-called parallel construction method in which the process of creating board wiring and the process of fixing chip components to the board wiring are performed in completely separate processes. In the example shown in Fig. 1, a chip component is placed on a board, covered with polyimide resin, holes are formed on the electrode terminals of the chip component, a metal film is deposited on the entire surface, and a wiring pattern is formed by photolithography. By forming
This is the so-called serial construction method. For example, the yield in the case of two processes (the yield of each process is 90 (
(assumed to be L), in the case of the serial construction method, it is 0.9
×0.9=0.81, resulting in a final yield of 81 (Ff), whereas in the case of parallel construction, 1-(0.1X0.1)20.99, the final yield is 99 (fl). . As described above, the configuration of the present invention can provide an extremely high yield. In the configuration of the conventional example shown in FIG. 1, if a defective IC or chip component is installed, it is not possible to remove and replace only the defective chip, because the 1C In order to replace the 1C and chip parts, it is necessary to excavate the 1C and chip parts from the polyimide resin.

このために、ICやチツプ部品の配線パターンは完全に
破損してしまう。更に新しいIClチツプ部品と交換し
えたとしても、最初のポリイミイド樹脂で埋設する工程
から開始しなければならないから、殆んどの場合、1チ
ツプの不良であつても全体を基板ごと不良としなければ
ならない、このために製造歩留りが著しく低下し、製造
コストが著しく高くなるものであつた。ところが本発明
の製造方法であれば、チツプ部品とリード上の接合部を
再度加熱治具で加熱する事により容易に着脱し、良品と
交換出来るものである。又、IC等を第1図の例以外の
方法で基板に搭載する場合、例えば、もつとも一般的で
あるフイルムキヤリヤ方式によると、ICチツプの電極
端子上のバンプとリードを接合する工程、更に前記IC
チツプの電極端子から延在したリードを配線基板に接合
する工程が必要であるばかりか、前記延在したリードを
配線基板に接合するための接合面積が必要となる。
As a result, the wiring patterns of ICs and chip components are completely damaged. Furthermore, even if it is possible to replace the ICl chip with a new ICl chip component, it is necessary to start from the initial embedding process with polyimide resin, so in most cases, even if one chip is defective, the entire board must be declared defective. Therefore, the manufacturing yield was significantly lowered and the manufacturing cost was significantly increased. However, with the manufacturing method of the present invention, by heating the joints on the chip parts and the leads again with a heating jig, the chips can be easily attached and detached and replaced with good products. Furthermore, when mounting an IC or the like on a substrate by a method other than the example shown in FIG. Said IC
Not only is a process necessary for bonding the leads extending from the electrode terminals of the chip to the wiring board, but also a bonding area is required for bonding the extended leads to the wiring board.

この接合面積の必要性はそのまま実装密度を低下させる
事によるから、高密度の実装が行なえなくなる。これに
対し、本発明はICチツプ上の電極端子とリードとの接
合のみで良いから、従来必要としていた、配線基板上で
の接合面積が不必要であるから、その分だけ高密度の実
装が行なえるものである。前記接合面積は一般にリード
長さを最低27nmとすれば2×(LSIチツプ周辺長
)77ZJの分だけ必要となるものである。更に本発明
の構成であれば、金属フイルムを構成回路の外部導出端
子(第4図の35)として利用出来るため、新たに外部
導出端子を附加する必要がないから、工数が少なく、低
価格な実装体を提供出来るものである。
The need for this bonding area directly reduces the packaging density, making it impossible to perform high-density packaging. In contrast, in the present invention, only the electrode terminals on the IC chip and the leads need to be bonded, so the bonding area on the wiring board, which was conventionally required, is unnecessary, and high-density packaging is possible accordingly. It can be done. Generally, if the lead length is at least 27 nm, the junction area is required to be 2×(LSI chip peripheral length) 77ZJ. Furthermore, with the configuration of the present invention, since the metal film can be used as the external lead-out terminal (35 in Figure 4) of the component circuit, there is no need to add a new external lead-out terminal, so the number of man-hours is reduced and the cost is low. It is possible to provide an implementation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a−gは従来の高密度化した実装方法の説明図、
第2図a−fは本発明の一実施例を示す断面説明図、第
3図は本発明の応用例を示す断面図、第4図は本発明の
完成品の一例の平面図、第5図、第6図、第7図は本発
明の応用例の説明図、第8図a−cは本発明の量産工程
の一例を示す斜視図である。
Figures 1a-g are explanatory diagrams of the conventional high-density mounting method;
Figures 2 a-f are cross-sectional explanatory views showing one embodiment of the present invention, Figure 3 is a cross-sectional view showing an application example of the present invention, Figure 4 is a plan view of an example of a finished product of the present invention, and Figure 5 6 and 7 are explanatory diagrams of application examples of the present invention, and FIGS. 8 a to 8 c are perspective views showing an example of the mass production process of the present invention.

Claims (1)

【特許請求の範囲】 1 複数の第1の開孔部を有する金属フレームと、前記
金属フレーム上に形成され、前記複数の第1の開孔部と
合致する複数の第2開孔部を有する絶縁性フィルムと、
前記絶縁性フィルム上に形成され、前記複数の第2の開
孔部に突出部を有すると同時に、選択的に前記第2の開
孔部間を接続する配線パターンと、前記複数の第1の開
孔部側から挿入、配置され、前記突出部と電極が接続さ
れた複数の素子片とを有する実装体。 2 絶縁性フィルムに複数の開孔部を形成する工程、前
記絶縁性フィルムに金属フィルムを接着する工程、前記
金属フィルムを食刻し、前記複数の開孔部に突出部を有
すると同時に選択的に前記開孔部を接続する配線パター
ンを加工する工程、前記絶縁性フィルムに前記絶縁性フ
ィルムの開孔部と合致した複数の開孔部を有する金属フ
レームを接着する工程、前記金属フレームの複数の開孔
部に複数の素子片を挿入し、前記突出部と前記複数の素
子片を挿入し、前記突出部と前記複数の素子片の電極と
を接合する工程、前記絶縁性フィルムおよび金属フレー
ムを所定の形状に切断する工程とからなる実装方法。
[Scope of Claims] 1. A metal frame having a plurality of first apertures, and a plurality of second apertures formed on the metal frame and matching with the plurality of first apertures. an insulating film,
a wiring pattern formed on the insulating film, having protrusions in the plurality of second openings and selectively connecting between the second openings; A mounting body including a plurality of element pieces inserted and arranged from the opening side and connected to the protrusion and electrodes. 2. A step of forming a plurality of openings in an insulating film, a step of adhering a metal film to the insulating film, etching the metal film, and forming protrusions in the plurality of openings while selectively processing a wiring pattern connecting the openings to the insulating film; bonding a metal frame having a plurality of openings that match the openings of the insulating film to the insulating film; and a plurality of the metal frames. a step of inserting a plurality of element pieces into the opening portion, inserting the protrusion and the plurality of element pieces, and joining the protrusion and the electrodes of the plurality of element pieces, the insulating film and the metal frame; A mounting method comprising the step of cutting the into a predetermined shape.
JP55031211A 1980-03-11 1980-03-11 Mounting body and mounting method Expired JPS5925386B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55031211A JPS5925386B2 (en) 1980-03-11 1980-03-11 Mounting body and mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55031211A JPS5925386B2 (en) 1980-03-11 1980-03-11 Mounting body and mounting method

Publications (2)

Publication Number Publication Date
JPS56129356A JPS56129356A (en) 1981-10-09
JPS5925386B2 true JPS5925386B2 (en) 1984-06-16

Family

ID=12325090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55031211A Expired JPS5925386B2 (en) 1980-03-11 1980-03-11 Mounting body and mounting method

Country Status (1)

Country Link
JP (1) JPS5925386B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0636465B2 (en) * 1988-01-22 1994-05-11 イビデン株式会社 Continuous substrate for mounting electronic parts and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5216665A (en) * 1975-07-28 1977-02-08 Sharp Kk Electronic device

Also Published As

Publication number Publication date
JPS56129356A (en) 1981-10-09

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