JPS5925391B2 - semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable element incorporated into a semiconductor integrated circuit.

An object of the present invention is to provide continuous and accurate adjustment means in a semiconductor integrated circuit.

Conventionally, trimming (adjustment) using elements inside a semiconductor integrated circuit (IC) has been impossible, whether it is a resistor or a capacitor. A method has been adopted in which a large number of elements having the following characteristics are incorporated and selected.

However, this method does not allow precise trimming, creates wasted area in the IC, and is not reliable enough, so the number of steps is only slightly limited. only used. For this reason, if accurate adjustment is required, trimming is usually done using an external volume control, variable capacitor, or laser trimming. However, this is the biggest obstacle in pursuing miniaturization and cost reduction. The present invention eliminates these drawbacks and uses a charge injection device as an element that can be continuously and accurately trimmed within an IC.

This charge injection device is monolithically formed on a semiconductor substrate, and an example of this is a floating gate avalanche injection device (FAMOS) conventionally used in nonvolatile memories.
The structure of FAMOS is as shown in Fig. 1, and the voltage (usually 30
When a voltage of about V to 50 V is applied, electrons in the drain having an energy higher than the lower end of the SiO26 conductor are accelerated by the electric field, injected into the SiO2, and accumulated in the floating gate 3. The conductance of the MOS channel and the equivalent capacitance of the MOS diode change depending on the amount of charge stored in the floating gate. That is, F.A.M.
The OS can be used in two ways: variable resistance type or variable capacitance type. First, the case where FAMOS is used as a variable resistance type will be explained.

FIG. 2 shows an example of a method for controlling channel conductance while monitoring the amount of charge injection. Make two FAMOS of the same size, connect the gates, and use one for writing and the other for monitoring. The write power supply 11 applies a voltage that causes the drain of the FAM0S9 to avalanche against the substrate. F.A.M.O.
Since the amount of charge injected into each of S9 and IO is the same, the amount of charge injected into FAMOS9 can be determined by measuring the current flowing through the monitor 10 with the current detector 12, and the conductance of the channel at that time can be determined. know. Monitor F
Current flowing through AMOS and therefore FAM for writing
By continuously and accurately controlling the amount of charge injected into the OS, the conductance of the FAMOS channel,
That is, resistance can be controlled continuously and accurately. A case in which writing is performed using a P-channel FAMOS will be described below.

Figures 3-a and 3-b show the memory write power supply 11.
Here is an example. Figure 3-a simply shows a power supply and a switch (mechanical or electronic) connected in series.
This makes it impossible to precisely control the amount of charge injection. Therefore, as shown in FIG. 3-b, a writing pulse generator 15 is combined with a power source so that the amplitude, pulse width, and pulse generation cycle can be arbitrarily varied. This makes it possible to continuously change the amount of charge injection. As an example of the detector 12 of the current flowing to the monitor, in addition to using an ammeter, as shown in the example shown in FIG. It is conceivable to provide a feedback circuit so that the comparison can be made, and when a match is found, the switch of the write power supply 11'' can be opened or the pulse generator can be stopped.

An example of the comparator section 17 is shown in FIG. 5, and examples of the write power supply 11'' are shown in FIGS. 6-a and 6-b. In FIG. 5, the comparator output VO is -0 when the input voltage VR is higher than Ref. When it is .6V.Vref or less, it becomes V2 (Zena voltage).The power supply for writing is turned on and off by the output 18 of the comparator section.The case where the P channel FAMOS is used as a variable resistance type has been described above. , N-channel FAMOS can be used in the same way.

FIG. 7 shows an example in which a P-channel FAMOS is incorporated into the IC 2l and used as a variable resistor for trimming. FAMO for circuit parts that require resistor trimming
S22 is provided, and FAMOS23 for writing is used as a source.
It is provided connected to each of the gates, and its source and drain are provided as external terminals S and D. IC for trimming
Writing is performed during operation, and the output for monitoring is 0.
When the UT reaches the desired state, the write power supply 24 is turned off by the write power supply control unit 25 using its output, and the F
The amount of charge injected into the AMOS 23 and therefore into the FAMOS 22 is controlled to control the conductance. After trimming, the source and drain terminals S and D of the write FAMOS 23 are left open. When FAMOS is used as a variable capacitance type, a gate 26 is provided in addition to the floating gate 3 as shown in FIG. 8, and the capacitance between this gate and the substrate 8 is controlled.

FIG. 9 shows an example in which a P-channel FAMOS is incorporated into an IC and the capacitance is trimmed. FAMOS27 used as variable capacitor and FAMOS28 for writing
The source and gate of each are connected to each other, and source and drain terminals S and D for writing are provided. By performing writing while the IC is operating, and turning off the writing power supply 29 by the writing power supply control unit 30 when the monitor output reaches a desired state, the writing to the FAMOS 28 is performed.
Therefore, the amount of charge injected into the FAMOS 29 is controlled, and the capacitance is controlled. FAMOS2 for writing after trimming
The source and drain terminals S and D of 8 are left open. These methods are based on MNOS (Metal {Itride)
10xide-S (1rr1ic0nduct0r) and MAOS (MetalAllrllna{)Xide
It is also effective for trimming using a charge injection type memory such as -SmlcOnductOr), and has the advantage of being erasable and re-trimming possible.

By using these non-volatile memories as variable resistance type or variable capacitance type, it is no longer necessary to insert a resistor or capacitor with a value like a step in the IC as in the past, and the degree of integration can be increased. Continuous and accurate trimming is possible.

Further, since there is no need for trimming due to polyurethane, variable capacitors, etc., miniaturization and cost reduction 7 can be easily pursued. Further, the present invention uses two nonvolatile generating elements, connects one of the nonvolatile elements to the write power supply control section, and
Since the gates of two non-volatile elements are connected in common, the amount of charge injection can be continuously controlled by external operation, and the amount of control can be adjusted accurately, allowing for highly precise trimming. have an effect.

[Brief explanation of drawings]

FIG. 1 shows the structure of FAMOS. 1... Source, 2... Drain, 3... Floating gate, 4... Channel, 5... Depletion layer, 6... S
iO2 film, 7...source electrode, 7''...drain electrode, 8...substrate. Fig. 2 shows →l of the trimming method when the FAMOS of the present invention is used as a variable resistance type. 9 ...FAMOS for writing, 10...F for monitor
AMOS1ll... Power supply for writing, 12... Detector of the current flowing through the FAMOS for monitoring, 13... Drain terminal of the FAMOS for writing, 14... Drain terminal of the FAMOS for monitoring. Figures 3-a and 3-b show the writing power supply 1 in Figure 2.
An example of 1 is shown below. SW...Mechanical switch, Vcc...Power supply for writing, 15...Pulse generator for writing, 0UT...
At the output of the write pulse generator, in FIG. 3-a, the mechanical switch SW is in a state where the transistor operating as an electronic switch is turned ON. FIG. 4 shows an example of a detector for the current flowing through the monitor FAMOS shown in FIG. 16... Known reference resistance, 17... Comparator section, 18... Comparator section output, 11''... Writing electrode when the current detector is provided with a feedback circuit to the writing power source 11. VR... Voltage on the monitoring FAMOS side of the known reference resistor 16, Vref... Specified voltage. Fig. 5 shows an example of the comparator section 17 in Fig. 4. 19... Comparator, 20. ... Inverter buffer, Rl, R2 ... Input end protection resistor, VO...
Comparator output. Figures 6-a and 6-b show the writing power supply 1 in Figure 4.
15 examples are shown. Vcc: Power supply for writing, 0UT: Output of the pulse generator for writing, STOP: Terminal to stop the pulse generator for writing, input to this terminal when used with the comparator section in Figure 5. There is no output when is high. FIG. 7 shows an example of a trimming method when FAMOS is used as a variable resistance type inside an IC. 21...
IC chip, 22...FAMOS for variable resistance, 23.
...Writing FAMOS124...Writing power supply, 25...Writing power supply control unit, S...Writing FAMOS source terminal, D...Writing FAM
OS drain terminal, 0UT...output for monitor. FIG. 8 shows the structure of FAMOS when used as a variable capacitance type. 26...Terminal gate. FIG. 9 shows the trimming method →1 when FAMOS is used in C as a variable capacitance type. 27... FAMOS for variable capacitance 28... FAMOS for writing, 29... Power supply for writing, 30...
Power supply control unit for writing.

Claims (1)

[Claims] 1 has a first non-volatile memory element and a second non-volatile memory element, floating gates of the first and second non-volatile memory elements are connected in common, and the first non-volatile memory element has a The first non-volatile memory element is connected to the write power supply unit, and controls the amount of charge injected into the second non-volatile memory element according to instructions from the write power supply unit, and the first non-volatile memory element A semiconductor integrated circuit characterized in that a memory element is used as a variable resistance element or a variable capacitance element.