JPS5925502B2 - MSK signal synchronous demodulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on MSK (Minimum Shift Keyim).
g) That is, it relates to a synchronous demodulation method of a modulated signal generated by phase continuous FSK with a modulation index of 0.5 or a similar digital FM method.

Unlike AM and PSK signals, the phase continuous FSK signal has a constant envelope of the modulated wave, and the main spectrum is not affected by suppression due to output amplifier saturation, etc.
This is an advantageous modulation method for transmission lines that include these nonlinear systems.

In particular, a phase-continuous FSK signal with a modulation index of 0.5 is called an MSK signal, and has attracted attention as an efficient L-modulation method with a narrow occupied bandwidth.Generally, the received phase-continuous FSK signal is synchronously demodulated. In some cases, it is necessary to extract a synchronous carrier wave from the received modulated wave, but these modulated waves are a type of FM signal, and unlike PSK signals, multiplication alone cannot extract the bright line related to the center wave number. I can't get a spectrum (・
.

However, in the case of an MSK signal, its second harmonic wave has a modulation index of 1
．． 0 phase continuous FSK, (so-called Sunde's FSK
As is well known, fb is a positive and negative signal from the center frequency.
//! (fb-clock frequency) produces a bright line spectrum at a detuned frequency. Therefore, the conventional method was to extract these two emission line spectra using a phase-locked circuit or a tank circuit, step down the spectrum, and perform synchronous detection as a reference signal bound to the clock (RUDdeBU).
DA:! 1C0herentDem0du1ati0n
0fFrequencyShiftKeyingWit
hL0wDeviati0nRatiO! I; IEEE
trans. OnCOm. June 972). This method has a complex configuration and many adjustment points, and if the same code is continuously transmitted in the transmitter, synchronized operation is impossible, and four phase uncertainties occur when dividing two extracted waves. It required consideration. Apart from this, the reference signal is locally modulated with the demodulated code, and the phase is compared with the received signal.
A method of synchronous detection by configuring a so-called remodulation comparison type carrier-synchronized circuit has also been proposed (Morihiro, Furuya; Phase continuous FSK carrier-synchronized circuit; IEICE Technical Report CS-J
Kayo S). However, since this method requires the same circuit as the modulation system in the demodulation circuit, the configuration inevitably becomes complicated. Therefore, the present invention is intended to improve the above-mentioned drawbacks of the prior art.The purpose of the present invention is to realize a carrier synchronization circuit with a simple configuration, to save the number of required parts, and to replace each component with a digital logic element. The object of the present invention is to provide a demodulation circuit that is suitable for ultra-miniaturization.

The feature of the present invention is to perform the doubling operation of the input signal equivalently in the base band by comparing the sine and cosine phases of the human input signal and the reference signal, and by comparing the phases of the respective phase comparison outputs with each other, that is, by multiplying them. Line ℃゛, Fb //! generated in the basal band at this time! The objective is to establish phase synchronization of carrier waves by phase-detecting frequency components.

A detailed explanation will be given below with reference to the drawings. FIG. 1 is a block diagram of a synchronous demodulation circuit according to an embodiment of the present invention.

1 is an input signal, 2 is a sine synchronous detection signal, 3 is a cosine synchronous detection signal, 4 is a baseband multiplication signal, 5 is a synchronous timing clock signal, 6 is a 2-divided signal of the synchronous timing clock, 7 is a phase control 8 is a reference carrier wave, and 9 is a demodulated output signal.

Components 11 and 12 are phase comparators, 13 is a phase shifter, 14 and 15 are low-frequency r wave filters, 16 and 17 are phase comparators using multiplication circuits, 18 is a loop filter, and 19 is a voltage control An oscillator, 20 a divide-by-2 circuit, and 21 an identification and multiplexing circuit.

Input signal 1 is split into two and connected to phase comparators 11 and 12.

On the other hand, a reference carrier wave 8 generated by a voltage controlled oscillator 19
is divided into two, one is connected to the phase comparator 12 and the input signal is compared with the cosine phase π
π, the remaining one passes through one phase shifter 13,
After being given a phase rotation of -, it is connected to a phase comparator 11 to compare the sine phase with the input signal. two phase comparators 11
, 12 are outputted by low-frequency wave generators 14, 12, respectively.
15, the sine and cosine synchronous detection signal 2 of the input signal
, 3.

The signals 2 and 3 are phase-compared with each other in a phase comparator 16 to obtain a baseband double signal 4. The signal 4 is phase-compared with the timing clock divided-by-2 signal 6 by the phase comparator 17 (by taking the product), and the output is passed through a loop filter and then sent to the voltage controlled oscillator 19 as the control signal 7. Control to form a phase-locked loop.MS
Since the K signal essentially has a summation logic conversion effect on its modulation phase, the discrimination multiplexing circuit At 21° C., differential logic conversion is performed between the detection codes of the two detection sequences, and then the demodulated output 9 is obtained by multiplexing them into one code sequence.

Next, the operation of the carrier-locked loop, which is the main point of the present invention, will be explained with reference to the waveforms of each part shown in FIG.

Assuming that the phase difference between the input signal 1 and the reference carrier wave 8 is θ, the output of the phase comparator 16 has a sine phase comparison characteristic v=A sin 2θ (A is an arbitrary value) as shown in FIG. 2a.

This is used for carrier synchronization of PSK signals (COSTAS
This is a well-known format and indicates that the input signal is equivalently doubled in the base band. MS received here
The K signal corresponds to the mark or space of the transmitted information,
Assume that a phase transition of +1 or -1 occurs linearly in the time slot, and a certain moment when the state transitions is t = o, and the phase difference φD between the phase of the input signal and the phase of the reference carrier wave at this time is Then, the output signal v(t) of the phase comparator 16 becomes like the following 2π phase difference.

COs(2πf()t+ − t)φDb−0)−[Fig. 2b for three examples) QAc, d respectively v
(t) shows the waveform.

Here, if the clock signal divided by 2 signal 6 is taken as shown in FIG. 2e, the output of the phase comparator 11 is V. (t) becomes. Here, since the phase of 2πFbt in the first term rotates for one cycle, that is, 3600 rotations during one time slot 0-T, the DC component of the first term (long-term average value of the signal) is It becomes zero.

Therefore, V passed through the loop filter 18. The first term of (t) becomes zero due to the averaging function of the loop filter,
The DC component E becomes as shown in FIG. 2f, regardless of the transmission code.

The signal 7 after passing through the loop filter contains this DC component, which is used to control the phase of the reference carrier wave to form a synchronous loop.
If 9 is a characteristic in which the frequency increases with a positive control voltage and decreases with a negative voltage, then in Fig. This is a stable point.In this way, since the phase at which the reference carrier is synchronized has two uncertainties, o and π, the polarity of the coherent detection outputs 2 and 3 may be reversed (2 and 3 may be swapped). However, in the configuration example shown in FIG.
In step 1, differential logic conversion is performed, but in this process, the influence of uncertainty in the synchronization phase is automatically removed.As mentioned earlier, according to the present invention, each element is converted into digital logic. It is easy to configure using elements.

An example of the configuration in this case is shown in FIG. 31, 32, 38,
Reference numeral 39 denotes a flip-flop which has a function of sampling and holding the input code state at a certain point in time and outputting the sample, and a typical example of this is a delay flip-flop (D flip-flop) b.

33 is a voltage controlled oscillator having a two-phase output of o phase and ÷ phase;
Generally, this can be easily constructed using a quadruple wave multipipulator oscillator and a frequency divider circuit.

34, 35, 41, and 42 are exclusive ORs, 36 is a loop filter, and 31 is a 0-phase, 3-phase, frequency-divided-by-2 2-phase output generator for the clock signal, which is also realized with the same configuration as 31. can.

40 is a negative circuit.

1 to 9 are the same as those explained in FIG.

With such a configuration, the same operation as described with reference to FIG. 1 can be realized.

Delay flip-flops 31 and 32 are used as sine and cosine phase comparators, respectively (an input signal is applied to the zeta input of the delay flip-flop, and a reference signal is applied to the timing input), and the difference between the respective phase detection output signals 2 and 3 is If exclusive OR 34 is used as a phase comparison of the first
The low-frequency wave generators 14 and 15 explained in the figure are not required.
This exclusive OR output has a rectangular phase comparison characteristic as shown in FIG. 4a with respect to the phase difference θ between the input signal and the reference carrier wave. However, +1 and -1 are respectively binary logic levels.

It should be noted that the phase comparators 31 and 32 are not delay flip-flops, but SR flip-flops or exclusive OR and low-frequency wave generators. Assuming that the phase difference φD is the same as that explained in the figure, the output signal v of the exclusive OR 34 is
/(t) can be expressed as follows. The waveforms of v'(t) are shown in FIG. 4B, c, and d for three examples, respectively.

Here, the 2-frequency divided signal 6 of the clock signal is divided into 1 as shown in Fig. 4e.
(t)=SgnCcOs(πFbt)], and when the phase is compared with vl(t) in exclusive OR 35, the output will depend on the phase difference between v'(t) and r(t), as shown in FIG. Then, the duty ratio b'. A rectangular pulse varying with the determined Fb is obtained.

As is clear from FIG. 5, the average value of the output, ie, the DC component, is independent of marks and spaces and is determined by φo. Its value is.

This is illustrated in Figure 4f. The signal obtained by smoothing the rectangular pulse by the loop filter 36 following the exclusive OR 35 contains a DC component with a triangular characteristic as shown in FIG.
A synchronized loop is formed by controlling the phase of the reference carrier wave. From the phase comparison characteristic shown in FIG. 4f, there is an uncertainty of 0, π in the carrier synchronization phase. On the other hand, the clock frequency r/
When the polarity of (t) is reversed, the phase comparison characteristic is also reversed, and the carrier synchronization phase becomes π/2 or 3π/2. Next, the process of demodulating the transmitted code will be explained.

The MSK signal is (-π/
2, +π/2), so the sine and cosine phase detection outputs 2 and 3 are detected alternately in time,
They are connected to the data input terminals of delay flip-flops 38 and 39, respectively, and are alternately sampled and identified and reproduced using the optimum timing signal obtained from the clock signal divide-by-2 circuit 37. Assuming that these identification codes are Pi and Qi, the relationship between the codes Pi and Q and the transmission code Ai is related to the history from one bit before. As shown in Figure 6a, Pi)
Even if q is positive (“1” level), the previous bit q is positive (“1” level).
level) represents a space, and as shown in figure b, q
If is negative (“O”), it represents a mark.

That is, A2l-P2l4q2l-1 becomes.

Here, e indicates a logical operation of exclusive OR. Similarly, for the output of q, as shown in Figure 6C and d, the η peak is 0.
There is a relationship of q21-1(+)P21-2.

Therefore, when the cosine and sine detection/identification signals are mutually compared in the exclusive OR 41, the output shows the negation of the transmitted information every time slot.

Therefore, regarding the signs of odd subscripts, we corrected this by using the timing 2-frequency wave and the exclusive OR 42,
The transmitted code Ai can be correctly demodulated to the demodulated output 9. Since the 0 and π uncertainties in carrier synchronization invert both the identification codes P and q, the demodulated output is not affected. FIG. 7 shows the regenerated code sequence. Furthermore, when the polarity of the timing 2-frequency wave r(t) is reversed, the carrier synchronization phase changes to π/2 or 3π/2.
Therefore, the cosine/sine identification outputs are swapped. Ko1q214
P21-1 } A2l-1:P2l-14q21-2 In this case, the sign of the even subscript is inverted, but since the polarity of r(t) is inverted and becomes υ·, correct demodulation is always performed.

In this way, demodulation is possible by mutual differential logic conversion of each detection code. The operation of the present invention has been explained above using an ideal MSK signal as an example.

However, the synchronous demodulation method according to the present invention is not limited to such pure MSK, but is applicable to the same type of signal structure, that is, modulation in which each bit of the modulation code carries information alternately in in-phase and quadrature phase. It can be similarly applied to signal demodulation. An example of such a modulation signal is
Phase PSK, BFSK (S
inusOidalFSK), modified MSK that limits the baseband in the transmitter, and partial response FM.
There is TFM (TamedFM), which is a type of
SK (TamedFSK) (FRANKdeJAGER
and CORNELISBDEKKER; TamedF
requencyMOduIatiOn. ANOvel
MethOdtOAchleveSpectrur]1
Ec0n0myinDigita1Transmiss
i0n; IEEE Trans. OnCOMvOl. C.O.
M26! F25, Mayl978), etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the synchronous demodulation circuit according to the present invention, FIG. 2 is a block diagram of operation waveforms of each part of the circuit of FIG. 1, and FIG. 3 is a block diagram of another embodiment of the synchronous demodulation circuit according to the present invention. ,
4 shows the operating waveforms of each part of the circuit in Fig. 3, Fig. 5 shows the operating waveforms of the phase comparator, Fig. 6 shows the relationship between the detection output and the transmitted code, and Fig. 7 shows the reproduced code sequence. 1...Input signal, 2...Sine synchronous detection signal, 3...
・Cosine synchronous detection signal, 4... Baseband multiplied signal, 5
... Synchronous timing clock signal, 6... Frequency division signal, 7... Phase control signal, 8... Reference carrier wave, 9...
... Demodulated output π output signal Mi 11, 12 ... Phase comparator,
13...One phase shifter, 14,15...Low frequency waveform generator, 1
6, 17... Phase comparator, 18... Loop filter, 19... Voltage controlled oscillator, 20... 2 frequency divider circuit,
21...Identification multiplexing circuit, 31, 32, 38, 39.
... Delay flip-flop, 33... Voltage controlled oscillator, 34, 35, 41, 42... Exclusive OR circuit, 3
6...Loop filter, 37...2 frequency division two-phase output generator, 40...NOT circuit.

Claims (1)

[Claims] 1. A sine phase comparison and a cosine phase comparison of the MSK reception input signal and the reference signal are performed by two phase comparators to obtain detection outputs of in-phase and quadrature phase, respectively, and the detection outputs are converted into two detection outputs having an opposite phase relationship. After determining the sign using the divided timing clock signal,
A demodulated output is obtained by performing differential logic conversion on each other and alternately inverting the code of the code series obtained as an output using a frequency-divided timing clock signal, and a signal obtained by comparing the phases of the two detection outputs with each other. A synchronous demodulation method for an MSK signal, characterized in that the phase of the reference signal is synchronously controlled in accordance with the MSK reception input signal by multiplying the frequency of a timing clock by a signal divided by two, and using the direct current component of the product signal. 2 Apply the MSK receive input signal to the data inputs of two delay flip-flops, and apply reference numbers having a phase difference of π/2 from each other to the timing inputs of the delay flip-flops so that the outputs of the delay flip-flops are in-phase and After obtaining quadrature phase detection outputs and alternately identifying and judging the detection outputs using the frequency-divided-by-2 timing signals in respective delay flip-flops, the exclusive OR of these two signals is taken, and the frequency-divided output is divided by two with the exclusive OR output. A demodulated output is obtained by further performing an exclusive OR with the timing signal, and
Obtain the exclusive logic of the two detection outputs, take the exclusive OR of the output and the 2-frequency divided signal of the timing clock, and calculate the phase of the reference signal using the DC component of the output.
A synchronous demodulation method for MSK signals, characterized in that synchronous control is performed according to a K reception input signal.