JPS5926054B2 - Transmission/reception control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission/reception control circuit for a line adapter used in a data transmission system.

2. Description of the Related Art A control device for data transmission between a central processing device such as a computer and a terminal device is known.

Among these, HDLC (HighlevelDataLin
The present inventor has developed an LSI (Large Scale Integrated Circuit) capable of controlling the transmission of kControl) procedures and SYN synchronization procedures. This is, for example, line adapter (LA) 1 in Figure 1.
It is used as a connection part with the line 6 of , and has the configuration shown in FIG. FIG. 1 shows an outline of a terminal device, in which a central processing unit (CPU) 2 is connected to a main memory (MS) 4 and a line control channel (CMC) via a common bus 3.
) 5, etc., and the CMC 5 is further provided with subchannels such as a line adapter LA via an LA bus T.
Each line adapter 1 is provided corresponding to a line 6, and therefore an HDLC LSI is also provided for each line. The HDLC LSI shown in Fig. 2 has various features.
Regarding the procedure, (1) S-P (serial-parallel) conversion function of transmitting and receiving register, (2) "o" insertion and deletion function, (3) CRC (CyclicRe-dunda)
(4) NRZ 1 degree demodulation function,
It has (5) an interframe time pool (IFTF) function, (6) a minimum frame configuration (32 bit) check function, etc. The present invention relates to the transmission/reception control circuit section of such HDLC LSI. When transmitting and receiving data using HDLC procedures or synchronous basic transmission procedures, line adapter 1 may be controlled through a channel or directly by a program. Control is performed by issuing notifications (interruptions) indicating the state of the line.

IRQ in FIG. 2 indicates this interrupt. By the way, in the program and channel CMC, there are cases where transmission and reception cannot be performed, such as during initialization, when the reception buffer is full, and when preparations are not completed. Even in such a case, if you leave it as is, the adapter will generate an interrupt and send/receive it, and the sent/received data will need to be discarded or invalidated, so the program will be at least as complicated as this process. becomes. In view of the above, the present invention attempts to reduce the load on programs by providing oven and closing functions to the adapter, and includes a line adapter connected to a line and having a data register v, and a line adapter connected to the line adapter. provided in the adapter of the data transmission system consisting of a processing unit,
A transmission/reception control circuit that sends and receives data after generating an interrupt related to transmission/reception to the processing unit includes a transmission interrupt control circuit for issuing a transmission interrupt to the processing unit, and a reception interrupt control circuit for issuing a reception interrupt for the processing unit. an interrupt control circuit;
A transmitting side interrupt mask and a receiving side interrupt mask are provided to allow or prohibit the sending of an interrupt signal in the interrupt control circuit according to information given from the processing unit, and the transmitting interrupt control circuit is configured to detect whether the transmitting interrupt mask When the sending of signals is prohibited, the interrupt signal other than the interrupt signal indicating that the data register is empty is reset, and the mask is used to send an interrupt signal for the interrupt signal indicating that the data register is empty. The reception interrupt control circuit gates the transmission of interrupt signals to the processing unit while the reception interrupt mask is inhibiting the transmission of interrupt signals. The present invention is characterized in that the transmission of the interrupt signal to the processing section is prohibited by resetting the interrupt signal at certain times. This will be explained in detail below with reference to the drawings. FIG. 3 shows an embodiment of the present invention, and H in FIG.
This shows the part of DLCLSI related to the present invention.

The register specified by the register address RA from the program In this example, write data WD is written to the write data register 10, and when an interrupt is generated and a send ready signal is returned, the data is converted into serial data by the register register 11. It is then sent out over line 12. This write data is sent to the CRC calculation register 13, where it is calculated, a 2-byte FCS (frame check sequence) signal is created, and these signals FCS(1), FCS
(2) is sent out following the final data Dn (data is also in 1-byte units, so if there is a large number of data, it is sent as multiple bytes D1 to DO). The P/S register 11 has a flag creation function, and this flag F is attached before and after the signal frame. Therefore, one frame of each transmitted signal is flag F.
1 address A, control C1 data D1 to DOL, error check bits FCS(1), FCS(2), and flag F. On the other hand, the received data from the receiving line 14 is converted into parallel data by the S/P register 15 and set in the read data register 16. The data in the register 16 is taken in through the data selector 17, and
A check is performed in the RC calculation register 18. The above configuration is an outline of the transmitting/receiving end, and if compared with FIG. 2, the P/S register 11 and the S/P register 15 are included in the line S-P conversion control section 30.

As shown in Figure 2, there is an NR between the lines 12 and 14.
A ZI modulation circuit 31, an NRZ demodulation circuit 32, etc. are involved. The write data register 10 corresponds to the transmit data register 33 in FIG. 2, and the read data register 16 corresponds to the receive register groups 35 to 38 in FIG. The CRC calculation register 13 on the transmitting side corresponds to the register 43 in FIG. 2, and the CRC calculation register 18 on the receiving side corresponds to the CRC check circuit 39 in FIG. Further, a data selector 40 is interposed between the line S-P conversion control section 30 and the CRC calculation register 13 and transmission data register 33 on the transmission side. In the present invention, the HDLCLS is provided with a transmitter interrupt mask circuit 19, a receiver interrupt mask circuit 20, and an AND gate 25.

This LS is equipped with a transmission interrupt control circuit 21 and a reception interrupt control circuit 22 (both included in the interrupt control circuit 41 in FIG. 2), and has a function of applying an interrupt IRQ according to various states. However, this is done by interrupt mask circuits 19 and 20.
to limit. The interrupt mask circuits 19 and 20 are actually the second
It consists of one bit each in the mode register 42 shown in the figure. For transmission interrupt requests, SBE (cent buffer empty),
There are URE (underrun error), STO (cent time over), etc., and reception interrupt requests include RBF (
There are read buffer hook (c), CRCOK (check result good), ABORT (aport detection), IDLE (idle state detection), etc., but in the conventional method, an interrupt is immediately issued when these interrupt causes occur, and the transmission/reception is not performed as described above. Even when this is not possible, transmission and reception are performed with an interrupt, resulting in the inconvenience of having to perform wasteful processing such as discarding data. Therefore, in the present invention, if transmission/reception is not desired, the program sends the data and sets the receiving side interrupt masks 19 and 20 to the prohibited side (for example, "0" output state), so that even if an interrupt cause occurs, an interrupt signal is not generated. I tried not to.
To explain this with respect to FIGS. 4 and 5, a in these figures is a fixed pattern (e.g. 011
11110), address part A, control part C, data part Dl, D2, . . . , check bits FCS(1), FCS(2), and flag F.

FIG. 4 is a time chart explaining transmission control, in which b indicates notification to the program, c indicates writing to the register section TDO of the write data register 10, and d indicates writing to the register section TDl of the register 10. , e indicates the transmission oven closed state (6H" is oven, 5L" is closed) by the AND gate 25, and f indicates program processing. The reason why the register 10 is divided into TDO and TDl is because of the final data. In this example, D2 is By setting the data in the register section TDl and setting the previous data A-D1 in the register section TDO, it is possible to know whether the data is the final data on the LSI side, and by providing the CRC calculation register 13, the FCS (
1), FCS(2) signals can be created on the LSI side, and the final data can be automatically followed by FCS(1), FCS(2), without the help of a program.
and F can be sent, thus reducing the burden on the program. In this device, in order to transmit data, the transmitting side is first opened. In other words, the fourth
By processing the program shown in FIG. f, the level e shown in the same figure is set to 8H. Specifically, the relevant bit of the mode register in FIG. 2, which corresponds to the transmitting side interrupt mask circuit 19 in FIG. 3, is set to 01. This opens the AND gate 25, and if an interrupt cause such as cent buffer empty SBE occurs in the transmission interrupt control circuit 21 thereafter, it is sent out through the AND gate 25 and the OR gate 26, and an interrupt IRQ is applied. If the data is not to be transmitted continuously after one frame has been transmitted, the bit corresponding to the interrupt mask circuit 19 is set to "O" and the gate 25 is closed.In other words, the program processing shown in FIG. The level of e in the same figure is 6L1.
Make it. This closes the transmission. In addition, if you want to continue sending data, the interrupt mask circuit 19
61" and put it in the transmission oven state. If you want to send data again after it is closed, you can set it to the transmission oven at that point and send data using the same procedure as described above. Sending side The cause of interrupt occurrence is S
In addition to BE, there is an underrun error UREl transmission time over STO, etc., but other than SBE, it is meaningless to leave the cause of the interrupt in the close period, so the "0" setting of the interrupt mask circuit 19 is This also prevents the occurrence of interrupts.

On the other hand, since it is better to leave the cause of the interrupt in SBE, it is not set, but the gate 25 prohibits its transmission. On the receiving side, since no cause of interrupt remains, the output of the interrupt mask circuit 20 is simply reset, thereby inhibiting the occurrence of an interrupt. FIG. 5 is a time chart illustrating reception control, in which b indicates notification to the program, c reads data from the read data register 16, and d indicates reception oven control using the mask 20.
Closed ('''H'': oven, ``L'': closed) state; e indicates program processing.

In the case of data reception, the receiving oven can be closed arbitrarily by setting the mask 20 to 81° and 60° by program, as in the case of data transmission. In other words, during closing, no notifications such as RBF are made, and accordingly, no transmission is made to this LSI. While closed, receive buffer full (RBF), CRC check 0K (CR
COK) abort detection (ABORT), idle detection (
The registers to which various interrupt causes such as IDLE) are written are reset, and do not become interrupts IRQ. On the other hand, if the mask 20 is set to, for example, "1" as a reception oven through program processing, an interrupt related to reception will occur during that time, as shown in FIG. 5, and the transmission to and reception of this LSI will occur as scheduled. Conventional transmitting/receiving oven/
In the case of a method that does not use a close, if the transmitting side does not immediately write the next data to the register 10 upon notification of SBE after sending one frame, the sending side will not be notified of SBE after that and will not be able to write the next data. It is difficult to grasp the trigger when sending out.

Also, if the receiving side does not have an oven close function, if the program becomes unable to receive data, for example, data will be received even when the receive buffer is full (RBF), so the program will not be able to receive the data. You have to read and discard. On the other hand, if there is a close function as in the present invention, for example, on the receiving side, by closing the receiving side, there will be no subsequent interrupt cause related to reception, so there will be no need to perform unnecessary processing due to notification. As described above, in the present invention, the HDLCLSI is provided with a transmitting/receiving oven closing function that can be controlled from a program, so it is possible to prohibit (mask) notifications regarding transmission and reception for each transmission and reception of each line.

Although some programs have a masking function, they generally provide an interrupt level and can mask each level, but cannot mask each transmission/reception of each line within the same level. On the other hand, in the present invention, since it is possible to individually mask each line at the same level, the present invention is effective in such cases.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an example of a terminal device, FIG. 2 is a block diagram showing the configuration of HDLCLSI used in the line adapter of FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. 4A to 4F are time charts illustrating the mode of closing the transmission oven, and FIGS. 5A to 5E are time charts illustrating the mode of closing the reception oven.

Claims (1)

[Claims] 1. A data transmission system that is installed in a data transmission system consisting of a line adapter that is connected to a line and has a data register, and a processing unit connected to the line adapter, and that generates an interrupt related to transmission and reception to the processing unit. , a transmission/reception control circuit for transmitting and receiving data, a transmission interrupt control circuit for issuing a transmission interrupt to the processing section;
A reception interrupt control circuit for issuing a reception interrupt, and a transmission side interrupt mask and a reception side interrupt mask for allowing or prohibiting the transmission of an interrupt signal in the interrupt control circuit according to information given from the processing section. The transmission interrupt control circuit resets interrupt signals other than the interrupt signal indicating that the data register is empty when the transmission interrupt mask prohibits transmission of the interrupt signal, and also resets interrupt signals other than the interrupt signal indicating that the data register is empty. In response to an interrupt signal that indicates a problem, the reception interrupt control circuit gates the transmission of the interrupt signal to the processing unit while the mask prohibits the transmission of the interrupt signal. A transmission/reception control circuit is characterized in that when a reception interrupt mask prohibits transmission of an interrupt signal, the transmission of an interrupt signal to a processing section is prohibited by resetting the interrupt signal.