JPS5926061B2 - Erroneous output prevention circuit system for digital data distribution equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an erroneous output prevention circuit for a digital data distribution device.

Digital data distribution devices are actively used in programmable sequencers and the like.

An example of a programmable sequencer will be described. As shown in FIG. 1, the sequencer includes a data input device 1, a data output device 3, and a processor 2 that exchanges data between the input and output devices. A digital data distribution device is provided in the main part of the output device. This output device serially receives data from the processor and sequentially stores the data in a register based on the address sent from the processor at the same time. The data stored in this register is output based on the address sent from the processor. These tasks correspond to data distribution. On the other hand, as the amount of data processing increases, failure diagnosis is required. The program sequencer mentioned above is no exception. Particularly, since the output device performs the work of distributing data, trouble diagnosis is given special importance. Read data from the output device is sent to various operating devices. Therefore, if the output device malfunctions, malfunctioning operations will be commanded to various operating devices. From this point of view as well, failure diagnosis of output devices is important. An example of a failure diagnosis method for such an output device is shown below.
As shown in FIG. 2, the basics of fault diagnosis is to compare the input signal Si of the control device 4 with the output signal 50 using a comparator 5.
An abnormality signal Sa is output only when there is a mismatch.

Therefore, if a failure occurs in the equipment, the operator can check the abnormal signal and take appropriate measures. However, in recent years, equipment has become larger and more complex, and operators are increasingly required to have highly specialized knowledge.

On the other hand, from a social perspective, it is becoming increasingly difficult to secure highly specialized engineers. Against this background, there is a need to further develop devices with a failure diagnosis function, and to have the ability to issue an abnormality signal in the event of a failure and at the same time maintain the device in a certain fixed state. If this function is realized, it becomes possible to easily change the operation of the controlled object to the current state or to stop the operation in the event of a failure of the control device. The present invention was proposed from this viewpoint.

The subject of the present invention is primarily an output device in a programmable sequencer, but it can also be extended and applied to digital data distribution devices. The gist of the present invention is to connect the output section of the digital data distribution device to one signal DOOFF.
The circuit has a circuit configuration that can be turned off by a signal, and the abnormal signal output line of the device is connected to the DOOFF line, and when the device generates an abnormality, it outputs the abnormal signal to the outside and also turns the output to zero.
This is intended to be fixed to the FF.

The present invention will be explained in detail below with reference to the drawings. First, let's explain the output circuit of a programmable sequencer.

The configuration diagram of this output circuit is shown in FIG. 3.
A processor (not shown) sends an address ADDBs write command signal WSTB. Data DATA is sent. The decoder takes in the sent address ADDR at the timing of the write command signal WSTB and decodes it.

In the figure, address ADDRII consists of 3 bits,
The data is input bit by bit to the A, B, and C terminals of the parallel decoder 31 and decoded. The address decoded by the decoder 31 is input to the timing terminals T of the registers 32, 33, and 34 as write timing.
For example, in the case of 100F'' from ADD, it becomes the timing signal for register 3.On the other hand, each register 32, 33,
Data terminal D of 34 receives data DA from the processor.
TA is commonly applied. The data is taken in by a timing signal. Therefore, address ADDR
/)≦゛00bi, a capture command is input to the timing terminal of the register 33, and the data DATA reaching the data terminal at that time is written to the register 33. The data stored in the registers 32, 33, and 34 are sent to output circuits 38, 39, and 40, and the output is 0. ,01,07 to the controller. When reading data from each register, the data selector 37
will be utilized. This data selector 37 selects the address A
Upon receiving the DDR, each output 0 according to the contents of the address.
The corresponding output data among 0, 01, . . . 07 is outputted from terminal Y as data DIN. This data DI
N is input to the processor. The register 35 is a special register in which the same data as the register 33 is written when data is written in any one of the registers 32, 33, and 34, for example, the register 33. The data written in the register 35 becomes data 35a and is applied to the mismatch detection circuit 41. At the same time, the data in the register 3 is output as DIN via the output circuit 01 and the data selector 7, and is also applied to the mismatch detection circuit 41. If the output circuit is normal here, data 35a and data DIN match, so
The output data 41a of the mismatch detection circuit becomes logic "0". Data 41 is stored in the register 36 by the write signal WSTB.
The logic "O" of a is written, and the output signal of the register 36 is 0.
a becomes logic "0", that is, a normal signal. If the output circuit fails and the mismatch detection circuit input signal 35a and DIN become mismatched, the output signal 41a of the mismatch detection circuit 41 becomes logic "1", which is the register 36. is stored in the abnormal signal 0
Output a. FIG. 4 shows an embodiment of the present invention in which such an output circuit is provided with an erroneous output prevention circuit.

FIG. 5 is a detailed diagram of the DOOFF circuit and output circuit section.
The difference between this embodiment and FIG. 3 is that the DOOFF circuit 100
It is a part. The DOOFF circuit consists of an 0R gate 46, a switch circuit 47, and output circuits 38, 39...
- 40 has also been improved so that it can be turned off by the output of the switch circuit 47. When the output circuit is operating normally, the abnormal signal 0a is not output, that is, the logic of 0a is 10.
”.

Note that the input DOOFFEXT of the 0R gate 46 is designed to allow a signal to be applied from outside the output circuit, and when not used, the logic is "0". That is, the 0R circuit input signal 0a (5D00FFXT is the logic "0").゜゛, the output 46a also has a logic of 60゛, the switch circuit 47 becomes inoperative, and the output circuits 38, 39, 40 are not turned off.Let's examine this operation in Fig. 5.This circuit is an 0R gate. 51, resistor 52, transistor 53, relay driver 54, 55,...56, relay 57, 58
, . . . 59, and a power source 60. 0R gate 1
Inputs 0a, . 0 if D00FFEXT is logic 60''
The logic of the R output also becomes "O", and the base current 1B of the transistor 53 is supplied via the resistor 52.

This base current 1B causes collector current C to reach relay 57.
, 58, . . . , 59. Therefore, the output is 0. ，
0,...0m is 0N depending on the relay driver output
,0F. I will do F. Next, let's examine the operation in the case where the output circuit breaks down using FIG. 5.

If the output circuit fails, the abnormality signal 0a becomes logic 6r'', so the output of the 0R circuit 1 also becomes logic 1, blocking the inflow of the base current B of the transistor 53. Therefore, the collector current 1C also stops flowing.Relay 57, 58,
...59 can no longer maintain its operation and becomes FF (all 0), outputting 0. , 01...0n are also all set to 0FF.
As described above, when a failure occurs in the digital data distribution device, all outputs can be turned off by the malfunction output prevention circuit. By the way, the malfunction output blocking circuit is composed of a semiconductor, and the time required from receiving a malfunction signal to blocking output is several microseconds. Therefore, the fifth
Even if the relay driver 54 malfunctions in the output circuit shown in the figure and attempts to operate the relay 57,
Since the relay power is cut off in several microseconds, which is much shorter than the relay operating time of several milliseconds, the relay will not malfunction. In the conventional method, measures such as stopping are taken only after an erroneous output occurs, so in principle there is a period of time during which the erroneous operation continues. The erroneous output prevention circuit of the present invention is essentially different from conventional products in that it does not output erroneous output to the outside even if the output circuit fails. By the way, if a failure occurs in the output circuit and the output circuit is turned off, there will certainly be no erroneous output, but the question may arise as to whether the system being controlled can continue normal operation.

This allows normal operation for the following reasons. Generally, important operating ends are driven by two independent coils. If one coil is excited to turn on the operating end, the other coil is used for the purpose of turning off. Furthermore, these operating ends maintain an ON or OFF state when both coils are not excited. Therefore, this type of operating end will not malfunction unless it is excited. According to the example of the present invention, first, no erroneous output is generated. Second, turn the output to 0FF and do not excite the operating end. That is, the operating end maintains its current state without malfunctioning. As is clear from the above description, effects can be obtained by the present invention. (1) System reliability is greatly improved because erroneous output is not output even if the output device fails.

(2) Even if the output device fails, damage to the system can be greatly reduced.

(3) System countermeasures against output device failure are simplified and cost is reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a sequencer, Fig. 2 is a block diagram of a malfunction detection circuit, Fig. 3 is a circuit example of an output circuit, Fig. 4 is an implementation of the present invention, and Fig. 5 is a partial detailed diagram thereof. . 1...Input device, 2...Processor,
3... Output device, 51... 0R gate, 52... Resistor, 53... Transistor.

Claims (1)

[Claims] 1. In an erroneous output prevention circuit system for a digital data distribution device having a discrepancy detection circuit that detects an error by comparing the signal of the output circuit of a programmable sequencer with the same input signal, the output line of the distribution device is It is connected to one terminal of a certain electromagnetic relay via a current buffer, and the remaining terminals of the relay are connected to a power source for driving the relay via a transistor, and the signal from the mismatch detection circuit is connected to the transistor. An erroneous output prevention circuit system for a digital data distribution device characterized in that the power applied to the relay is cut off by turning off the transistor by applying the power to the base through a resistor. .