JPS5926124B2 - phase synchronized circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked circuit, and more particularly to a phase-locked circuit including a sampling circuit.

A conventional phase locked circuit including a sampling circuit includes a variable frequency oscillator, a phase comparator that detects the phase difference between the input signal and the output signal of the variable frequency oscillator, and a sampling circuit that samples the output of the phase comparator at a fixed period. circuit and
The variable frequency oscillator is coupled with a hold circuit connected to the sampling circuit and holding the output voltage of the sampling circuit in order to supply a control signal to the variable frequency oscillator.

However, in this circuit, if the sampling period of the sampling circuit is set short, the time (hereinafter referred to as pull-in time) until the synchronization system is captured by the reference input signal (hereinafter referred to as reference signal) becomes shorter.
Although the control speed becomes faster, the jitter of the synchronization system increases due to the increase in the noise band.

Therefore, it is effective against noise superimposed or mixed into the reference signal, unnecessary interference waves, and noise generated within the synchronization system.
It has the same drawbacks as for signals.

On the other hand, if the sampling period is set long, the effects of noise and jitter can be suppressed, but the disadvantage is that the acquisition time becomes longer and the synchronization acquisition range becomes narrower.

Therefore, in a conventional phase-locked circuit configured using a sampling circuit with a fixed sampling period, it is possible to combine the wide pull-in range and quick response characteristics obtained by a sampling circuit with a short sampling period with the long sampling period. However, it is not possible to satisfy both the strong noise removal characteristics obtained with the sampling circuit of 1, and there is a drawback that the sampling period must be set at a compromise between the two as necessary.

An object of the present invention is to monitor the synchronization state and change the sampling period of the sampling circuit according to the synchronization state of the synchronization system, thereby reducing the synchronization pull-in range and deteriorating the control characteristics and response characteristics. The object of the present invention is to provide a phase synchronized circuit with good noise removal characteristics.

According to the present invention, a variable frequency oscillator, a phase comparator that detects a phase difference between an input signal and an output signal of the variable frequency oscillator, a sampling circuit that samples the output of the phase comparator, and a A phase-locked circuit comprising a hold circuit connected to the sampling circuit for supplying a control signal and holding the output voltage of the sampling circuit, which monitors the synchronization state of the phase-locked circuit; A phase-locked circuit characterized in that the sampling period of the sampling circuit is controlled based on the result is obtained.

The present invention will be explained in more detail below with reference to the drawings.

FIG. 1 is a principle diagram of a conventional phase synchronization circuit, in which 1 is a reference signal input terminal, 2 is a phase comparator, and 3 is a comparison signal (output signal of a voltage controlled oscillator).

) input terminal, 4 is a voltage controlled oscillator, 5 is a sampling circuit, and 6 is a hold circuit.

When the reference signal is applied to the reference signal input terminal 1, the phase comparator 2 detects the phase difference with the output signal of the voltage controlled oscillator 4 applied to the comparison signal input terminal 3, and generates an error signal according to the phase difference. It is supplied to the sampling circuit 5.

This error signal is periodically sampled by the sampling circuit 5, becomes a pulse train of instantaneous values (sample value signal), and is sent to the hold circuit 6. Due to the instantaneous value holding action of the hold circuit 6, it becomes a continuous signal. Voltage controlled oscillator 4 so that the phase of the comparison signal matches the phase of the reference signal.
control.

In this case, since the sampling period of the sampling circuit is fixed, it is not possible to have both strong noise removal characteristics and quick response characteristics.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which the sampling circuit 5 in the circuit of FIG. 1 is replaced with a sampling period variable sampling circuit 5', and a synchronization monitor 7
, a controller 8 is provided.

FIG. 6 a = f and FIG. 7 a - f show the waveforms of each part of the embodiment of FIG. 2, and FIG. Figure 7 a-f
indicates a synchronous state.

Note that the time T in FIG. 7 is shown shorter than that in FIG. 6.

When the synchronization system is out of synchronization, the phase comparator 2 compares and detects the phase difference between the reference signal shown in FIG. 6a and the output of the voltage controlled oscillator 4 shown in FIG.

When the output of the phase comparator 2 changes at a fast speed as shown in FIG. 6C, the synchronous monitor 7 operates and sends an alarm signal to the controller 8. By shortening the period as shown in FIG. 6d, the response speed of the yarn is increased and the phases of the reference signal and comparison signal quickly match.

When the synchronous system reaches a synchronous state, that is, a state in which the frequencies of the reference signal (Fig. 7a) and the output of the voltage controlled oscillator 4 (Fig. 7b) match, the output of the phase comparator 2 (Fig. 7C) There is no change, the synchronization monitor 7 stops operating, and the controller 8.
In order to stop the alarm signal, the sampling period of the variable sampling circuit 5' is lengthened by the controller 8 as shown in FIG. 7d.

In the synchronized state, the frequency of the voltage controlled oscillator 4 is kept constant, so the output signal after sampling (Fig. 7 e) also remains constant, and the output signal after integration by the hold circuit 6 (
Since there is almost no change in FIG. 7f), the operation of the loop itself is not affected whether the sampling period is lengthened or shortened.

Therefore, in the synchronous state, by lengthening the sampling period, the response speed to disturbances is reduced without affecting the operation of the phase-locked loop, resulting in strong noise removal characteristics.

FIG. 3 shows a specific circuit of FIG. 2.

The synchronization monitor 7 is a commonly used AM detector, and supplies a ground potential to the controller 8 when the error signal of the phase comparator 2 fluctuates due to loss of synchronization, and supplies a positive voltage to the controller 8 in a synchronized state.

The controller 8 is composed of resistors R1 and R2, a capacitor C1 and a diode D1.

When the ground potential is supplied to the controller 8, the diode D1 becomes conductive, the charge on the capacitor C1 is immediately discharged, the voltage controlled multi-vibration break (VCM) 9 is supplied with the ground potential, and the frequency immediately increases.

Conversely, when a positive voltage is supplied to the controller 8, the diode D1 is cut off, and the capacitor C1 is charged positively through the resistor R1 according to the time constant determined by the capacitor C1 and the resistor R2, and the frequency of the VCM9 is Gradually decreases.

The output pulse of the VCM 9 is converted into a narrow pulse by a waveform shaper 10.

, this waveform shaper 10 includes a NAND, AN circuit, and a resistor R.
3 and a capacitor C2.

The output of this waveform shaper 10 is applied to an analog switch 11, and the analog gate 11 conducts only while this pulse is applied, and sends it to the output signal hold circuit (capacitor C3) 6 of the phase comparator 2.

The voltage controlled oscillator 4 is controlled by the output of the hold circuit 6.

The synchronization monitor 7 may be a phase comparator that compares the phase of the output signal of the voltage controlled oscillator 4 and the signal of the input terminal 1.

In this case, the controller 8 may be omitted. Note that the frequency of the VCM 9 becomes high when synchronization is lost, as described above.

In other words, the sampling period becomes shorter.

Therefore, in order to shorten the synchronization pull-in time, it is preferable to make this sampling period shorter than the period of the input signal.

Further, in the synchronous state, the output frequency of the VCM 9, that is, the sampling period is selected so as to maintain the loop stably even in the presence of disturbances such as noise, and is generally selected to be considerably longer than the period of the input signal.

FIG. 4 is a block diagram of another embodiment, in which a sampling period variable sampling circuit 5'/ also serves as a phase comparator, and a waveform shaper 12 (this may be omitted). It is equipped with

The reference signal is first converted into a triangular wave, a sawtooth wave, or a rectangular wave by the waveform shaper 12 and applied to the variable sampling period sampling circuit 5''. The output signal of is sampled at the frequency of the divided signal.

The sampling period is controlled by changing the division ratio, and the control method is the same as in the previous embodiment.

FIG. 5 is a specific example of FIG. 4.

The waveform converter 12 is a commonly used integrator, bootstrap circuit, etc. (can also be omitted), and the reference signal is
Here, it is converted into a triangular wave, a sawtooth state, or a square wave, and applied to the analog switch 11.

The ground level voltage from the synchronization monitor 7 is connected to the diode D.
When added to the cathode side of 2, diode D2 conducts, immediately bringing the clear terminals of FF(1) to FF(N) to ground level, and passing the undivided signal through the OR(1) to 0R(N) circuit. is output, which is converted into a narrow width pulse by the circuit of the waveform shaper 10 and applied to the gate terminal of the analog switch 11.
When a more positive voltage is applied to the cathode of diode D2, diode D2 is cut off and resistor R is applied through resistor R4.
5. Capacitor C3 is charged according to the time constant determined by capacitor C3, but the flip-flop FF (
Since the time constants of 1) to FF(N) are set slightly different from each other, the frequency division operations do not start at the same time, the frequency division ratio gradually increases, and the output frequency also gradually decreases.

As explained above, when matching the phase of the comparison signal with the reference signal that contains noise and unnecessary interference waves, it is possible to match the phase of the comparison signal with the reference signal that contains noise and unnecessary interference waves without reducing the pull-in range or deteriorating the pull-in speed response characteristics. As an example, in the carrier suppression single sideband method, phase synchronization is generally applied to the slave local oscillator using a synchronization pilot sent from the master station. In this case, two conditions are required: to respond as quickly as possible to changes in the state of the incoming pilot signal, and to minimize the influence of noise and disturbances normally included in the pilot signal. According to the synchronization method, both of these conditions can be satisfied and more stable communication can be ensured.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional circuit, Fig. 2 is a block diagram of the original circuit, Fig. 3 is a specific example of Fig. 2, Fig. 4 is another embodiment of the present invention, and Fig. 5 is a block diagram of a conventional circuit. Specific example of Figure 4. Figures 6a-f are time charts of waveforms of various parts to explain the operation of the circuit in Figure 2 in an asynchronous state, and Figures 7a-f are diagrams showing the operation of the circuit in Figure 2 in a synchronous state. FIG. 3 is a time chart diagram of waveforms of various parts for explaining the following. 1.1', 1'"...Reference signal input terminal, 2.
... Phase comparator, 3 ... Comparison signal input terminal, 4 ... Voltage controlled oscillator, 5 , 5', 5
”...Sampling circuit, 6...Hold circuit, 7...Synchronization monitor, 8...
- Controller, 9... Voltage control multi-by-break, 10... Waveform shaper, 11... Analog switch, 12... Waveform shaper.

Claims (1)

[Claims] 1. A variable frequency oscillator, a phase comparator that detects a phase difference between an input signal and an output signal of the variable frequency oscillator, a sampling circuit that samples the output of the phase comparator, and a control signal that is supplied to the variable frequency oscillator. a hold circuit connected to the sampling circuit and holding the output voltage of the sampling circuit in order to hold the output voltage of the sampling circuit; and second means for varying the sampling period of the sampling circuit in response to the output of the first means.