JPS5927544B2 - Facsimile signal decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile signal decoding device, and particularly to a decoding device for an encoding method used for efficiently transmitting or storing binary signals such as black and white binary facsimile signals. be.

Conventionally, as a method for encoding binary facsimile signals, (
1) A run-length encoding method in which the signals obtained by scanning are converted into time series, and then sequentially and alternately encodes and transmits the sizes of continuous lengths (run lengths) of white and black, and (2) multiple methods. For example, a method has been proposed in which signals of two scanning lines are encoded all at once.

However, the method (1) has low compression efficiency because it does not utilize the property that the facsimile signal has a strong correlation in the direction perpendicular to the scanning line direction (vertical). In addition, method (2) uses vertical correlation for signals of several scanning lines that are encoded at once, but does not use correlation with other scanning line signals. Although the compression effect was greater than that of method (1), a sufficient compression effect was still not obtained. The present invention eliminates these drawbacks of the conventional method, eliminates redundancy in facsimile signals with a relatively small amount of memory and simple circuits, and significantly compresses the amount of codes to be transmitted, that is, the number of bits. The present invention provides a decoding device using a two-dimensional sequential encoding method.

The principle of the first encoding method used in the present invention is that an information changing pixel (hereinafter simply referred to as a changing pixel) having a binary signal value different from the immediately preceding pixel in a facsimile signal
To sequentially encode information indicating the position of (hereinafter referred to as address), the same scanning line (
The relative number of pixels from one changed pixel selected from nearby changed pixels on the scanning line immediately before the encoding line (hereinafter referred to as the encoding line) or on the scanning line immediately before the encoding line (hereinafter referred to as the reference line).
(hereinafter referred to as length).

1, 2, and 3 are diagrams showing examples of facsimile signals, in which small frames without hatching indicate white pixels, . . . small frames with hatching indicate black pixels.

First, the encoding starting pixel A. and other change pixels are defined as follows. AO: Starting pixel on the encoding line that is the starting point for encoding, al: A on the encoding line.

Next change pixel, B,: A on the reference line. occurs after the pixel immediately above A, and A. The first changed pixel having a binary signal value different from B2: the next changed pixel of bl on the reference line, the encoding procedure sequentially changes the pixels on the encoding line and the reference line as shown below. They are compared, and changed pixels on both scanning lines are sequentially detected and encoded.

(Step 1) When two changed pixels B, , b2 on the reference line are detected before the changed pixel al on the encoding line (second
), this state is set as pass mode, B1 and b2 are encoded with pass mode code, and B is used as the starting pixel for the next encoding.

Pixel A on the encoding line immediately below. ′. (Step 2) If the changed pixel al is detected on the encoding line before B2 among the two changed pixels Bl and b2 on the reference line (see FIGS. 3A and B), the changed pixels A and bl Proceed to scan the pixels until the distance A occurs.

The number of bits [AOa,] obtained by encoding al in the horizontal mode and adding the mode code to it is determined. At the same time distance Bl
a, is encoded as a vertical mode, and the number of bits [Blal]
seek. The numbers of encoded bits are compared, and one of the encoding modes is selected and adopted under the following conditions.

When this condition is met, it is determined that the correlation between the encoded pixel al and the reference pixel bl is strong, and the distance B is determined in the vertical mode.
la, is selected and adopted, and a new starting pixel is moved to the position al. When this condition is satisfied, the encoding change pixel A and the starting pixel A.

It was determined that there was a strong correlation with the horizontal mode code, and distance A was added following the horizontal mode code. al is encoded, and a new starting pixel is moved to the position of al. Table 1 shows an example of a code table used in this encoding method.

This code table uses MH codes (Modified Huffman codes, see CCITT Recommendation T.4 for details) and bit-by-bit codes D(n) as examples.
It goes without saying that the present invention is not limited to the use of such codes, and that general variable length codes can be used. In addition, in the code column of vertical mode in Table 1, the code "'1"' means that if A, is detected before bl, the code "''
+''' indicates that al is detected after bl.In the above explanation, expressions (a) and (b) were given as conditions for separating horizontal mode and vertical mode, but other conditional expressions It is also possible to separate them, for example.

Furthermore, in step 1, pixel A.

The changed pixel directly above a1 is not considered as Bl or b2, but is pixel A. or a change directly above pixel a1 is included in the encoding target pixel Blb2, or it is not considered as pixel Bl, b2 unless it is more than n (n is O or a positive integer) pixels away from pixel AO, al. conditions can be changed. As explained above, the addresses of encoded changed pixels are sequentially encoded, but the addresses are relative to one changed pixel selected from changed pixels already encoded on the encoding line or reference line. Encoded using distance.

Decoding is performed by the inverse operation of encoding.

That is, when decoding a new encoded line, the line decoded immediately before is used as a reference line, and the starting pixel A is used. For example, the value is set to the first pixel and the value is set as the white pixel. The decoder then sequentially decodes the received encoded signals and identifies whether the initial mode is horizontal mode, vertical mode, or pass mode. If the horizontal mode is identified, the encoded signal is further decoded to obtain the distance A. Decode the value of al and select the starting pixel A on the encoded line. A from position. The starting pixel A is used to reproduce the changed pixel a1 at a position separated by al. The pixels from to just before the changed pixel a1 are reproduced at the same pixel level as the starting pixel. Then set the position of the starting pixel to A. to the position a1, and set the level of the new starting pixel a1 to A. is played to the opposite level. If the vertical mode is identified and the absolute value of the distance Blal is other than O or 1, the encoded signal is further decoded to encode the value of the distance Blal.

In the case of vertical mode, the position of the changed pixel b1 is detected on the reference line, and if the distance B, al is 0, the pixel a1 is reproduced directly below the changed pixel b1, and if the polarity of the distance Blal is ゛-゛, from the change pixel b1 to the starting pixel A. B in the direction of
Regenerate pixel a1 on the encoding line separated by lal,
If the polarity of the distance Blal is +11, the changed pixel b1
From the starting pixel A. Pixel a1 is reproduced on a coding line separated by Bla in the opposite direction. Starting pixel A. The level of the pixels immediately before pixel a1 is the starting pixel A. The pixel a1 is the starting pixel A. is played at the opposite level. After that, the position of the starting pixel is A. Move from to a1. If the pass mode is identified, two change pixels Bl on the reference line
, b2 is detected, and the position of the starting pixel is A. B2 from the position of
Move to the position directly below. Furthermore, pixel A. The pixels on the encoding line up to the pixel immediately below pixel B2 are pixel A. is reproduced at the same pixel level. A first embodiment of the decoding device according to the present invention is shown in FIG.

The encoded signal from the human input terminal 201 is temporarily stored in the input buffer memory 202. Mode code identification circuit 2
03 has the configuration shown in FIG. 5, and its operation is to read the signal (at most 4 bits as shown in Table 1) necessary for mode identification from the input buffer memory 202, and to select the pass mode, horizontal mode, or vertical mode. Identify which one it is. If the signal is 1111100, it is determined that the mode is pass mode, and the output of the P line is set to ``1''. The signal is T! 111
If it is 11, it is identified as horizontal mode, and the output of the h line is set to ``1''.
shall be. Also, the signal is ゛O-11100- 1?1100
T! If so, the polarity of Blal in vertical mode is 11+
”1, and the output of the V+ line is set to 1115.
If the signal is "101" or 1110111, it is determined that the polarity of Bla in the vertical mode is "1", and the output of the V line is set to "11".The address control circuit 221
The configuration is shown in the figure, and the outputs of the mode code identification circuit, P, . When V- and V+ become 111, A is added from SaO. A pulse is applied to the memory 211 to shift the memory one bit at a time from the address. Identification circuit 2
When the P line of 03 becomes 1111 (pass mode), the address control circuit 221 sequentially shifts the reference line memory 211 from the address of -AO and starts detecting Blb2.

Note that information on the previous line is stored in advance in the reference line memory via the encoding line memory 212. The changed pixel detection circuit 240 outputs 1 every time there is a pixel different from the previous pixel in the signal series added from the line memory 211.
1 "7 is output. When the output "11" of the changed pixel detection circuit 240 is output, the changed pixel is A. If the pixel has a polarity different from
1 detection circuit 251 (AND circuit), and the output of the BIP line becomes Tlll. The AObl counter 272 receives pulses from the address control circuit 221 and counts the number of pulses from the AO address to b1 (BlP line is 11F1). After b1 is detected, the B2 detection circuit 252 detects (B
When the lp line is ゜”1゛7) and a changed pixel is detected by the changed pixel detection circuit 240, the output of the B2P line is set to ゜”1゛7).
It consists of a flip-flop and an AND circuit. The AOb2 counter 271 receives a pulse from the address control circuit 221 and counts from the AO address to B2 (
B2p line is ゛11! Count the number of pulse lines. AOb2
Information in the counter 271 is added to the AO register 300 via a gate 281 (opened when the p line of the mode code identification circuit 203 becomes !1111).
The information in the AO register 300 is transmitted to the address control circuit 221.
and 222, and a new A. Set the address and
The decoding operation is resumed. When the v+ line or V line of the identification circuit 203 becomes ``11'' (vertical mode), the output ``1'' of the OR circuit 291 is connected to the address control circuit 221 and Bl.
It is added to the al decoding circuit 231.

As a result, the above-mentioned decoding regarding b1 is executed, and AO
The count of the bl counter 272 is A of b1. This indicates the address for . Also, Blal decoding circuit 2
31 reads one word worth of signals from the input buffer memory 202 and decodes them. This decoded value is sent to the adder 26
A by 1. A is added to the value of the bl counter 272 and is also added to the value of the bl counter 272 by the subtracter 262. The value of the bl counter 272 is subtracted from the value of the bl counter 272. The output V+ line of the mode code identification circuit 203 is 1
? In the case of "1", the gate 284 opens, and the information in the adder 261 is applied to the address control circuit 222 via the OR circuit 292, and the A. register 3 via the gate 282.
Also added to 00. On the other hand, when the output V line of the mode code identification circuit 203 is "1", the gate 285 is opened and the subtracter 2
The information of 62 is applied to the address control circuit 222 via the OR circuit 292, and the information of A. It is also added to the register 300 of. The address control circuit 222 has the configuration shown in FIG. 7, and confirms the address of a1 based on the information transmitted via the OR circuit 292, and checks the address of A1 on the encoded line memory.

All information from to just before a1 is A. and a1
The information is A. Invert the information. The information in the AO register 300 is transmitted to the address control circuits 221 and 222.
A new member joins A. Set the address and resume decoding. When the h line of the mode code identification circuit 203 is ``1'' (horizontal mode), the AOal decoding circuit 23
2 reads one word worth of signals from the input buffer memory 202 and decodes them.

The decoded values are sent to A through the address control circuit 222 and gate 283, respectively. It is added to the register 300. The address control circuit 222 determines the address of a1 and stores A on the encoding line memory. All A's from to just before a1.
, and invert a1. AO register 30
0 is rewritten to the address of a1, A, the address is new A. It becomes the address. The scarce new information is applied to address control circuits 221 and 222. Set the address and resume decoding. In the decoding circuit described above, the conditions for setting the detection circuit, register, counter, etc. are not described nor shown in the diagram, but among these circuits, the mode code identification circuit 203 and the b1 detection circuit are 25
2. Address control circuits 221, 222, counter 271
, 272, decoding circuits 231, 232, etc. are reset each time an AO address is newly set.

Also, the end of one line is A. This is done by monitoring the address, and when the AO address becomes the address of the end pixel of one line, the decoding is completed and the decoding of the subsequent line is restarted. In the above encoding method, when the horizontal mode is identified, the distance between the starting pixel and the encoding change point a1 is encoded, and a code indicating the horizontal mode is added, but in order to further improve the compression efficiency, In addition, when the horizontal mode is identified, it is considered that the subsequent changed pixel (hereinafter referred to as A2) is also encoded. In this case, since two changed pixels Al and a2 are encoded together in one horizontal mode, the horizontal mode code amount per one changed pixel is reduced, and compression efficiency is increased. Note that in this method, the position of the changed pixel A2 is encoded by the distance Ala2. Table 2 shows an example of a code table used in this encoding. A second embodiment of the decoding device according to the present invention is shown in FIG.

The encoded signal from the input terminal 201 is temporarily stored in the input buffer memory 202.

The mode code identification circuit 203 has the configuration shown in FIG. 5, and its operation is to read out the signals (at most 4 bits as shown in Table 1) necessary for mode identification from the input buffer memory 202, and select the pass mode, horizontal mode, or vertical mode. The signal is 111101?
If so, it is determined that it is pass mode, and the output of the p line is set to 1V "1. If the signal is 1111111, it is identified as horizontal mode, and the output of the h line is set to 1111. Also, the output of the h line is set to 1111.
, 11100-Q7llOOll, it is determined that the polarity of Blaal in the vertical mode is 1+'', and the output of the V+ line is set to 1111.The signal is 1101]1 or 111
If it is 1011T, it is determined that the polarity of Bal in the vertical mode is 11-11, and the output of the V line is set to 1-11. The address control circuit 221 has the configuration shown in FIG. 6, and includes the output of the mode code identification circuit, the P. When V1v+ becomes Tllll, A is added from SaO. A pulse is applied to the memory 211 to shift the memory one bit at a time from the address. The P line of the identification circuit 203 is “1”
When it becomes (pass mode), the address control circuit 221
is A.

The reference line memory 211 is sequentially shifted from the address , and detection of Blb2 is started. Note that information on the previous line is stored in advance in the reference line memory via the encoding line memory 212. The changed pixel detection circuit 240 outputs an output 11'1 every time there is a pixel different from the immediately previous pixel in the signal series added from the line memory 211.

When the changed pixel detection circuit 240 outputs “1°”, the changed pixel is a pixel with a polarity different from A. EXOR.
The output “1;” is sent to the b1 detection circuit 2 through the circuit 293.
51 (AND circuit), Bl, line output 1; "1
becomes. AObl counter 272 is address control circuit 2
Receives a pulse from 21, and from the AO address to b1 (B
, the number of pulses when the p line is 11 "1" is counted.The B2 detection circuit 252 counts the number of pulses when the p line is 11 "1". After b1 is detected (the Blp line is 11 f"), the B2 detection circuit 252
Furthermore, when a changed pixel is detected by the changed pixel detection circuit 240, the output of the B2P line is set to 71FV, and is composed of a flip-flop and an AND circuit. The AOb2 counter 271 receives a pulse from the address control circuit 221,
From the AO address to B2 (the B2p line counts the number of pulses that are "1").The address control circuit 221 temporarily stops sending out shift pulses from the "1" on the 2P line.A
The information of the Ob2 counter 271 is added to the A. register 300 via the gate 281 (opened when the p line of the mode code identification circuit 203 becomes 1"1").
The information in the AO register 300 is added to the address control circuits 221 and 222, and a new A. The address is set and the decoding operation is resumed. When the v+ line or the v-line of the identification circuit 203 becomes 11111 (vertical mode), the output of the OR circuit 291 is 1111! is the address control circuit 221
and is added to the Bral decoding circuit 231.

As a result, the above-mentioned decoding regarding b1 is executed, and AO
The count of the bl counter 272 is A of b1. This indicates the address for . Also, Blal decoding circuit 2
31 reads one word worth of signals from the input buffer memory 202 and decodes them. This decoded value is sent to the adder 26
A by 1. A is added to the value of the bl counter 272 and is also added to the value of the bl counter 272 by the subtracter 262. The value of the bl counter 272 is subtracted from the value of the bl counter 272. The output V+ line of the mode code identification circuit 203 is “
When the value is 1, the gate 284 is opened, and the information in the adder 261 is applied to the address control circuit 222 via the OR circuit 292 and the information is applied to the address control circuit 222 via the gate 282. register 300
Also join. On the other hand, when the output v of the mode code identification circuit 203 is 111, the gate 285 opens and the subtracter 262
The information is sent to the address control circuit 22 via the OR circuit 292.
2 and through gate 282. It is also added to the register 300 of. The address control circuit 222 determines the address of a1 based on the information transmitted via the OR circuit 292, and determines the address of A1 on the encoded line memory. All information from to just before a1 is A. and the information of a1 is A. Invert the information. The information in the AO register 300 is added to the address control circuits 221 and 222, and a new A.
Set the address and resume decoding. When the h line of the mode code identification circuit 203 becomes 11V1 (horizontal mode), the AOal decoding circuit 232 and the Ala2 decoding circuit 233 sequentially read two words worth of signals from the input buffer memory 202 and read the first one word. A.

The al decoding circuit 232 decodes the remaining one word as Ala
2 decoding circuit 233 decodes. The decoded value is applied to address control circuit 222 and gate 28
3 or A via gate 286. It is also added to the register 300. The address control circuit 222 determines the address of Al, a2, and A on the encoding line memory. All A's from to just before a1. After assuming the same information as and inverting a1,
All information from a1 to just before A2 is the same as A, and A2
is inverted with respect to A. The AO register 300 is A,
, a2 addresses one after another, and the A2 address becomes the new AO address. This new information is added to the address support circuits 221 and 222. Set the address and resume decoding. In the decoding circuit described above, the conditions for setting the detection circuit, register, counter, etc. are not described nor shown in the diagram, but among these circuits, the mode code identification circuit 203, B2 detection circuit 252,
Address control circuits 221, 222, counters 271, 2
72, decoding circuits 231 to 233, etc. are reset each time an AO address is newly set.

Further, the end of one line is performed by monitoring the AO address by the address control circuit 222, and when the AO address becomes the address of the end pixel of one line, decoding is ended and decoding of the subsequent line is restarted. Next, a method for limiting the deterioration of the image quality of the reproduced screen due to code errors, which is another object of the present invention, will be described.

In the encoding method used in the present invention, in order to encode the image signal of the encoded line, the image signal information of the reference line immediately before this encoded line is used to encode the encoded line. There is. Therefore, also on the decoder side,
The image signal information of the reference line that has already been decoded is used to decode the image signal of the encoded line. In this way, since code decoding is performed while sequentially using the image signal information of the immediately preceding scanning line, code errors may occur due to the influence of line noise, etc., and if the image signal of a certain line is not reproduced correctly. Re-signals of lines subsequent to the line may not be reproduced correctly, and the image quality of the reproduced screen may deteriorate significantly. Therefore, it is necessary to detect the occurrence of a code error, suppress the deterioration of the image quality of the line where the code error has occurred, and promptly recover from the code error state so that the deterioration of image quality due to the code error does not spread beyond the line where the deterioration of the image quality occurred. become. According to the present invention, for these purposes, the encoder side generates a so-called self-synchronized first signal that can be detected from any location in the code sequence.
A control code is inserted in a predetermined section of the image signal, for example, immediately before the start of encoding on the first f)7f6.1 line of every 4 lines (K-4), and the corresponding . /I6. For the l line, without using the image signal information of the previous line,
/F6. The image signal information of the 1 line is encoded (for example, run-length RL encoding), and the black 2, rot 3, etc. immediately after the F and 1 lines are encoded according to the present invention. A second control code different from the first control code for code error detection is inserted every time the coding of each line is completed. On the decoder side, the self-synchronized first
When a control code is detected, the RL for the immediately following code sequence is
/F6. without using the information of the previous line as encoded. Decoding is performed as one line.

When the second control code is detected, it is assumed that encoding according to the present invention has been performed, and decoding is performed using the immediately preceding line information. Immediately after each line is decoded, the presence or absence of the first or second control code is checked and error retrieval is performed. If an error is detected, processing such as replacing the erroneously decoded line with the image signal of the immediately previous scanning line is performed to suppress deterioration in image quality. When an error is detected, the decoding operation is temporarily stopped, but
As soon as the self-synchronous first control code is detected, R
Restart decoding of L and recover from the error state. FIG. 9 is a block diagram of a decoding apparatus according to a third embodiment of the present invention. In the decoding device, when the first control code detection circuit 106 detects the first control code, the encoded line is encoded without referring to reference line information thereafter.

For example, the RL decoder 107 that decodes a run-length (RL) code decodes the RL for one line (one black line), writes reproduced pixel information to the line memory 108, and when the decoding of one black line is completed, the line memory 108
Transfer the contents to Line Memo 1 River 09. Thereafter, using the contents of the line memory 109, the decoder 110 according to the present invention sequentially decodes the black 2, black 3, . . . black K lines. Note that each time the decoding of each line is completed, the control code is detected by control code detection circuits 106 and 111, and the code error detection circuit 112 detects whether or not a code error has occurred. Once a code error occurs, JI from that scanning line onward)
．． No decoding is performed up to K scanning lines. After that, when the first control code is detected, the normal decoding operation is started and the code error state is recovered. In addition, if the first to fifteenth circuits referred to in the present invention are associated with the reference numerals of the embodiments of the present invention in the above, they may be considered as follows.

That is, the first circuit...encoding line memory 2
12 Second circuit...Reference line memory 211
Third circuit...address control circuit 222 Fourth circuit...address control circuit 221 Fifth circuit...
...AO memory 213 6th circuit ...Mode code identification circuit 203 7th circuit ...B1 detection circuit 251 8th circuit ...B2 detection circuit 25
2 Ninth circuit...Blal decoding circuit 231 Tenth circuit...AOal decoding circuit 232 first
1 circuit...First control code detection circuit 106 first
2 circuit...Second control code detection circuit 111 first
3 circuit...RL decoder 107 14th circuit...
... Code error detection circuit 112 15th circuit ...
... It may be considered that the Ala2 decoding circuit 233 corresponds to each.

As explained above, the present invention enables highly efficient encoding of signals with extremely strong correlation between adjacent lines, such as black-and-white binary facsimile signals, by using the distance from the neighboring change pixels, and As shown at the beginning of writing, in parts where there is no correlation with the line immediately above, the distance from the same line is used for encoding.By appropriately selecting two types of encoding methods, highly efficient encoding is possible regardless of the degree of correlation. It has the advantage of making it possible.

Further, for example, after inserting a self-synchronous first control code every K scanning lines, RL encoding is performed for only one scanning line, and
Subsequent scanning lines are encoded according to the present invention, and by checking for code errors each time the encoding of one scanning line is completed, it is possible to prevent image quality deterioration due to code errors from spreading and to quickly recover from a code error state. It has the advantage of being possible.

[Brief explanation of drawings]

1, 2, and 3A and 3B are facsimile signal example diagrams for explaining the encoding method of the present invention, and FIG. 4 is a program diagram showing a first embodiment of the decoding device according to the present invention. 5 to 7 are block diagrams showing specific examples of circuits used in the decoding device of FIG. 4, and FIG. 8 is a block diagram showing a second embodiment of the decoding device according to the present invention. FIG. 9 is a block diagram showing a third embodiment of the decoding apparatus according to the present invention.

Claims (1)

[Claims] 1. In an apparatus that sequentially samples signals obtained by scanning an original image into pixels and decodes a signal in which the positions of information changing pixels included in the sampled binary facsimile signal are encoded, A first circuit that stores line information to be decoded, a second circuit that stores reference line information that has been decoded immediately before, and a third circuit that controls the address of the first circuit.
a fourth circuit that controls the address of the second circuit; a fifth circuit that sets a starting pixel that is the starting point of decoding on the line to be decoded; 2
, or a sixth circuit that identifies the presence or absence of the third three types of mode codes, and a first information change pixel located after the pixel directly above the starting pixel on the reference line and having a signal value different from that of the starting pixel. A seventh circuit that detects the first reference pixel, an eighth circuit that detects a second reference pixel that is an information change pixel next to the first reference pixel on the reference line, and a second mode code are identified. a ninth circuit that decodes a code indicating the relative distance between the first reference pixel and the information change pixel next to the starting pixel on the decoding line when the third mode code is identified; The first step is to decode a code indicating the distance from the starting pixel to the information change pixel located next to the starting pixel on the decoding line.
1. A facsimile signal decoding device characterized by comprising a circuit of 0. 2. In a device that sequentially samples a signal obtained by scanning an original image into pixels and decodes a signal obtained by encoding the position of an information changing pixel included in the sampled binary facsimile signal, the line information to be decoded from now on is decoded. a first circuit for storing reference line information, a second circuit for storing reference line information that has just finished decoding, and a third circuit for controlling the address of the first circuit.
a fourth circuit that controls the address of the second circuit; a fifth circuit that sets a starting pixel that is the starting point of decoding on the line to be decoded; 2
, or a sixth circuit that identifies the presence or absence of the third three types of mode codes, and a first information change pixel located after the pixel directly above the starting pixel on the reference line and having a signal value different from that of the starting pixel. A seventh circuit that detects the first reference pixel, an eighth circuit that detects a second reference pixel that is an information change pixel next to the first reference pixel on the reference line, and a second mode code are identified. a ninth circuit that decodes a code indicating the relative distance between the first reference pixel and the information change pixel next to the starting pixel on the decoding line when the third mode code is identified; The first step is to decode a code indicating the distance from the starting pixel to the information change pixel located next to the starting pixel on the decoding line.
0 circuit, and an eleventh circuit that detects the first control signal from the encoded signal sequence, and a second circuit that detects the first control signal from the encoded signal sequence.
a 12th circuit that detects a control signal of the encoded line; a 13th circuit that decodes a signal obtained by encoding the encoded line without referring to reference line information; and a 14th circuit that detects the presence or absence of a code error. A facsimile signal decoding device characterized by comprising: 3. In a device that sequentially samples a signal obtained by scanning an original image into pixels and decodes a signal obtained by encoding the position of an information changing pixel contained in the sampled binary facsimile signal, the line information to be decoded from now on is decoded. a first circuit for storing reference line information, a second circuit for storing reference line information that has just finished decoding, and a third circuit for controlling the address of the first circuit.
a fourth circuit that controls the address of the second circuit; a fifth circuit that sets a starting pixel that is the starting point of decoding on the line to be decoded; 2
, or a sixth circuit that identifies the presence or absence of the third three types of mode codes, and a first information change pixel located after the pixel directly above the starting pixel on the reference line and having a signal value different from that of the starting pixel. A seventh circuit that detects the first reference pixel, an eighth circuit that detects a second reference pixel that is an information change pixel next to the first reference pixel on the reference line, and a second mode code are identified. a ninth circuit that decodes a code indicating the relative distance between the first reference pixel and the information change pixel next to the starting pixel on the decoding line when the third mode code is identified; The first step is to decode a code indicating the distance from the starting pixel to the information change pixel located next to the starting pixel on the decoding line.
0 circuit, and when the third mode code is identified, the first information change pixel located next to the starting pixel and the first information change pixel located next to the starting pixel on the decoding line 11. A facsimile signal decoding device comprising: a fifteenth circuit for decoding a code indicating a distance from the second information change pixel. 4. In a device that sequentially samples signals obtained by scanning an original picture into pixels and decodes a signal obtained by encoding the position of information changing pixels included in the sampled binary facsimile signal, the line information to be decoded from now on is decoded. a first circuit for storing reference line information, a second circuit for storing reference line information that has just finished decoding, and a third circuit for controlling the address of the first circuit.
a fourth circuit that controls the address of the second circuit; a fifth circuit that sets a starting pixel that is the starting point of decoding on the line to be decoded; 2
, or a sixth circuit that identifies the presence or absence of the third three types of mode codes, and a first information change pixel located after the pixel directly above the starting pixel on the reference line and having a signal value different from that of the starting pixel. A seventh circuit that detects the first reference pixel, an eighth circuit that detects a second reference pixel that is an information change pixel next to the first reference pixel on the reference line, and a second mode code are identified. a ninth circuit that decodes a code indicating the relative distance between the first reference pixel and the information change pixel next to the starting pixel on the decoding line when the third mode code is identified; The first step decodes a code indicating the distance from the starting pixel to the information change pixel located next to the starting pixel on the decoding line.
0 circuit, and when the third mode code is identified, the starting pixel and the first information change pixel on the decoding line located next to the first information change pixel located next to the starting pixel on the decoding line. a fifteenth circuit that decodes a code indicating the distance to the second information change pixel, an eleventh circuit that detects the first control signal from the encoded signal sequence, and a a 12th circuit that detects the control signal of No. 2; a 13th circuit that decodes a signal obtained by encoding a coded line without referring to reference line information; and a 14th circuit that detects the presence or absence of a code error. A facsimile signal decoding device characterized by comprising: