JPS5928054B2 - Substrate for hybrid integrated circuits - Google Patents
Substrate for hybrid integrated circuitsInfo
- Publication number
- JPS5928054B2 JPS5928054B2 JP54086267A JP8626779A JPS5928054B2 JP S5928054 B2 JPS5928054 B2 JP S5928054B2 JP 54086267 A JP54086267 A JP 54086267A JP 8626779 A JP8626779 A JP 8626779A JP S5928054 B2 JPS5928054 B2 JP S5928054B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- conductive pattern
- substrate
- connection area
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置特に混成集積回路に用いられる基
板に係り、さらに詳述するならばフェイスダウンボンデ
ィング(FaceDownBonding)法により半
導体チップを電気的、機械的に結合する際に適した基板
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate used in a semiconductor device, particularly a hybrid integrated circuit. The present invention relates to a substrate suitable for.
一般に、フェイスダウンボンディング法は、基板表面と
半導体チップの主表面とを互に対向させて基板上の接続
領域及び半導体チップ上の電極のいずれか一方又は両方
に形成された突起状のはんだ部をそれぞれ接触させた後
、それらを同時に加熱して冷却することにより、前記は
んだ部を介して基板上の接続領域と半導体チップ上の電
極を電気的に接続すると共に、半導体チップを基板上に
固定するようにしたもので、この方法は半導体装置特に
混成集積回路の性能向上や集積度の向上、製造工程の簡
素化、歩留りの向上等に有効な接続方法として多く利用
されている。In general, the face-down bonding method uses protruding solder parts formed on either or both of the connection area on the substrate and the electrode on the semiconductor chip, with the substrate surface and the main surface of the semiconductor chip facing each other. After bringing them into contact, they are simultaneously heated and cooled to electrically connect the connection area on the substrate and the electrode on the semiconductor chip via the solder portion, and to fix the semiconductor chip on the substrate. This method is widely used as an effective connection method for improving the performance and degree of integration of semiconductor devices, especially hybrid integrated circuits, simplifying manufacturing processes, and increasing yield.
この種の接続方法において従来用いられている基板とし
ては、第1図a及びbに示すように、アルミーナ等の絶
縁材料よりなる基板本体1上に、kg一Pd又はAuな
どで導電性パターン2を所定の形状に形成し、前記導電
性パターン2の複数の接続領域を除く部分を除いてその
周面を取り囲むようにガラスフリットなどの材料よりな
るガラス膜3を形成して、導電性パターン2上の各々の
接続領域に前記ガラス膜3よりも突出させて突起状を有
するはんだ部4をそれぞれ形成したものである。As shown in FIGS. 1a and 1b, a board conventionally used in this type of connection method includes a board body 1 made of an insulating material such as alumina, and a conductive pattern 2 made of Pd or Au. is formed into a predetermined shape, and a glass film 3 made of a material such as glass frit is formed to surround the circumferential surface of the conductive pattern 2 except for the plurality of connection areas. A protruding solder portion 4 is formed in each of the upper connection regions to protrude beyond the glass film 3.
なお、前記はんだ部4には、通常Sn40%、Pb60
%のはんだが使用される。しかしながら、このような基
板においては、導電性パターン2上に形成された接続領
域のはんだ部4がはんだに濡れない膜3で取り囲まれて
いるため、はんだに濡れない膜3の厚み分だけ突起状の
はんだ部4が実質的に低くなつてしまう。Note that the solder portion 4 usually contains 40% Sn and 60% Pb.
% solder is used. However, in such a board, since the solder portion 4 in the connection area formed on the conductive pattern 2 is surrounded by the film 3 that does not wet with solder, the protrusion shape increases by the thickness of the film 3 that does not wet with solder. The solder portion 4 becomes substantially lower.
通常、導電性パターン2はガラスフリットを使用した場
合、10〜30μ程度の厚みがあり、ガラスフリットの
焼成時にそれが接続領域のはんだ部4にだれて接続領域
の面積のバラツキが大きくなり、これによつて、前記は
んだ部4の高さがバラツキを生じ、歩留及び信頼性の低
下を招いていた。また、前記はんだ部4の下部がはんだ
に濡れない膜3よりも低いため、はんだ部4を形成する
時にはその接続領域に対し通常、フラックスが使用され
ているが、ボードの発生により接続領域の表面が十分に
活性化されず、はんだの濡れに差を生じ、はんだ部4の
バラツキを招く要因となつていた。さらに、半導体チッ
プを接続した後その接続状態を確認するため、通常、基
板本体1と平行して実体顕微鏡等で観察を行つているが
、この場合はんだに濡れない膜によつて接続領域が観察
しにくくなる等の欠点があつた。本発明は以上の点に鑑
み、このような問題を解決すると共にかかる欠点を除去
すべくなされたもので、その主目的は接続箇所がまわり
に付けられたガラス膜の影響で半田ぬれ性が悪くなるこ
とを防止することができる混成集積回路用基板を提供す
ることにある。Normally, when glass frit is used as the conductive pattern 2, it has a thickness of about 10 to 30 μm, and when the glass frit is fired, it sag on the solder part 4 of the connection area, which increases the variation in the area of the connection area. As a result, the height of the solder portion 4 varies, resulting in a decrease in yield and reliability. In addition, since the lower part of the solder part 4 is lower than the film 3 that does not wet with solder, flux is normally used for the connection area when forming the solder part 4, but the surface of the connection area is not activated sufficiently, causing differences in solder wetting, and causing variations in the solder portions 4. Furthermore, after connecting semiconductor chips, in order to confirm the connection state, observation is usually performed using a stereomicroscope in parallel with the board body 1, but in this case, the connection area is observed using a film that does not get wet with solder. There were drawbacks such as making it difficult to use. In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The main purpose of the present invention is to prevent solder wettability from being poor due to the influence of the glass film surrounding the connection points. It is an object of the present invention to provide a hybrid integrated circuit board that can prevent such problems from occurring.
また、本発明の他の目的は導電性パターンの接続領域に
形成される突起状を有するはんだ部の高さのバラツキを
少なくすることができると共に、フエイスダウンボンデ
イングに好適なはんだ部の形状をバラツキなく形成する
ことができ、また、歩留の向上および信頼性の向上を図
ることができると共に作業性を高めることができる混成
集積回路用基板を提供することにある。このような目的
を達成するため、本発明は、絶縁性をもつ基板本体の主
表面に形成された導電性パターン上の接続領域に突起状
を有するはんだ部を設け、かつ前記はんだ部を取り囲む
ように形成されたガラス膜を設け、前記はんだ部はその
下部が前記ガラス膜よりも高く位置するように形成した
ものである。以下、図面に基づき本発明の実施例を詳細
に説明する。Another object of the present invention is to reduce variations in the height of solder parts having protrusions formed in connection areas of conductive patterns, and to reduce variations in the shape of solder parts suitable for face-down bonding. It is an object of the present invention to provide a substrate for a hybrid integrated circuit, which can be formed without any problems, and which can improve yield and reliability as well as improve workability. In order to achieve such an object, the present invention provides a solder portion having a protrusion in a connection area on a conductive pattern formed on the main surface of an insulating substrate body, and a solder portion that surrounds the solder portion. A glass film formed on the solder portion is provided, and the solder portion is formed such that a lower portion thereof is located higher than the glass film. Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第2図a及びbは本発明の一実施例を示す要部平面図及
びその−5線断面図であり、同図において第1図と同一
又は相当部分は同一番号を用いている。FIGS. 2a and 2b are a plan view of essential parts and a cross-sectional view taken along the line -5 showing an embodiment of the present invention, and in these figures, the same or equivalent parts as in FIG. 1 are designated by the same numbers.
この実施例では、導電性パターン2の接続領域にはんだ
に濡れやすい金属膜5をガラス膜3と同じか又はそれ以
上の厚みを有して形成し、この金属膜5上にはんだ部4
を突出させて突起状に形成したものである。この場合、
導電性パターン2は通常使用されているAg−PdにP
tを添加したり、Agの比を増してはんだの濡れ性を良
くしたものである。上記実施例の基板によると、導電性
パターン2の接続領域に突起状に形成されるはんだ部4
の高さのバラツキを少なくでき、またはんだに濡れやす
くするため、前記はんだ部4の形状をバラツキなく形成
でき、これによつて、歩留および信頼性の向上をはかる
ことができるとともに、従来のものに比べてはんだに濡
れない領域に邪魔されることなく、接続状態を観察でき
るので、作業性を高めることができる。In this embodiment, a metal film 5 that is easily wetted by solder is formed in the connection area of the conductive pattern 2 to have a thickness equal to or greater than that of the glass film 3, and a solder portion 4 is formed on this metal film 5.
It is formed into a protrusion shape by protruding. in this case,
The conductive pattern 2 is composed of commonly used Ag-Pd and P.
The solder wettability is improved by adding t or increasing the ratio of Ag. According to the substrate of the above embodiment, the solder portion 4 is formed in a protrusion shape in the connection area of the conductive pattern 2.
In order to reduce the variation in the height of the solder part 4 and to make it easier to wet the solder part 4, the shape of the solder part 4 can be formed without variation. Work efficiency can be improved because the connection status can be observed without being disturbed by areas that are not wetted by solder.
また、接続箇所がまわりに付けられたガラス膜の影響で
半田ぬれ性が悪くなることを防止することができる。第
3図a及びbは本発明の他の実施例を示す要部平面図及
びそのl−『線断面図であり、同図において第2図と同
一又は相当部分は同一番号を用いている。Further, it is possible to prevent the solder wettability from becoming poor due to the influence of the glass film attached around the connection point. FIGS. 3a and 3b are a plan view of main parts and a sectional view taken along the line 1--1 of the same, showing another embodiment of the present invention, and in these figures, the same or corresponding parts as in FIG. 2 are designated by the same numbers.
この実施例において上述と相異している点は、導電性パ
ターン2の各々の接続領域と一致する箇所にガラス膜3
の膜厚と同じかそれ以上の膜厚をもつ金属あるいは絶縁
材料よりなる下地膜6を形成し、この下地膜6により前
記接続領域を持ち上げることによつて該接続領域に形成
される突起状のはんだ部4をガラス膜3よりも高くなる
ように形成したものである。この場合、前記下地膜6は
ガラス膜3と同一材料を用いてもよいし、又は導電性パ
ターン2と同じ材料を用いてもよい。したがつて、この
実施例においても上記実施例と同効である。以上のよう
に、本発明によれば、接続箇所がまわりに付けられたハ
ンダ膜の影響で半田ぬれ性が悪くなることを防止するこ
とができ、また、導電性パターンの接続領域に形成され
る突起状を有するはんだ部の高さのバラツキを少なくで
きると共に、はんだに濡れやすくなるため、フエイスダ
ウンボンデイングに好適なはんだ部の形状をバラツキな
く形成でき、歩留の向上および信頼性の向上をはかるこ
とができる。The difference in this embodiment from the above is that a glass film 3 is provided at a location corresponding to each connection area of the conductive pattern 2.
By forming a base film 6 made of metal or insulating material with a film thickness equal to or greater than that of the base film 6, and lifting the connection area by this base film 6, a protrusion-like shape formed in the connection area is formed. The solder portion 4 is formed higher than the glass film 3. In this case, the base film 6 may be made of the same material as the glass film 3 or the same material as the conductive pattern 2. Therefore, this embodiment also has the same effect as the above embodiment. As described above, according to the present invention, it is possible to prevent the solder wettability from deteriorating due to the influence of the solder film attached around the connection point, and also to It is possible to reduce the variation in the height of the solder part with protrusions, and it also becomes easier to wet with the solder, so the shape of the solder part suitable for face-down bonding can be formed without variation, improving yield and reliability. be able to.
さらに、ガラス膜に邪魔されることなく、接続状態を容
易に観察できるので、作業性を高めることができるとい
う効果がある。Furthermore, since the connection state can be easily observed without being obstructed by the glass film, there is an effect that workability can be improved.
第1図a及びbは従来の混成集積回路用基板を示す一部
平面図及びI−V線断面図、第2図a及びbは本発明の
一実施例を示す要部平面図及び−1線断面図、第3図a
及びbは本発明の他の実施例を示す要部平面図及び一『
線断面図である。
1・・・・・・基板本体、2・・・・・・導電性パター
ン、3・・・・・・ガラス膜、4・・・・・・接続領域
のはんだ部、5・・・・・・はんだに濡れやすい金属膜
、6・・・・・・接続領域を持ち上げるための下地膜。1A and 1B are a partial plan view and a sectional view taken along the line IV of a conventional hybrid integrated circuit board, and FIGS. Line sectional view, Figure 3a
and b are main part plan views showing other embodiments of the present invention;
FIG. DESCRIPTION OF SYMBOLS 1... Board body, 2... Conductive pattern, 3... Glass film, 4... Solder part in connection area, 5...・Metal film that is easily wetted by solder, 6... Base film for lifting the connection area.
Claims (1)
形成された導電性パターンと、この導電性パターンの接
続領域を取り囲むように形成されたガラス膜と、上記導
電性パターンの接続領域上に設けられ、上記導電性パタ
ーンと電気的に接続されるはんだ部とを備え、上記はん
だ部の下面を上記導電性パターン上の上記ガラス膜上面
と同一またはそれ以上の高さに設置した混成集積回路用
基板。1 An insulating substrate body, a conductive pattern formed on the main surface of this substrate body, a glass film formed so as to surround the connection area of the conductive pattern, and a glass film formed on the connection area of the conductive pattern. and a solder part electrically connected to the conductive pattern, the lower surface of the solder part being set at the same or higher height than the upper surface of the glass film on the conductive pattern. Circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54086267A JPS5928054B2 (en) | 1979-07-06 | 1979-07-06 | Substrate for hybrid integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54086267A JPS5928054B2 (en) | 1979-07-06 | 1979-07-06 | Substrate for hybrid integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5610952A JPS5610952A (en) | 1981-02-03 |
| JPS5928054B2 true JPS5928054B2 (en) | 1984-07-10 |
Family
ID=13882035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54086267A Expired JPS5928054B2 (en) | 1979-07-06 | 1979-07-06 | Substrate for hybrid integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5928054B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH068404B2 (en) * | 1984-12-28 | 1994-02-02 | 日東電工株式会社 | Bonding adhesive tape or sheet |
-
1979
- 1979-07-06 JP JP54086267A patent/JPS5928054B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5610952A (en) | 1981-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100537243B1 (en) | Semiconductor device and method for manufacturing the same | |
| US3952404A (en) | Beam lead formation method | |
| JPS5839048A (en) | Flexible region adhesive tape | |
| US3675089A (en) | Heat dispenser from a semiconductor wafer by a multiplicity of unaligned minuscule heat conductive raised dots | |
| JP4703938B2 (en) | Air pad solder joint structure of wafer level package and manufacturing method thereof | |
| JPH09260436A (en) | Semiconductor device | |
| US3543106A (en) | Microminiature electrical component having indexable relief pattern | |
| US3371148A (en) | Semiconductor device package and method of assembly therefor | |
| JPS5928054B2 (en) | Substrate for hybrid integrated circuits | |
| US4672415A (en) | Power thyristor on a substrate | |
| KR20080037681A (en) | Semiconductor chip, manufacturing method thereof, and semiconductor device | |
| US3763550A (en) | Geometry for a pnp silicon transistor with overlay contacts | |
| JPS5850021B2 (en) | Manufacturing method for semiconductor devices | |
| JPH03285338A (en) | Bonding pad | |
| CN101523584A (en) | Protective barrier layer for electrodes of semiconductor devices | |
| JPS6016749B2 (en) | Packages for integrated circuits | |
| JPH0396243A (en) | Semiconductor integrated circuit device | |
| JPH0719797B2 (en) | Semiconductor device mounting tool | |
| JPS6041728Y2 (en) | semiconductor equipment | |
| JP2600898B2 (en) | Thin package device | |
| JPH0119395Y2 (en) | ||
| JPH019160Y2 (en) | ||
| JPS6153854B2 (en) | ||
| JPH01286430A (en) | Mounting method for semiconductor chip | |
| JPS6317546A (en) | Semiconductor device |