JPS5928059B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory for dynamic memory suitable for use in semiconductor integrated circuits.

First, an outline of the present invention will be explained regarding the case where a P-type silicon substrate is used. In the present invention, two plates of gate electrodes are arranged parallel to each other in an electrically separated state between the source and drain, and the gate electrode G, which is closer to the drain side, is formed of a Pf type polycrystalline silicon layer. Furthermore, the silicon surface immediately below is formed of a very shallow n-type layer with low concentration. Between this electrode and the source region, a normal n-channel M
A gate electrode of an OS structure, an insulating film, and a P-type substrate are formed. In this structure, by applying an appropriate voltage to the gate electrode G1 adjacent to the drain side and the gate electrode and drain electrode adjacent to the source side, holes are accumulated on the silicon surface directly below G1, and There is a mode in which an n-type channel layer is formed near the p-n junction of G1 to form a state "01" in which current can flow between the drain region and the source region, and a mode in which holes are not accumulated directly under G1. The n-layer becomes a depletion layer unless a positive voltage is applied to G2, and even if a positive voltage is applied to G2, no current flows between the source and drain. ! 1111? Enables writing and reading.

Next, a conventional semiconductor memory will be explained.

There are two types of semiconductor memory: dynamic and static types. Highly integrated memories have extremely small area requirements per memory cell, such as the one-transistor or one-transistor type shown in Figure 1.
Dynamic memories consisting of capacitors are often used. However, if the capacitance of the capacitor C used for storage is extremely reduced, it becomes difficult to determine whether the memory cell is charged or not, so the memory cell according to this method cannot be made very small and requires a certain amount of area. In addition, the state of charge of capacitor C changes due to damage caused by alpha rays,
Minimizing the cell area poses extremely difficult problems, such as errors in the stored contents. In response, in February 1978, the IEEE academic society
tiOnalSOlld-State Circuits
11StratifiedCharge proposed by Mr. Darrel MErb at the conference
Mem0ry-DigestOfTechnicalP
apers, P. P. 24-25, and 1978 1
February 1 EEE Society) InternationalOnalEle
P. announced at ctrOnDeviceMeeting. K. Mr. Chatterjee? 1Taper
Is01atedDynamicGainRAMC0I
F1 changes the structure of conventional field-effect MOS transistors by accumulating charged particles (holes, electrons) in the silicon surface layer directly below the gate, and forming a channel region directly below them. State Vfl- in which current flows between sources and state 10 in which current does not flow! ! A memory cell is formed by making . In this structure, one memory cell consists of almost one transistor, and the feature is that it requires a smaller area than the conventional one-transistor, one-capacitor memory cell. Next, as a conventional memory of this type, D. M. Mr. Erb's 1Stratif
iedChargeMem0ry! 5 in FIG. 2) FIG. 3 will be explained. As shown in FIG. 2 on a P-type silicon substrate 1, a drain 2, a source 3, and a shallow n-type region 4 with a low concentration are formed adjacent to the drain. Thereon, a gate electrode 5 is formed directly above region 4 and a gate electrode 6 is formed between this electrode 5 and source region 3 with an insulating film interposed therebetween. When integrated rather than a single cell, as shown in Figure 3,
The gate electrode 6 is arranged perpendicular to the drain 2, source 3, and gate electrode 5. Next, the operating principle will be explained.

When writing first, source 3, drain 2
If you want to write the state of 11"1, apply -VR to the gate electrode 6. At this time, apply a voltage of 1c to the gate electrode 5. Since the voltage applied to the gate electrode 5 is negative, the holes are transferred to the silicon surface of the n-type region 4 directly under the gate electrode 5 through the silicon surface. Next, when the voltage applied to the gate electrode 6 is set to O or a positive voltage, the hole in the region 4 stays at that location because it acts to prevent the hole from dissipating. Since the donor concentration in the n-type region 4 is low when there is no implantation, a depletion layer is formed in the n-type region 4 by applying a relatively small negative voltage to the gate electrode 5. Therefore, no current flows between the drain 2 and the source 3 even if a positive voltage is applied to the gate electrode 6. However, since holes are now injected as described above, the n-type The thickness of the depletion layer in the region 4 layer is reduced (by commensurately inducing electrons) and the thickness of the depletion layer in the n-type region 4
A channel is formed near the pn junction of. The time this hole remains in region 4 is long enough because the electric field formed by the pn junction prevents the hole from dissipating.゛1
In order to write the state of 01, the voltage applied to the gate electrode 5 is set to a voltage of -{Jc(0), which is greater than the voltage -c when writing 111. When this voltage is higher than a certain threshold voltage -Vc(1), holes are not transferred to the region 4 even if -VR is applied to the gate electrode 6.
Therefore, no change occurs in the depletion layer in the n-type region 4. At this time, due to the relative relationship between the voltages applied to the gate electrodes 5 and 6, the potential barrier on the silicon surface becomes lower with respect to holes, and if holes exist in region 4, the gate electrode The holes are pushed out to the silicon surface directly below the electrode 6. In the above manner, a state of "0" is formed.When reading out one memory cell, the gate electrode 5 is
When a negative voltage close to volts is applied to fix holes, and a positive voltage greater than the threshold voltage Vth is applied to the gate electrode 6, the surface of the P-type substrate 1 forms an n-type inversion layer. When a channel is formed and a voltage is applied between the source and the drain, holes are accumulated in region 4, and if there are, a current flows between the source and drain, indicating the state of T9ll, and the holes are removed. If there is no accumulation, this current will not flow and a state of ゛゜0゛ will be exhibited. In the case of this memory cell, the gate electrode 6 serves as a select line, and the gate electrode 5 serves as a write line. Therefore, as can be seen in FIG. 3, the gate electrode 5 and the gate electrode 6 must be wired orthogonally. In particular, the gate electrode 6 is connected to the source 3, the drain 2, and the gate electrode 5.
It has the disadvantage that it is extremely difficult to fabricate. In other words, it is so difficult to introduce an n-type impurity directly under the gate electrode 5 and to form the gate electrode 5 of polycrystalline silicon only thereon, considering the order of the process. Also, it was announced at the EDM Society in December 1978! TTaperIsOl
In the case of the DynamicGainRAMCell, as shown in FIG. 4, a P-type region 9 is provided directly under the gate electrode 11 to create a hole accumulation layer, and the periphery of the P-type region 9 is The shape area is 7.

Further, the P+ region 8 under the field oxide film 10 is used as a source 7 of holes required for injection, and this P+ region 8 is used as a source 7 of holes required for injection.
+ region 8 and P-type region 9 directly under the gate are separated by an intermediate n
A tapered oxide film 10 whose thickness gradually increases is required to take advantage of changes in the potential of the shaped region 7 and its surface, and controlling the film thickness also becomes a difficult problem. The present invention accumulates charged particles (holes, electrons) on the silicon surface and inner surface directly below the gate electrode, and finally
By modulating the source-to-source current,! 118-10? This relates to a memory cell that creates two states of W, but compared to the conventional memory cells mentioned above, it is easy to manufacture, has a large operating margin, has a low operating voltage, and has large-scale integration. It has many features such as an electrode arrangement suitable for circuits.

FIG. 5 shows a cross-sectional view of a memory cell according to an embodiment of the present invention, and FIG. 6 shows its equivalent circuit.

FIG. 7 shows a layout when memory cells are arranged as an integrated circuit. The select line is the drain electrode 19
The writing line is performed by applying an appropriate voltage to the first gate electrode 16, and reading is performed by applying an appropriate voltage to the second gate electrode 17 and source 15. Next, to describe the operating principle of this memory cell, as shown in FIG. It consists of a second gate electrode 17 (hereinafter referred to as G2) formed between G1 and the source 15, and the drain electrode 19 is perpendicular to these wiring lines to form a select line.

G1 of this memory cell is formed of polycrystalline silicon with a sufficiently high concentration. Since the silicon substrate 1 directly under G, has an extremely shallow n-type conductivity region 14, a built-in electric field is formed between the gate electrode 16 and the n-type region 14, so that this shallow n-type conductivity region 14 is The region 14 forms a depletion layer even when no negative voltage is applied to G1, and prevents conduction of electrons from the source 15 to the drain 13. In other words, by appropriately selecting the concentration and thickness of the n-type region 14 and the concentration of P+ polysilicon in G1, no source-drain current flows even without applying a negative voltage to G1.
A state of 1W is obtained.

Further, the electric field formed in the n-type region 14 acts to prevent holes from dissipating. Next, the case of writing 1F' and 10' will be explained. When writing 11'', the drain voltage Vd is set to d=0, -G, (1) is written to G, and -G2 is written.
Apply Vg2.

If a hole is accumulated on the silicon surface directly under G2 due to the negative voltage applied to G2, and the value of 1 g1 (1) applied to G1 is sufficient for the transfer of this hole, the hole will be transferred to G1. The electrons are injected into the n-type region 14 directly below, are attracted by the built-in electric field, accumulate in the n-type region 14, and induce new electrons in the n-type region. The width of the depletion layer is narrowed by these electrons, and this region 14
form a channel. After writing is completed, change the voltage applied to G1 to -Vgl, which is greater than -Vgl (1).
Or change to O bolt. (-g1(1K-G,).
The voltage applied to G2 is also set to a value of 0 or G2' rather than -Vg2. Next, the drain voltage Vd is d=Ud
Make it. By applying a voltage Ud between the substrate and the substrate, the holes accumulated in region 14 are further prevented from dissipating. Also, this increases the potential barrier on the silicon surface of the p-n region directly below, which is dominated by G1 and G2, so at least when a voltage of Vd is applied to the drain, there is a transition from G2 to G, or from G, from G
There is no light transport of holes to , . Writing 1101 similarly sets the drain voltage Vd to d=O, adds a voltage of 1 G, (0) to G1, and adds -Vg2 to G2.

-Vgl(0) is a voltage greater than one g1(1), G2
The voltage is not high enough to transfer holes from the silicon surface directly below to the region 14 directly under G1.

Conversely, if there are holes in the region 14, the voltage is set to transfer the holes to the silicon surface directly under the G2 gate.

After writing is completed, -g1(0) is set to g1 and -G2 is set to Vg2'. Then, the drain voltage is set to Vd=U
Make it d. In this way, -Vgl to G1, V to G2! G2
, drain voltage Vd, source voltage Vs=Us, and the state in which voltages are applied to each is the so-called standby state 111
11 or 1!01W information is retained. Next, as a reading method, S=US1 for the source, Vd for the drain
=0, +Vg2(R) is applied to G2, and -Vg/ is applied to G1.

If holes are accumulated in the region 14, a source-drain current will flow under the above applied voltage. If no holes are accumulated in the region 14, no source-drain current flows. This current may be determined by providing a sensor at the end of the source electrode. When a cell is selected, the voltage of the drain region is always O, but the drain voltage of other unselected cells is Vd=Ud
is set to When a positive voltage force Ud is applied to the drain region, the potential barrier becomes large and hole transfer is blocked (even if a voltage is applied to G, . . . G2). Note that the applied voltage in the above description is just an example, and the value, polarity, and application order of the applied voltage can be changed depending on the design method. next,
An example of a process and manufacturing method for realizing a memory cell according to the present invention will be described. As shown in FIG. 8, a thick oxide film 10 is formed on a P-type silicon substrate 1 to isolate elements, and a gate oxide film 18a is thermally generated over the entire surface. Next, the 9th
As shown in the figure, after forming polycrystalline silicon on the entire surface and adding P-type or n-type impurities, G217 is formed by photolithography and polycrystalline silicon etching. Note that at this time, in order to adjust the threshold voltage, a P-type impurity such as boron may be introduced directly under the gate oxide film 18a by ion implantation or the like. Next, after oxidizing the surface of the polycrystalline silicon layer 17, an insulating film 18b is formed on the silicon surface.
Then, an n-type region 14 is formed by ion implantation or the like. Next, a polycrystalline silicon film is formed over the entire surface by CVD or the like, and p-type impurities are added. Subsequently, using photolithography, Gll6 is formed as shown in FIG. 10. At this time, the resist 21 used for photoengraving is left on G, l6, and this resist 21 is used as a mask to mask the source.
The region that will become the drain is doped with n-type impurities by ion implantation, or an oxide film is formed on polycrystalline silicon, and using this as a mask, thermal diffusion is performed to form the drain 13 in the cage region.
A sauce 15 is formed. Furthermore, as shown in FIG. 5, after forming an insulating upper oxide film 20 on the entire surface, a contact hole is made in the drain 13, and a metal material such as aluminum is deposited.
The aluminum electrode 19, which is a drain electrode and serves as a select line, is wired by photolithography. The shape of the completed cell is shown in FIG. In addition, in order to apply positive and negative voltages to the gate of this memory cell, an n-type well is locally created as a peripheral circuit to form a P-channel transistor, but the source and drain of this transistor are The region may be formed at the same time as the above-mentioned addition of P+ impurities to polycrystalline polysilicon. The features of this embodiment compared to the conventional one are as follows. (1)E
The select line of Mr. rb's ChargememOry is an electrode made of polycrystalline silicon indicated by the gate electrode 6, but in the case of this example, the select line is connected to the drain 13.
It is.

Compared to forming the drain with polycrystalline silicon, the connection between the drains is made by the final metal wiring, which makes manufacturing much easier than the former. Also, by making the drain a select line, the voltage applied to the drain is a binary value of Ud (50), but if Erb's gate electrode 6 is made a select line, a three-value voltage is applied for writing, holding, and reading. In addition, in the case of this embodiment, since the material of the first gate G1 adjacent to the drain is made of P-domain polycrystalline silicon, it is difficult to apply a voltage to the gate. Even if it has never happened before, the n-type silicon region directly below is depleted.This makes writing easier, and Gl, G
Lower the voltage applied to 2. With appropriate design, the voltage applied to G1 may not necessarily have a negative value. (2) The two gate electrodes Gl and G2 are Er
In Mr. b's ChargememOry, the wiring is orthogonal, but since the wiring is parallel, the two layers can be electrically separated by a thin insulating film and then laid out on top of each other, thereby reducing the cell area.

Furthermore, as shown in FIG. 7, the source diffusion layer can be shared with the adjacent memory cell due to the circuit design, and the drain can also be shared with the adjacent memory cell, so the source diffusion layer is 1/1/2 per cell. The contact hole for the two wires and the drain becomes 1/2 contact hole per cell, making it possible to reduce the area. The aforementioned area reduction is TaperIsOlated
In the case of a dynamic gain RAM cell, this cannot be specified. Also1TaperIs01ateddy
In the case of namicGainRAMce1I, it is necessary to apply extremely high positive and negative values to the gate for hole transfer, but in the case of this embodiment, the applied voltage can be reduced.

As described above, according to the present invention, the first line, which becomes the write line and the read line between the source and drain,
The second gate electrodes are arranged parallel to each other, and a drain electrode is formed on the first and second gate electrodes through an insulating film so as to be orthogonal to both gate electrodes, and this is used as a select line. Therefore, the manufacturing thereof is extremely easy, and the cell area can be reduced, so that a semiconductor memory suitable for use in a semiconductor integrated circuit can be obtained.

[Brief explanation of the drawing]

Figures 1A and 1B are equivalent circuit diagrams and cross-sectional views of a 1-transistor, 1-capacitor type dynamic cell, Figures 2 and 3 are cross-sectional views and top views of Stratified charge mem Ory, and Figure 4 is TaperedIsOlated.
A cross-sectional view of a dynamic cell, FIG. 5 is a cross-sectional view of a memory cell showing an embodiment of the present invention, FIG. 6 is an equivalent circuit diagram of the embodiment of FIG. 5, and FIG. 7 is an integrated circuit of the embodiment of FIG. FIGS. 8 to 10 are explanatory diagrams showing the manufacturing method of the embodiment shown in FIG. 1 is a P-type substrate, 2 is a drain, 3 is a source, 4 is an n-type region, 5 is a gate electrode, 6 is a gate electrode, 7 is an n-type region,
8 is a P+ region, 9 is a P type region, 10 is an oxide film, 11 is a gate electrode, 12 is a gate oxide film, 13 is a drain, 14
is an n-type region, 15 is a source, and 16 is a P+ type polycrystalline silicon j
17 is a polycrystalline silicon gate (second gate electrode), 18a and 18b are gate oxide films, 19 is an aluminum electrode (drain electrode), 20 is an oxide film, and 21 is a resist.

Claims (1)

[Scope of Claims] 1. A source and a drain spaced apart from each other on a semiconductor substrate of a first conductivity type; write lines arranged in parallel between the source and drain and electrically isolated from each other;
first and second gate electrodes serving as readout lines; a shallow, low-concentration second conductivity type region formed adjacent to the drain on the substrate surface directly under the first gate electrode near the drain side; A drain electrode connected to the drain via a contact hole and serving as a select line formed on the two gate electrodes via an insulating film so as to be orthogonal to the gate electrodes. semiconductor memory. 2. The above-mentioned first gate electrode is formed of P^+ polycrystalline silicon with a sufficiently high concentration, and the shallow second conductivity type region with low concentration directly under the first gate electrode is an n-type region. A semiconductor memory according to claim 1, characterized in that: 3. The semiconductor memory according to claim 1 or 2, wherein the first and second gate electrodes are arranged on top of each other with an insulating film interposed therebetween.