JPS5928917B2 - cathode ray tube display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cathode ray tube display device consisting of two screens, in which particularly minute display information can be written at any position on the screen with a light pen, and the display information is displayed on the screen. The present invention relates to a cathode ray tube display device in which characters, figures, etc. can be edited.

The present invention particularly aims to provide a cathode ray tube display device that is applicable to devices where writing and erasing of display information is performed in units of minute pixels on the screen when using a light pen. . For example, if all the information displayed on the screen is displayed as 15 characters horizontally and 8 lines vertically as shown in Figure 1A, with 256 dots (picture elements) horizontally and 192 lines vertically, then 1 Characters are displayed in blocks formed by 16 horizontal dots and 24 vertical lines.

Therefore, when writing fine line characters such as Chinese characters in this display range, the positioning of the light pen tends to shift depending on the angle of the pen, making it difficult to write accurately. As a means of solving the above inconvenience,
A second cathode ray tube display device is provided which magnifies and displays picture elements corresponding to one character, and fine writing and erasing in pixel units is performed on this second cathode ray tube screen, in other words, line correction is performed. There is a method in which all information is transferred to a display area corresponding to one character at an appropriate position on the first cathode ray tube screen where all information is displayed. However, in the case of a figure written over a wide area that cannot be accommodated in the display area for one character, the above method is used to make corrections one block at a time and sequentially transfer it to the first cathode ray tube screen. Using the method of updating display information,
It is difficult to understand the connection between the boundary points where two blocks touch each other, and correction and transfer of each block must be repeated several times. The present invention seeks to provide means for solving the above-mentioned disadvantages.

In other words, the present invention accomplishes the above-mentioned 1 process.
It has a sub-memory that stores picture elements included in a square display area obtained by combining a character's worth of picture element blocks and a plurality of adjacent blocks, and displays this sub-memory information on a second cathode ray tube. Then, in other words, writing and erasing on this screen, after correcting the line, inserting it at any appropriate position on the screen of the first cathode ray tube where all the information is displayed, It is an object of the present invention to provide a cathode ray tube display device in which display information on the screen of a first cathode ray tube can be edited.

The present invention will be explained below with reference to the drawings, but it is assumed here that all information displayed on the screen of the first cathode ray tube is displayed in 256 dots horizontally x 192 dots vertically, as shown in FIG. 1A. The information in the submemory displayed on the screen of the second cathode ray tube is 48 dots horizontally x 48 dots vertically, as shown in Figure 1B. It is assumed that twice as many picture elements can be displayed.

In addition, we chose a 48 x 48 dot square for the display information of the submemory because it is easier to write within a square area when creating figures, etc. This is because the expansion of one picture element becomes maximum. The display information on the first cathode ray tube screen and the submemory display information on the second cathode ray tube screen are transferred to the block to which the light pen is applied on the first cathode ray tube screen, and to each block on its left and right. The information contained in the square display area consisting of a total of 6 blocks, which is the 3 blocks directly above or below the 3 blocks closest to the position where the light pen is applied, is taken as one unit, and the information is extracted from 6 blocks in the main memory. It is assumed that the data is transferred to the submemory or from the submemory to six blocks of the main memory. Of course, in the present invention, the square display area may be specified as a total of 6 blocks, including 2 blocks on the right side from the block where the light pen is applied, 3 blocks adjacent to the 3 blocks above and 3 blocks above or below, Other designation methods may be used as long as it is a square. Further, the information for a total of 6 blocks forming a square is equivalent to the information for a total of 24 blocks, 4 blocks vertically and 6 blocks horizontally.
In this case, the enlargement of one pixel of each block will be small, so if we take into account correction work such as lines, it is desirable to have an enlarged square with information for the optimal 6 blocks.Here, we will use this example below. explain. FIG. 2 is a block circuit diagram showing the configuration of an apparatus according to an embodiment of the present invention, in which 1 is a first cathode ray tube;
2 is the second cathode ray tube, 3 is the central processing unit (hereinafter simply CPU)
4 is a light pen, and 5 is a keyboard switch for applying a plurality of key inputs to the embodiment device as shown in FIG.

The first cathode ray tube 1 also includes a main memory 11 in which all information displayed on the screen is stored, a parallel/serial zeta converter 12, (1) a bus buffer 13, and (1) a selector 14. 1 constitutes a cathode ray tube display section. The second cathode ray tube 2 has a sub-memory 21 in which all the information displayed on the screen is stored, a parallel/serial zeta converter 22, (2) a bus buffer 23, and (2) a selector 24. It constitutes the pipe display section. In the main memory 11, each storage address has a one-to-one correspondence with each of all picture elements on the screen of the first cathode ray tube 1, and reading is performed in synchronization with raster scanning of the first cathode ray tube 1. As a result, the first cathode ray tube 1 refreshes and displays the information stored in the main memory 11 on the screen. Furthermore, data stored at each address of the main memory 11 is inputted and outputted via (1) a bus buffer 13, and address data is supplied from (1) a selector 14. On the other hand, in the submemory 21, each storage address has a one-to-one correspondence with each of all picture elements on the screen of the second cathode ray tube 2, and reading is performed in synchronization with raster scanning of the second cathode ray tube 2. As a result, the second cathode ray tube 2 refreshes and displays the information stored in the submemory 21 on the screen. The raster scanning of the second cathode ray tube 2 is synchronized with the raster scanning of the first cathode ray tube described above. Furthermore, data stored at each address of the sub-memory 21 is inputted and outputted via (2) a bus buffer 23, and address data is supplied from (2) a selector 24. Here, the total weather information displayed on the first cathode ray tube 1 is as shown in FIG.
Let us take as an example a case in which all the information that is regularly divided into programs and displayed on the second cathode ray tube 2 is six programs as shown in FIG. 1B.

Therefore, all picture elements displayed on the second cathode ray tube 2 are
As shown in Figure B, it becomes 48x48 dots. Reference numeral 6 in FIG. 2 is a synchronization signal generator, which generates a vertical synchronization signal (hereinafter simply referred to as VD) and a horizontal synchronization signal (hereinafter simply referred to as VD) for the first and second cathode ray tubes 1 and 2 based on the clock signal output from the oscillator 6a. (simply referred to as HD) and a blanking pulse BLK are created and output.

Further, 7 is a counter which indicates a dot clock CP (1j) corresponding to the picture element displayed on the first cathode ray tube 1 and a dot clock CP (2 j) corresponding to the picture element displayed on the second cathode ray tube 2.
) from the clock signal and outputs it. 15 is a main address counter, into which the above-mentioned D, HD, dot clock CP (1), and blanking pulse BLK are input;
By counting HD with D as a reference, a memory (1 ) Y address data is supplied to (1) the selector 14 and (1) the latch circuit 41.

At the same time, this main address counter 15 is set to a dot clock CP(1) (for example, 5.73MH) with the HD as a reference.
z), the memory (1)
) selector 14 and (1) latch circuit 41. Reference numeral 16 denotes a sub-address counter, which is similar to the above-mentioned main address counter 15 except that the dot clock CP(2) is input thereto.

Therefore, in the same way as the main address counter 15, this sub-address counter 16 sends information to (2) the selector 24 and (2) the latch circuit 42 in the sub-memory 21 corresponding to the pixel position in the Y direction of the second cathode ray tube 2. Memory (2) Y address data representing each storage address is supplied. At the same time, memory (2) X address data is also supplied from the sub-address counter 16 to the (2) selector 24 and (2) latch circuit 42. (1) Selector 1 mentioned above
4 and (2) selector 24 receives the CP described later as the other input.
Address bus AB from U is connected.

These (1) and (2) selects/14 and 24 select one of the two inputs by blanking pulse BLK. That is, during the screen refresh display period, in other words, during the non-blanking period, (1) the selector 14 selects memory (1) from the main address counter 15;
) X and Y address zeta inputs are selected and supplied to main memory 11. Also, during the same period, (2) selector 2
4 selects the memory (2) X and Y address data input from the sub-address counter 16 and supplies it to the sub-memory 21. At this time, (1) bus buffer 13 and (2) bus buffer 23 are not chip-selected, and the bus and port facing data bus DB are maintained at high impedance. Therefore, during the display period described above, the memory (1) X and Y address data supplied from the main address counter 15 is given to the main memory 11 via the (1) selector 14, so that The data at the storage address (here, data in 8-bit units) is output to the data bus.

Similarly, the sub-memory 21 is given the memory (2) Output to the data bus. The data outputted on these data buses CP(1) and CP(2) are loaded into shift registers forming parallel/serial converters 12 and 22, respectively, in a well-known manner, and dot clocks CP(1) and CP(2), respectively.
) is read out one picture element at a time.

As a result, screen display data of a series of picture elements read out from this is obtained. This display data is supplied to the cathodes of the first and second cathode ray tubes 1 and 2 through well-known amplifiers 10 and 20 for driving cathode ray tubes, and is displayed as bright spots on the screen. . In the apparatus of this embodiment, each part is set to an initial state when the power is turned on, and thereafter control processing of each part is started by key inputs using the key switch 5 and the light pen 4 as shown in FIG.

Therefore, the main routine of the CPU 3 is programmed to be based on key input. The key inputs shown in FIG. 3 are key switches (11) and (1) write (11), which make the first cathode ray tube 1 and the second cathode ray tube 2 respectively 11 main 11 and 11 sub 1i screens.

The key switches for erase\ are independent of each other, and one of the two switches is selected one by one. Further, key switches 1 main→sub 1 and 11 sub→main 11 are provided as data transfer key inputs between the main memory and the submemory. When one of the Ff main 11 and ) 1 sub 8 screen key switches is selected, the other is released. The key switches 11 write 11,) 1 erase 1), 11 main→sub 1, and 1 sub→main 11 are also configured to release the others by being pressed selectively. . Therefore, when these switches are pressed, they instruct the device to execute the processing in the corresponding mode. The key switch 5 shown in FIG. 2 switches the CP in response to such key input.
Instructs U3 to execute the process. That is, here, first, when the key switch 5 is pressed, a key press flag is set, and the main routine of the CPU 3 is set in advance to search for this flag, and the binary code data of the corresponding switch translated by the encoder 51 is
) CPU via bus buffer 52 and data bus DB
Incorporate into 3. The CPU 3 determines which key is to be input based on this zeta, and executes the input. The key inputs given to the CPU 3 are organized as follows. First of all
When writing directly on the screen of the cathode ray tube 1 with the light pen 4, press the key switch 11 main 11 shown in FIG. By applying the screen to the soil, writing is performed on the corresponding picture element. Also, the second
When writing on the screen of the cathode ray tube 2, all that is required is to press the key switch of the 1W sub 1 described above, and subsequent operations are performed in the same manner. As already mentioned, this is true in 11
This is because the write 1W key switch maintains its previous state. In the case of erasing picture elements in the first and second cathode ray tubes 1 and 2, the selection of the erasure screen of the cathode ray tubes is selected using the key switches 11 main 11 and 11 sub 1, and the above 11 writing 11 key switch)F
This is done by switching to erase 11. Next, when transferring the information drawn on the screen of the second cathode ray tube 2 to the screen of the first cathode ray tube 1, first press the 11 sub → main 1 key switch, then move the light pen 4 to the first cathode ray tube 1. tube 1
By applying the light onto the screen of the second cathode ray tube 2, the image of the second cathode ray tube 2 is transferred to six square blocks at the positions indicated by the light pen 4. Conversely, when transferring the image of the six square blocks on the screen of the first cathode ray tube 1 to the second cathode ray tube 2, press the key switch 11 main → sub 11 and move the light pen 4 to the first cathode ray tube 2. By hitting a desired block on one screen, information is transferred between the six adjacent blocks.

Based on the key inputs for the operations described above, the CPU 3 controls each section and controls the data bus DB and address bus AB.
The operation of each part is almost the same as the writing and erasing operations to the main memory 11, and therefore the writing operation of the main memory 11 will be explained below.

When the light pen 4 is applied to the screen of the cathode ray tube, it detects raster light scanning the screen in a well-known manner and generates pulses. Therefore, the sensing output or pulse output from the light pen 4 is generated when the raster light passes within the field of view. As already mentioned, the main address counter 15 supplies the memory (1) X and Y address data to the (1) latch circuit 41, so it is supplied when it receives the detection output from the light pen 4. Latch the above address data.

This memory (1) X and Y address data indicates the horizontal and vertical positions of picture elements on the screen, so (1)
) The data latched by the latch circuit 41 is sent to the light pen 4.
This data indicates the location on the screen where the . (1)
The data latched by the latch circuit 41 is transferred to the bus buffer 43 (7) by sending memory address data specifying a storage address in 8-bit units of the corresponding main memory I river 1, and by writing data to the main memory 11 (3-8). Decoder 4
4 and then to the bus buffer 45 (6). The memory address data and write data are configured as follows.

First, as shown in FIG. 1A, the memory address data is composed of 8 dots out of a total of 256 dots in the X direction of the screen as one unit, which are sequentially associated with positions on the screen.
In other words, the memory address data consists of 5 bits indicating the address in 8-bit units in the X direction on the screen, and a total of 192 bits.
It is composed of 8 bits indicating which line among the lines. As described above, the write data to the main memory 11 is such that the memory (1)
The direction 192 dots are divided into 192 dot units (1
)Y address data circulates, so any data that determines which position among these 8 dots is sufficient is sufficient.

Therefore, (6) the write data to the main memory 11 that is supplied to the bus buffer 45 is data in which only 1 bit out of 8 bits is set to 1111). Therefore, (1) the above-mentioned memory (
1) Of the X and Y address data, the lower 3 bits of the X address data are converted by the 3/8 decoder 44 into 8 bit data corresponding to the 8 dots on the screen as described above, and (6) the data is supplied to the bus buffer 45. It is something to do. The (6) bus buffer 45 and (7) bus buffer 43 are opened by a command from the CPU 3, and the above-mentioned write data and block memory address data are loaded onto the data bus DB.

The command from the CPU 3 here consists of 16-bit parallel address data and is output to the address bus AB. For example, if (7) address data for selecting bus buffer 43 is output to address bus AB, this address data is transferred to (2) address decoder 32.
(7) bus bus 4 via track 431.
Let 3 open. (7) The timing of opening the bus buffer 43 is performed at the same time as the memory read timing indicated by RD. The CPU 3 (7) opens the bus buffer 43, takes in the memory address data carried on the data bus DB, and stores it in a predetermined built-in register. On the other hand, (6) the bus buffer 45 is also opened in the same manner as described above, and the CPU 3 takes in the write data on the data bus DB and stores it in a predetermined built-in register.

This operation of the CPU 3 is performed in sequence in a short period of time.
Based on this captured memory address data, the CPU 3 outputs memory address data representing the corresponding storage address of the main memory 1 to the address bus AB, and this data is transferred to the main memory 11 via the selector 14 (1) supplied to

At this time, the CPU 3 sends a memory write control signal indicated by WR indicating the write timing of the main memory 11 to the read/write terminal of the main memory 11 from the line 312 via the line 311 and (1) address decoder 31. and puts the memory into the write state. At the same time, (1) the address decoder 31 (1) opens the bus buffer 13 via the line 313, and the write data stored in the CPU 3 described above is supplied to the main memory 11 on the data buses DB and A. Writing to the main memory 11 is completed as described above, and instructions for writing and reading from this memory are executed by the CPU 3.

This command from the CPU 3 is executed during the blanking period so that refresh data and external write data do not collide on the data bus DB. If a color display device using a color cathode ray tube is used, the writing operation will be repeated three times for each of red, green, and blue. that's all,
Although the write operation of the main memory 11 has been described, the write operation of the sub memory 21 is similarly performed.

In this case, the light pen 4 is applied onto the screen of the first cathode ray tube 1 as described above. Therefore, (2) latch circuit 42, (5) bus buffer 46, 3/8 decoder 4
7. (4) The operations of the bus buffer 48 and CPU 3 are almost the same as in the case of the above-mentioned main memo January 1. That is, the memory address data consists of a 6-bit memory (2) indicating which line among 48 horizontal lines, a Y address data, and a 3-bit memory (2) indicating the memory storage address in 8-bit units in the X direction. The X address data is (2
) from the latch circuit 42 to (5) the bus buffer 46. On the other hand, as with the case of the main memory 11 already mentioned, the write data consists of 16 dots for 1 program and 2
Since the above-mentioned memory address data is circulated in units of divided 8 dots, it is sufficient to use data that determines which position among the 8 dots. Therefore, it is sufficient to configure the lower 3 bits of the output of the (2) latch circuit 42, which consists of 6 bits in total, as write data, and the remaining upper 3 bits as the above-mentioned memory (2) X address data. As a result, (2) the lower 3 bits of the output of the latch circuit 42 are converted by the 3/8 decoder 47 into 8-bit data corresponding to 8 dots on the screen, and (4) the data is supplied to the bus buffer 48. Next, the information drawn by writing on the screen of the second cathode ray tube 2 as described above is transferred to the first cathode ray tube 2.
The operation when transferring to the screen of the cathode ray tube 1 will be explained. In this case, as described above, the CPU 3 is given key inputs from the key switch 5 from sub 11 to main 11. The operation of the CPU 3 due to this key input is, as described above, that the detection output of the light pen 4 causes the main address counter 15 memory (1) 48 and (5) a program is set up to take in the address data and write data of the main memory 11 from the bus buffer 46. On the other hand, CPU3
is given in advance by regularly dividing the main memory address data into each predetermined block, and when a key input of "11 sub → main" is received, (5) it is fetched from the bus buffer 46 according to a predetermined routine set in advance. It calculates which block the memory address data belongs to and outputs it to the address bus AB as memory block address data.As a result, the main memory 11 is addressed in blocks at the corresponding storage address.
Therefore, 11 sub→main 11 key inputs are sent to the CPU.
3, and when the light pen 4 is placed on the screen of the first cathode ray tube 1, the main memory address data indicating the position in units of 8 bits (7) is fetched from the bus buffer 43 into the CPU 3 and stored.

Then, as described above, the CPU 3 successively transfers the data stored in the sub-memory 21 to the storage address of the main memo January 1 corresponding to the block to which the position indicated by the light pen belongs. At this time, the data in the submemory 21 to be transferred is written to the main memory 11 via the data bus Niro-DB-Iha. The operation of each part that controls the data transfer and the flow of address data as described above is performed by the CP.
It is executed by an instruction output from U3 to address bus AB.

This order of execution is determined by a routine preset in the CPU 3. The case where the image of the second cathode ray tube 2 is transferred to the first cathode ray tube 1 has been described above, but each part operates in the same way in the reverse case.

In this case, the key input is switched from 11 main to sub 11, and the light pen 4 is applied to the block to be transferred on the first cathode ray tube 1 in the same manner as described above. The key switch operation explained above is performed by the CPU.
It can be changed as appropriate by changing the routine set in 3.

Therefore, 11 main → sub 11. tI sub → main! Instead of 1 key switch, directly with 1 switch,
Even if a command is given to transfer data from the sub memory 21 to the main memory 11 or vice versa, this does not affect the spirit of the present invention. Although the present invention has been described above with reference to a black and white cathode ray tube display device, the present invention can also be applied to a color cathode ray tube display device.

In this case, the memory capacity may be tripled for red, green, and blue, and the same operation as described above may be performed for each of the three primary colors.

[Brief Description of the Drawings] Fig. 1 is a diagram showing a display format of an embodiment of the present invention, Fig. 2 is a configuration diagram of a device of an embodiment of the invention, and Fig. 3 is a diagram of an operation keyboard of an embodiment of the invention. It is a layout diagram. 1...First cathode ray tube, 2...Second cathode ray tube, 1, 10, 11, 12, 13, 14...
...First display means, 4, 41, 15, 43, 44, 45
, 5, 51, 52, 3, 31, 32... Extraction means, 2, 20, 21, 22, 23, 24... Second display means, 5, 51, 52, 4 ,42,46,47,
48, 16, 3, 31, 32...Writing and erasing means, 4, 41, 42, 43, 44, 45, 46, 47
,48,15,16,5,51,52,3,31,32
, 14, 24, 13, 23... transfer means.

Claims (1)

[Claims] 1. A scanning line is divided into a large number of picture elements, the brightness is controlled for each picture element, and images of characters, figures, etc. are created using a plurality of vertical and horizontal picture element matrices. A cathode ray tube display device that displays images on a screen, comprising: (1) a first cathode ray tube; and (2) the total number of picture elements included in a horizontally long display area of the first cathode ray tube screen by a certain appropriate number. a first display means for dividing the picture element blocks into a plurality of regular vertically elongated picture element blocks in which the number of picture elements is one unit, and displaying all information contained in all of these picture element blocks at once on the first cathode ray tube; and (3) the first
A second cathode ray tube in which raster scanning is performed in synchronization with raster scanning of the cathode ray tube; (5) extraction means for extracting information contained in a square display area obtained by combining a plurality of adjacent blocks from the first display means; and (5) all of the information obtained by this extraction means. a second cathode ray tube screen that displays the image as a square image on the second cathode ray tube screen;
(6) writing or erasing information displayed on the second cathode ray tube in units of picture elements, and providing this information to the second display means for display by the second cathode ray tube; writing/erasing means; (7) transferring the information displayed on the second cathode ray tube to the first display means and specifying any one block among the picture element blocks displayed on the first cathode ray tube; A cathode ray tube display device comprising a transfer means for inserting the specified block into a square display area formed by a plurality of blocks including the specified block.