JPS592910B2 - Image processing device using EL panel with memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a matrix-type binary image display device (halftone In a device that displays an image, a curve, a figure, etc. obtained by converting an image into a binary image at a certain threshold level), the first image is generated by adding 15 commonly used writing pulses and displaying it with a subsequent sustain pulse. A second image signal is then added without erasing the first image.

An image processing device that is capable of displaying the sum, difference, or common portion of the first image and the second image by devising a method of adding a write pulse or an erase pulse that corresponds to the second image signal at this time. It is. Generally, when an EL is used as a display element, a matrix type electrode arrangement as shown in FIG. 1 is adopted.

In Figure 1, 1 is a glass plate, 2 is a transparent electrode arranged in a striped pattern, 3 is a dielectric material such as Y203, 4 is a fluorescent layer such as ZnS doped with Mn, etc., and 3' is the same dielectric material as 3. , 5 are electrodes arranged perpendicular to 2. When an appropriate alternating current voltage is applied to one of the first electrode group 2 and one of the second electrode group 5 in an element having such a structure, only the intersecting portions of the electrodes emit light. This corresponds to one picture element on the screen. When a bipolar pulse as shown at 15 in Figure 2a is applied to one pixel of the matrix type EL element, the relationship between the average luminance B and the applied voltage Vp at that time is as shown by a curve in Figure 2b. Draw a closed loop.

When a pulse voltage as shown in Figure 2e is applied to an EL element with such characteristics, it initially emits light with a brightness of Bs during sustain pulse 4, and when a write pulse with an amplitude of Vw is applied, the brightness instantaneously increases to Bw/. The sustain pulse O that follows after emitting light at
It emits light with a brightness of Bw.

Next, when an erasing pulse O is applied, the luminance of the emitted light instantaneously becomes zero, and then a sustain pulse 8, which will be described later, emits light at a luminance of BE. A binary image processing method using an EL element having the above characteristics will be explained with reference to FIG.

Here, for the sake of simplicity, a (5×5) matrix type display device will be described as an example. Each picture element of the panel is Pll,
...゜゜゜゜゜゜P! 5, ゜゜゛゜゜゜゜゜, P5l
Number them like 5゜゜゛゜゛゜゜, P5$, etc. 2
The value image processing is performed on two images, the first image corresponding to the hatched areas in FIG. 3a, and the second image corresponding to the hatched areas in FIG. 3b.

White circles indicate locations where write pulses are applied, and black circles indicate locations where erase pulses are applied. Also, the triangle mark is 2
It shows the parts that emit light after processing the images. Image processing mode is sum (first image and second image)
(processing to add images), difference (processing to subtract the second image from the first image), and product (processing to depict the common part of the first image and the second image). The first image is written by a write pulse as shown in FIG. 3c, and thereafter continues to emit light by a sustain pulse. Writing the first image using a write pulse is common to each of the sum, difference, and product modes. In the sum mode, after the first image has been written and a sustain pulse has been applied, a second image is written by a write pulse as shown in FIG. 3d without applying an erase pulse.

A point indicated by a triangular mark Δ in FIG. 3e emits light from the subsequent sustain pulse rainbow. Since the writing pulse is applied twice to the common part P33-P34-P43-P44 between the first image and the second image, the luminance of the light emitted increases slightly and reaches the position BW2 in FIG. 4. A point to which a write pulse is applied only once emits light with a brightness of BWl. If the mode is set to sum, it is possible to combine two binarized images. In the difference mode, with a first image written and a sustain pulse applied, a second image is applied in correspondence with an erase pulse as shown in FIG. 3f. This erasing pulse erases the common parts P33, P34, P43, and P44 between the first image and the second image, and only the portion obtained by subtracting the second image from the first image is erased, as shown in Figure 3g. Is displayed. In product mode, with the first image written and sustain pulses applied, Figure 3h
As shown in FIG. 3, erasing pulses are applied to areas where there is no second image signal, that is, areas other than the hatched areas in FIG. 3b.

This erase pulse causes the common part P between the first image and the second image to
All light emitting points other than 337P34FP432P44 are erased. By using the difference and product modes, it is possible to depict moving objects and stationary objects.

For example, if Figure 5a is the first image and Figure 5b is the second image, and the difference mode is selected, only the cars in Figure 5a can be displayed, and if the product mode is selected, only the mountains in Figure 5a can be displayed. . FIG. 6 shows a block diagram of the structure of the image processing apparatus as described above.

6 is an imaging device such as a television camera, and 7 is a storage tube that stores one frame worth of video signal output from the imaging device 6. The signal stored here is synchronized with the display unit by a signal from a timing pulse generator 9. Picture elements are read out sequentially.

Reference numeral 10 denotes a circuit that applies or cuts off a read signal synchronized with the timing pulse to the storage tube, and after reading one frame worth of signals from the storage tube 7, the circuit is cut off.

8 is a signal processing circuit that converts the analog signal from the storage tube 7 into a digital signal that is binarized according to a threshold level.

11 is a sustain pulse generation circuit, and 12 is an erase pulse generation circuit.

Reference numeral 13 denotes a sum, difference, and subtraction mode switching circuit, and in the difference and product modes, the signal from the erase pulse generation circuit 12 is used.

14 is an electrode group Hl, H2,...Hrn-
1. This is a drive circuit for Hm.

A circuit 15 applies an erase pulse from the erase pulse generating circuit 12 to the gate circuit 16 when erasing the entire display image.

16 is a gate circuit that combines the signal from the mode switching circuit 13 and the signal from the erase pulse generation circuit 12.

17 is an electrode group Vl, 2...Vn-1, V
n drive circuit.

With this circuit, images of the sum, difference, and product of the signals from the imaging device 6 can be displayed on the EL display device. Figure 7 shows sum,
An example of a difference/product switching circuit, a sustain pulse generation circuit, and an erase pulse generation circuit is shown.

M1 to M3 are monostable multipipe radars (hereinafter, multivibrators are represented by M), S1 to S2 are shift registers (hereinafter, shift registers are represented by S), AND
l~AND2O is an AND gate (hereinafter, AND gate is A)
Represented by ND. ), 0R1 and 0R2 are OR gates (hereinafter the OR gate will be expressed as 0R), SW1 to SW3 are switches (hereinafter the switches will be expressed as 8V), and INl is the inverter (hereinafter the inverter will be expressed as IN). FIG. 8 shows output waveforms of each part, and FIG. 9 shows drive output waveforms and light emission waveforms. In Figure 8, Tn is V1
The period during which the electrodes are scanned, Th indicates the period during which the H1 electrode is scanned. The operation will be explained according to these figures. When performing binarized image processing, a first image and a second image are used to compare the two images, and the first image is normally processed using a write pulse.

First, the method for writing the first image will be explained. S in Figure 8
Wl is the image sum processing mode, Out is the difference processing mode, ? I is the product processing mode. When writing the first image, only SW1 is connected to the high potential side (hereinafter, the high potential side is indicated as "H"), and SW2 and SW3 are connected to the low potential side (hereinafter, the low potential side is indicated as "L"). A horizontal clock pulse (not shown) is input to the monostable multipipe radar M1, but at this time, the Q terminal of M1 is connected to the 5 in FIG. (The waveform shown in the figure is shown) is obtained. This output is also used as a clock pulse for shift register S2, which will be described later. An input indicated by 8 is applied to one terminal of AND3, and the Q terminal of M1 is Combined with the output 4
You will get the output shown in . This output is applied to the drive circuit to generate a sustain pulse (pulses θ of A, b, and c in FIG. 9 are generated). The input shown by 5 is added to one terminal of AND4, and the Q of monostable multipipe radar M1 is
It is combined with the output from the terminal to obtain the output shown at 4. This output is applied to the drive circuit to generate a sustaining pulse (generating pulses 8 in Fig. 9 A, b, and c).Furthermore, the 5 outputs are combined with the output of the Q terminal of the monostable multipipe radar M1 by ANDl, resulting in 5 outputs. get the output. 5 outputs are AND
2, it is combined with the output of the Q terminal of the monostable multipipe radar M1 to obtain an output of O.

These outputs are combined by AND5 and AND6, but at the time of writing the first image, field 1 is connected to the 1L1 side, and the AND, output is 8L1, and the outputs of AND and AND6 become L'. Binarized video signal (
Not shown.

) is input to the monostable multipipe radar M2.
At this time, an output as shown by 5 is obtained at the Q terminal of M2. Further, an output as shown in 1 is obtained at the Q terminal of M2. M
The output of the Q terminal of 2 is added to AND7 and AND8, but SW3 is currently connected to the 6L side, and A
The ND2O output is "L", and the AND7 and AND8 outputs are "L". AND, the Q terminal output 5 of M2
The output 1 of ANDl and the output of ANDl8 are added and combined, but since S is connected to the H side, the combined output has a waveform as shown in 6. This output is applied to 0R1, but the other two inputs of 0R1 are 0L1, and the output indicated by Ω is applied to one terminal of ANDl7. An input indicated by 4 is applied to the input terminal 12 of the shift register S2 from the timing pulse generation circuit 9 shown in FIG. Further, a waveform indicated by 4 is input to the clock pulse input terminal CL2 of S2. At this time, a waveform indicated by [F] is obtained at the first output terminal of S2, and a waveform indicated by 1 is obtained at the second terminal. [F] Output and 5 output are AN
Synthesized by Dl7. This output is applied to the drive circuit for the H1 electrode. The output of the drive circuit corresponds to pulse 5 in FIG. 9a. The inputs of 0R2 are both 0L'' when writing the first image, and the output of ANDl6 is also 5L''.

This output is independent of the sum mode. Further, when writing the first image, the output of ANDl8 (“H” at the time of writing the first image) and the output 4 of AND3 are applied to the ANDlO input terminal. This output is combined with the output of the first terminal Tll of the shift register S1 by ANDl5. An input of 4 is applied to the input terminal 1N1 of S1 from the timing pulse generation circuit 9 in FIG. Further, as a clock pulse, an output of 5 is applied from the Q terminal of M3. At this time, the first output terminal Tll of S1 has 5
An output as shown in is obtained, which is combined with the output of ANDlO at ANDl5 and applied to the V1 electrode drive circuit. The drive circuit output pulse corresponds to pulse 8 in FIG. 9a. Also A
In NDll, output 5 of ANDl is combined and further A
It is combined with shift register output 5 at NDl4 and applied to the V1 electrode drive circuit. The drive circuit output corresponds to pulse 7 in FIG. 9a. Also, the output of ANDl8 is added to ANDl3 through inverter 1N1, but N
The output of 0R2 is 6L, and the output of ANDl3 is 0L.When inputting the first image, the output of 0R2 is 0L0.
Therefore, the output of ANDl2 is 1L2'.
An output is obtained from ANDl2 and ANDl3 only in the difference or product mode. Although only the outputs applied to the V1 and H1 electrodes have been described above, the other electrodes can be considered in the same way. Through the above operations, a write pulse corresponding to the input signal of the first image is applied, and the light emission continues with the subsequent sustain pulse. Although only the output waveforms applied to the V1 and H1 electrodes have been described above, the other electrodes can be considered in the same way. The input method for the first image is sum, difference,
The same is true for each mode of the product. Next, a second image is added without erasing the first image. The method of processing the second image differs in sum, difference, and product modes. First is the sum mode, which is exactly the same as the method of inputting the first image.

If there is a common part between the first image and the second image, the writing pulse is applied again to that part, and the luminance of the light emission increases slightly. If the applied voltage as shown in FIG. 9a is again applied to the picture element (1, 1) during writing of the second image, writing will be performed by the write pulse 2 synthesized with 5, and thereafter the sustain pulse of amplitude s As a result, light emission continues with the brightness slightly increased compared to the state in which the first image was written. However, since we are considering a binarized image here, the slight difference in luminance is not important. Next is the difference mode, which is SW of the three switches.
2 is connected to the 6H side, and SW1 and SW3 are connected to the ``L'' side. At this time, the output of ANDl is 1H", which is combined with the output 5 of ANDl and the Q output 5 of M2 by AND5, and an output of [F] is obtained from the 0R, terminal. At this time, the other two inputs of 0R1 are 1L. ” and has no effect. - The [F] output is combined with the output 9 of the Tl2 terminal of S2 at ANDl7. The output of ANDl7 is applied to the H1 electrode drive circuit. The drive circuit output corresponds to pulse 4 in FIG. 9b. (P) Output is also ANDl3, Tl of S1
It is combined with the output 5 of the l terminal and the output of INl. IN
The output of l is 6H1 in difference mode, so AND
A combined output of 5 and [F] is generated at l3. This output is applied to V, the electrode drive circuit. The drive circuit output corresponds to pulse O in FIG. 9b. Also, an output of 9 is obtained at the AND6 terminal, which is added to 0R2. 6L1 is added to the other terminal of 0R2 in the difference mode, and 4 outputs are also obtained from 0R2.

The 9th output is combined with the Tl2 terminal output 9 of S2 by ANDl6, and is led to the H1 electrode drive circuit.

The drive circuit output corresponds to pulse 7 in FIG. 9b. Furthermore, the four outputs are combined by Tl of S1, terminal output 5, and ANDl2, and are led to V and the electrode drive circuit. The drive circuit output is the 9th
Corresponds to pulse 7 in figure b. Now, assuming that the second image is the same as the first image, the picture element (1,
1) will be deleted. 9 is an erase pulse of amplitude E, which is a combination of 4 and @.

@? Pulses such as , and J have small amplitudes and do not act as erase pulses. By the above operation, the common part between the first image and the second image is erased, and only the difference part between the first image and the second image remains. Next is the product mode, in this case 3
Among the switches, only SW3 is connected to 6H''.

At this time, the AND2O output becomes "H1", and this output becomes "A".
Added to ND7 and AND8. At this time, an output as shown at ω is obtained at the AND7 output terminal, and an output as shown at 4 is obtained at the AND8 output terminal. These outputs pass through 0R1 and 0R2 and are finally applied to the H1 and V1 drive circuits. AND, 2, ANDl3 makes S, output and AN again
(i) and 4 are combined with the S2 output by Dl6 and ANDl7, respectively, but this can be considered in the same way as in the difference mode. If the second image is the same as the first image, no erase pulse is applied to the picture element (1, 1), as can be seen from FIG. 9c. Pulses such as 0 and (2) are applied to the V and electrode during the scanning period, but even if they are applied to the picture element (1, 1) as N and α, the amplitude is VE/2 and does not act as an erase pulse. By the above operation, only the common portion of the first image and the second image is displayed. As mentioned above, in the sum mode it is possible to combine two images, in the difference mode it is possible to detect a moving object, and in the product mode it is possible to detect a stationary object, and this device can be applied to the field of image processing.

[Brief explanation of the drawing]

Figure 1A, b is a partially cutaway perspective view and cross-sectional view of an EL with a matrix structure, Figure 2A, b, and c are voltage application waveforms and E
Lf) B-characteristic diagram, Figure 3 shows the points where the erase pulse or write pulse is applied and the light emitting point in each mode of sum, difference, and product. Figure 4 is ELf) B-characteristic diagram, Figure 5.
The figure is a diagram of a binarized image applied to image processing.
The figure is a block diagram of a device capable of image processing in each mode of sum/difference and product. Figure 7 is a circuit for switching between sum, difference, and product modes. Figure 8 is a timing chart showing waveforms at various points in the mode switching circuit. , FIGS. 9A, 9B, and 9C are diagrams showing voltage application waveforms and light emission waveforms in each of the sum, difference, and product modes. 6...imaging device, 7...storage tube, 8.
... Signal processing circuit, 9 ... Timing pulse generator, 10゜゜゜ ... Cutoff circuit, 11 ...
. . . Sustain pulse generation circuit, 12 . . . Erasing pulse generation circuit, 13 . . . Mode switching circuit, 14.
17... Electrode drive circuit, 15... Full erase circuit, 16... Gate circuit.

Claims (1)

[Claims] 1 Matrix type that displays the sum, difference, and product of two first and second images using an electroluminescence display element that has a history characteristic between the pulse width, frequency, or amplitude of applied voltage and luminance. In the display device, the first
means for applying a write pulse to each pixel of the first image in response to an image input signal and displaying the first image with a subsequent sustain pulse; and means for switching and selecting the three display modes of sum, difference, and product. , when the sum mode is selected, a writing pulse is applied to each pixel of the second image according to the second image input signal, and means for adding the second image to the first image and displaying the sum; When the mode is selected, means for applying an erasing pulse to each pixel of the second image according to the second image input signal and subtracting the second image from the first image to display a difference; and when selecting the product mode; , means for applying an erasing pulse to each picture element without a second image in response to a second image input signal, extracting a common portion between the first image and the second image, and displaying the product. An image processing device using an EL panel with a characteristic memory.