JPS592924B2 - Sequencer input/output control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an input/output data transmission circuit for a programmable sequencer that sequentially controls a plurality of controlled devices.

Conventionally, as shown in Fig. 1, input data is taken in parallel from the respective input circuits INI...INn into shift registers SR1...SRn, which are capable of parallel input/output and left/right shifting, and stored in the sequencer main body SQ. These input data are serially transmitted to the memory section ME, and the program stored in the memory section ME performs arithmetic processing on these input data, and the results are stored in the memory section ME.These result data are used as output data to be sent to each shift register SR1... Serial transmission to SRn,
The signal was sent out in parallel to each output circuit OUT to control each controlled device DVI...DVn.

However, in the conventional circuit shown in FIG. 1, the shift register SR1...
- There is a drawback that there is no mechanism to detect an abnormality in the transmission circuit in the event that a defect occurs in one of the SRn or the transmission line is disconnected. However, the number of transmission locks must be manually changed each time, which is troublesome and is prone to erroneous operation. The present invention aims to solve the above problems. The present invention will be described with reference to the embodiment shown in FIG. 2. A sequencer main body SQ to which a plurality of controlled devices DVI...DVn are connected includes a storage section ME that stores programs, input/output data, check codes, etc.; An arithmetic unit AL that processes input data according to a program, a check code shift register CR, a comparison unit CM that determines the check code, a counter CN that counts transmission locks, and a control unit CT that controls these. has
Transmission shift register SR1 capable of serial input/output and parallel input/output provided in each controlled device DVI...DVn
... Connect SRn in series and connect the sequencer main body SQ.
from the storage unit ME to each transmission shift register SR1...
Pass through SRn, check code shift register CR
A data transmission loop is formed which returns to the storage unit ME via This counted number is used as the required number of clocks during input/output data transmission, and is also applied to the end of the input data string taken in from each transmission shift register SRl...SRn and to each transmission shift register SRl...SRn. This is an input/output control circuit for a sequencer that adds a check code to the beginning of an output data string to be sent.

Next, the operation of the circuit of the present invention shown in FIG. 2 will be explained.

When the power of the apparatus is turned on, the output data storage section of the memory section ME is cleared, and at the start of operation, empty output data transmission is first performed. First, control section C
All transmission shift registers SRl...SRn are cleared by clear signal a from T, and then a check code is sent out in synchronization with transmission lock b, followed by sequential output data. In this case, all data contents are O
It is. The contents of the check code shift register CR are constantly checked by the comparator CM, and when the check code is received, a check code reception signal c is sent from the comparator CM to the control unit CT, completing the transmission of output data. At this time, the counter CN counts the number of transmission locks so far and holds it for the next input transmission. When input data is taken in, first, the control unit CT sends a load signal d to each transmission shift register SRl...SRn, the input data is taken in from each input circuit 1N1...INn, and then the transfer registers are synchronized with the transmission lock. These input data are serially transmitted and sequentially written into the storage unit ME. At the same time, a check code is transmitted from the storage unit ME following the end of the input data string. At this time, the counter CT is
At the time of output data transmission, the transmission lock is counted down from the counted up value, and when it returns to 0, a transmission completion signal e is sent to the control unit CT, and the input data transmission is completed. At the same time, a check code reception signal c is also sent from the comparator CM, confirming that there is no abnormality in the transmission system. When these input data are calculated in the calculation unit AL according to the program and transmitted as output data from the storage unit ME, they are transmitted in synchronization with the clock with the check code at the beginning as described above. The transmission is completed by the received signal c, and is output to each output circuit 0UT1...0UTn, thereby controlling the controlled circuit DVl...DVn.
is controlled. The present invention is configured as described above, and since the occurrence of a failure in the data transmission system can be constantly monitored using the check code, it is possible to prevent trouble from occurring in the controlled device even if a failure occurs. Furthermore, even if the number of connected input/output devices changes or the number of transmission registers changes, the number of transmission locks is automatically changed, eliminating operational errors and preventing troubles.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a conventional example, and FIG. 2 is a schematic block diagram showing an embodiment of the circuit of the present invention.

Claims (1)

[Claims] 1 A sequencer body connected to multiple controlled devices includes a storage unit that stores programs, input/output data, check codes, etc., an arithmetic unit that processes input data according to the program, and a shift register for check codes. A transmission shifter capable of serial input/output and parallel input/output is provided in each controlled device, and has a comparison unit for determining the check code, a counter for counting the transmission clock, and a control unit for controlling these. The registers are connected in series to form a data transmission loop from the memory section of the sequencer main body, through each transmission shift register, through the check code shift register, and back to the memory section. After transmitting the check code, the check code shift register counts the number of transmission clocks until the check code is received, and uses this count as the required number of clocks when transmitting input/output data, and also A sequencer input/output control circuit that adds a check code to the end of the input data string to be taken in and to the beginning of the output data string to be sent to each transmission shift register.