JPS592998B2 - Denka Tensou Sochi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digital charge transfer device (hereinafter referred to as CCD).

) relates to refresh memory in memory. The two-phase drive digital CCD memory is Kurotsu 10.
The number of clocks is half that of the four-phase system, which is advantageous in terms of system configuration, but fat zero (bias charge) is absolutely necessary to improve transfer efficiency.

That is, it is required that the charge is held even when the clock is in the o state. If the 15 fat zeros were not used, it would be necessary to insert refresh circuits at very short intervals, and the degree of integration would not increase. Therefore,
This refresh circuit is used when a plurality of CCDs are connected. The 20-way refresh circuit has two methods: converting the transferred charge into a voltage change, detecting it, converting it to a predetermined voltage, and injecting the charge found at that voltage, and converting the transferred charge into a voltage change. There is a method of detecting the amount of charge, converting it to a predetermined amount of charge, and then injecting it.

Although the former method 25 requires a larger refresh circuit and has stricter restrictions on the power supply, it can easily supply zero fat. But with this method,
It is not possible to increase the density. In the latter case, the refresh circuit can be made smaller and the degree of integration can be increased by 30, but it is difficult to add fat zero, which will be described later.

The purpose of the present invention is to inject fat zeros in the latter manner. As an example of a method of detecting the transferred charge by voltage change, converting it into a predetermined amount of charge, and injecting it, 35
゛1974, IEEE, December
alofsolid-StateCircuits,,
VoLSC-9, /f6.6, PP, 436-442,
R. HoKrambeck, . TheOdOr
eF. Retajczyk,. JR. ,DOnaldJ
．． Silversmith,. R.O.BertJ. Sta
in. A4l6O-BitC4DSerialM
The circuit described in emOry (hereinafter referred to as Krambeck
There is a circuit called ``.

This circuit is a C4D refresh circuit, but it is
The case where it is applied to channel two-phase drive will be explained.

First, FIG. 1 shows the relationship between the gate potential, that is, the threshold voltage, with respect to the source potential in a CCD with a two-layer gate of polysilicon and aluminum.

In the figure, 1 is the characteristic of the polysilicon gate, and 2 is the characteristic of the aluminum gate. FIG. 2a shows the electrode structure of a two-phase drive CCD.

In the figure, 100 is an input diode, 101 is an aluminum electrode (gate), and 102 is a polysilicon electrode (gate) installed in an oxide film. For the transfer direction, aluminum electrode,
Aluminum electrode 101 and polysilicon electrode 102 are connected to form a polysilicon electrode, and one-phase and two-phase clocks are applied alternately. 10V voltage on terminal 3, 5V on terminal 4
The graph in FIG. 2b is a representation of the surface potential under each electrode when a voltage of is applied is converted into a source potential.
FIG. 3 shows the above-mentioned Krambeck circuit. FIG. 4 shows its driving clock. In FIG. 3, as in FIG. 2, 101 is an aluminum gate, 102 is a polysilicon gate, 5 and 6 are clock terminals, and 104 is an aluminum gate, which is used as an output gate.
10V is always applied to terminal 7. Further, 103 is an output diode which converts the charge transferred by this capacitance into a voltage. A capacitor 105 is for converting the applied voltage into charge, 106 is a reset transistor, 107 and 108 are MOS transistors, and 11 and 12 are power supplies. Reference numeral 13 in FIG. 4 is a first phase clock (hereinafter referred to as φ1), which is applied to the terminals 5 and 3 in FIG. FIG. 4 14 shows a second phase clock (hereinafter referred to as φ2), which is applied to terminals 6, 4, and 9 in FIG. Reference numeral 15 in FIG. 4 is a reset clock, which is applied to the gate 8 of the reset transistor 106 in FIG. The operation of the Krambeck circuit shown in FIG. 3 will be explained below. When 10V is applied to the gate 8 in FIG. 3, that is, in the reset state, the potential of the diode 103 is 7.6V from FIG.
becomes. Next, consider the case where when the clock 15 in FIG. 4 is at a low level, that is, 5V, φ2 becomes a high level and charges are sent to the output diode 103.

At this time, the change in surface potential under the polysilicon gate is
Expressed as a change in source potential, it is as follows. The maximum transfer charge amount Qmax is given by CT as the capacitance of the polysilicon gate.

This Qmax is applied to the capacitance of the output diode 103, causing a voltage change. When no charge was transferred, the potential of the output diode 103 was 7.6V, as described above. Assume that the potential of the output diode when it is transferred as Qmax is 5.85V. However, in reality, since the transfer efficiency is not 100%, the charge initially transferred through the CCDI is less than Qmax. It is assumed that the potential of the output diode 103 at this time is 6.55V. At this time, the gate potential of the transistor 107 is 7.5
V('0N, set the power supply 12('0 to 0FF at 16.55V)
What is necessary is to adjust the potential of VREF). transistor 10
If the threshold voltage of 7 is set to 6.9V, VREF becomes 5V from FIG. In this state, when the transistor 107 is ON, that is, when the output diode 103 is 7.6V, the potential of the node 200 is 5V.
The potential of the node 201 at this time is 6.9V since it is the gate voltage when the source potential is 5V, as shown in FIG. Since this is the timing at which charge is transferred to the output diode 103, φ2 is at a high level, and the node 9 of the capacitor 105 is at 10V. Next, φ1−=1
Consider the timing when the 0V high level φ2=5V low level.

At this time, since the node 9 of the capacitor 105 is connected to φ2, the voltage changes from 10V to 5V. Accordingly, the potential of the node 201 changes from 6.9V to 1.9V. At this time, since 3 is connected to φ1, 10
It is V. As shown in FIG. 2, the aluminum gate surface potential is 4.1 V when expressed as a source potential. That is, if the gate capacitance of the transistor 108, the capacitance of the capacitor 105, and the capacitance of the input diode 100 are collectively defined as CM, a charge of (4.1-1.9) CM is injected into the CCD.

On the other hand, since the maximum transfer charge across the CCDI was 3.5CT, if the gate capacitance CT and CM of the polysilicon gate were determined to be 3.5CT - 2.2CM, the maximum transfer charge to the CCD would be 3.5CT - 2.2CM. Amount of charge can be injected.

Next, consider the timing when φ,=5V1φ2=10V.

The potential of node 9 of capacitor 105 changes from 5V to 10V.
Since the potential of the node 201 increases by 5V from 4.1V to 9.1V. Node 200 at this time
From FIG. 1, the potential is 6.8V since it is the source potential when the gate potential is 9.1V. At this time, if charge is transferred to the output diode 103, the diode 1
The potential of 03 is below 6.9V, and the transistor 107 is 0
No N. If no charge is transferred to the diode 103, the above explanation will be repeated. In this state, that is, when charge is being transferred to the diode 103, when φ2 - 5V φ, = 10V, the voltage at node 9 of the capacitor 105 is 10V.
Since node 201 drops 5V from 5V to 5V, node 201 is 9.1V.
It is 4.1V, which is 5V lower than that.

At this time, since the surface potential of the aluminum gate is 4.1V, no charge is injected. At this time, the potential of the node 200 is 2.8V from FIG. At this time, when comparing the voltages across the transistor 108, 201 is 2.8V1
200 is 5V, the transistor 108 is connected between two poles, and the potential on the source side is higher, so it does not turn ON. As mentioned above, the potential at each point with respect to the voltage of each clock in Krambeck's circuit has been clarified.
: The state of the output diode 103 at each timing of the reset clock is set to 16, and the state of the node 201 is set to 1.
7, the state of node 200 is set to 18, and the state of node 201 is set to 9.
19 shows the change in potential with respect to .

The states shown in FIG. 5 will be explained in order.

First, (1) When the φ2 clock is at a high level of 10V and the output diode 103 is 6.55V (charge is being transferred), the potential of 201 is 9.1V in the section 301, as described above. , 200 is 6.8V. 2
The potential of 01 with respect to 9 is - since 9 is 10V.
It is 0.9V.

(2) In the section 302 where the φ2 clock becomes low level 5V and the reset clock is low level 5V, the φ2 clock changes from 10V to 5V, so nodes 200 and 201
They both find 5V and become 2.8V and 14.1V, respectively.

Therefore, the potential of 201 with respect to 9 remains at -0.9V. (3) During the period 303 from when the reset clock 15 is turned on until the φ2 clock goes high, the potential of the output diode is 7.6.
V, transistor 107 becomes 0N, and node 2
The level of 00 is 5V.

However, the level of node 201 is 4.1V, and for the reason described above, the level of node 201 is not changed and remains at 4.1V. Therefore, the potential for 9 of 201 also does not change. (4) Output diode 103
During the section 304 when the potential of the clock is 7.6V (that is, no charge is transferred) and the clock φ2 is at a high level of 10V, the signal charge is transferred from the CCD to the output diode when the clock φ2 becomes a high level. In this case, the signal is "0" and no charge is transferred.φ
When the 2 clock becomes high level, the potential of the node 201 becomes 9.1V, but at this time, the potential of the node 107 is 0N and the potential of the node 200 is 5V. Therefore, the transistor 108 turns ON, charge is accumulated in the capacitor 105, and the potential of the node 201 decreases to the gate potential of 6.9V, which is allowed when the source is 5V. Therefore, the potential of node 201 with respect to 9 is -3.1V. (5)
When the potential of the output diode 103 is 7.6V, the φ2 clock goes low, and the reset clock goes low during the section 305, when the φ2 clock goes low, the potential of the node 201 changes from 6.9V to 1. 9V
become.

At this time, the φ1 clock is at a high level, so the surface potential of the aluminum gate is 4.1V at the source potential, and 1
．． Since it is higher than 9V, charges are injected until the potential of node 201 reaches 4.1V. The potential of node 201 with respect to 9 becomes -0.9V again. The following is the same as the section 303, and when the charge is transferred to the output diode 103, the state is 301.

The Krambe & circuit has been described above.

However, with this method, if the transistor 107 turns off, fat zero cannot be injected. Therefore, at short intervals,
Since it has to be refreshed, the degree of integration cannot be increased. The present invention makes it possible to inject fat zero using such a method, and the configuration of the present invention is adapted to the sixth aspect.
As shown in the figure. The same numbers are used for the same parts as in the Krambeck circuit shown in FIG. 3, and the explanation thereof will be omitted. A feature of the present invention is that a diode junction transistor 109 is newly connected to a node 200 in parallel with the transistor 107, and its source is connected to a power supply 20 (VREF') for fat zero injection. From the operation of Krambeck's circuit described above, the charge injected into the CCD changes as φ
The second clock is at a high level of 10V, and the output diode has a potential of 6.9V or more, that is, when no charge is transferred. Therefore, the present invention provides a transistor 1
When 07 is 0FF, fat zero is injected from the power supply 20. As the driving clock, the same clock as shown in FIG. 4 is used. The power source 20 is set to 4.5V. Now, consider a state in which the transistor 107 is 0FF. At this time, the potential of the node 200 is 6.3V from FIG.
The potential of node 201 is 8.5V from FIG. Since the φ2 clock is at high level when the transistor 107 is 0FF, the potential of the node 9 is 10V. Next, φ1
Consider the case when the clock is at a high level and the φ2 clock becomes a low level. Since node 9 becomes 5V, the potential of node 201 becomes 3.5V, and at this time, since the surface potential of the aluminum gate of node 3 is 4.1V, charge is injected from capacitor 105 to CCD, The potential of the node 201 increases from 3.5V to 4.1V. That is, at this time, fat zero is injected. At this time, the potential change of the node 201 is 0.6V, and at the maximum transfer charge amount, it is 2.2V. Therefore, approximately 28% of fat zero will be injected. Next, the charge injection process based on clock timing will be explained.

Since the injection of signal "11", that is, the injection of the maximum transfer charge amount, is the same as in the case of Krambeck's circuit,
The injection process for Fat Zero will be explained. In Figure 7,
The potential of each node with respect to the clock is shown. 13 is φ1
14 is a φ2 clock, 15 is a reset clock, and 21 is the potential of the output diode.

Unlike the Krambeck case, since a fat zero is transferred, the potential of the output diode is at the reset level of 7.6V after being reset until the charge is transferred, but becomes 7.1V due to the fat zero. 22 is the potential of node 201 in FIG. 6, and 23 is the potential of node 6
In the figure, the potential is 200.

24 is the potential of node 201 with respect to 9.

The timing will be explained in order. (1) The period 306 from when the φ2 clock is at a low level and the reset clock is turned on until φ2 goes to a high level will be explained with reference to FIGS. 7 and 6.

The potential of node 201 is 4.1V. Node 200 is at 6.3V since transistor 108 is ON. Since 9 is 5V, the potential of node 201 with respect to 9 is -0.9V.

(2) In the section 307 when the φ2 clock becomes high level, node 9 becomes 10V, so node 201 becomes 9.1V.
It becomes V. Here, since the voltage at the node 200 is 6.3V, the potential at the node 201 can reach up to 8.5V. Therefore, charge is injected into capacitor 105 until node 201 goes from 9.1V to 8.5V. Node 201 9
The potential for the node 201 was -0.9V, but since 9 is 10V and the node 201 is 8.5V, it becomes -1.5V. (3) During the section 308 where the φ2 clock is at a low level and the φ1 clock is at a high level, the φ2 clock is at a low level, so the potential of the node 201 becomes 3.5.

At this time, since the φ1 clock is at a high level, the surface potential of the aluminum gate 3 is 4.1V, and charges are injected into the CCD until the potential of the node 201 changes from 3.5V to 4.1V. The potential of node 200 is 6.3V, but when the reset clock is applied, transistor 107 becomes ON and becomes 5V. However, at this time, the potential of node 201 is 4.1V, and the potential of node 201 does not change. As described above, according to the refresh circuit of the present invention, it is possible to inject a fat zero, and in a digital CCD memory, the interval between inserting the refresh circuit can be lengthened, and the degree of integration can be further increased. .

Also, in this embodiment, three power supplies were used, but this was done by changing the threshold voltages of transistors 106, 107, and 109.
It is also possible to use only one power source).

Furthermore, although the present invention has been described with respect to an N-channel CCD, the case of a P-channel can also be treated in the same manner.

[Brief explanation of the drawing]

Figure 1 is a diagram of the relationship between the source potential and gate voltage of polysilicon gates and aluminum gates in a CCD, and Figure 2a is a diagram of the relationship between the gate voltage and the polysilicon gate.
Figure 4 is a diagram of the structure of the main parts of the CD, Figure 4 is a diagram of the surface potential under each gate when a clock voltage is applied to the polysilicon gate and aluminum gate, Figure 3 is the configuration diagram of the conventional (Krambeek) refresh circuit, Figure 4 is FIG. 3 is a drive clock waveform diagram, FIG. 5 is a diagram of potential changes at each node with respect to the clock waveform in FIG. 3, FIG. 6 is a refresh circuit diagram of an embodiment of the present invention, and FIG. FIG. 2 is a diagram showing changes in potential at each node with respect to a clock waveform of the refresh circuit of FIG. 1,...CCD, 3,4,5,6,7...
...Clock terminal, 9...Capacitor terminal, 1
00... Input diode, 101, 102...
...Aluminum, polyzircon gate, 103...
...output diode, 105...capacitor,
106,107'108?109...MOS transistor.

Claims (1)

[Claims] 1 The first MO is connected to the output diode of the first charge transfer element.
The drain of the S transistor is connected to the first MOS
The source of the transistor is connected to a reset power supply, the gate of the first MOS transistor is connected to a reset clock, and the gate, source, and drain of the second MOS transistor are connected to the output diode of the charge transfer element, the second A power supply for determining the threshold voltage of the MOS transistor is connected to the source of the third MOS transistor, the gate of the third MOS transistor is connected to its drain, and the drain of the third MOS transistor is connected to the second MOS transistor.
connected to the input diode of the charge transfer element, and further connected to the input diode of the fourth charge transfer element.
The gate and drain of the fourth MOS transistor are connected, and the drain of the fourth MOS transistor is connected to the second MOS transistor.
connected to the drain of the OS transistor, and connected to the fourth MO
Connect the source of the S transistor to the power supply for bias charge supply, connect one end of the capacitor to the drain of the third transistor, connect it to the input diode of the next stage CCD, and connect the other end to the drive clock. A charge transfer device characterized by: 5