JPS5930294B2 - Information transfer control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a common bus control device for connecting a plurality of computers and the like to perform cooperative operations, and particularly relates to a small-scale system such as a microcomputer.

Conventionally, there has been a device of this type as shown in FIG.

In FIG. 1, 1a, Ib, and Ic are computers, 2 is a bus master that controls the common bus, 3 to 5 are REQ signals that request use of the common bus, and 6 to 8 are ACK signals that permit use of the common bus. 9 is a common bus line for the computers 1a to 1c to exchange information. Next, the operation will be explained.

When transmitting information via the common bus 9, only one computer must take initiative in using the common bus 9. That is, there may be two or more devices on the signal receiving side, but if there is only one device on the transmitting side, the signals will overlap and cannot be used. Therefore, as shown in Figure 1, when three computers request the use of the common bus 9 at the same time, it is necessary to determine the order in which the common bus 9 is used among the three computers, and each computer 1 to 3 REQ signals 3 to 5 are sent individually to the bus master 2. The bus master 2 sends an ACK signal (6 to 8
). The computer that has received the ACK signal uses the common bus 9 to exchange data with other computers. This conventional device required synchronization between computers that exchanged data.

In addition, in such a conventional device, REQ signal lines 3 to 5,
It has the disadvantage that the number of ACK signal lines 6 to 8 increases in proportion to the number of computers, and the circuit that determines the priority for simultaneous requests must be determined according to the purpose of use of the computer, so it can be applied in any case. The drawback was that it was extremely complex to make it as flexible as possible.

Furthermore, even if there is no need to prioritize, it is necessary to prioritize as a countermeasure against simultaneous requests.

In order to eliminate the above-mentioned drawbacks, this invention uses a simple bus master that does not increase the number of REQ and ACK signal lines in proportion to the number of computers and can be used even when there is no need to prioritize. The present invention provides an information transfer control device that does not require synchronization between computers.

A control device that is part of the present invention and that saves the number of REQ signal lines and ACK signal lines and determines priority among computers will be described below.

FIG. 2 is a diagram showing the overall configuration of the common bus control device. In the figure, 10a, 10b, 10c, and 10d are computers that can exchange data through the common bus 9, and bus use requests from each computer The common bus line is controlled by the bus master 11, which accepts and gives permission to use the bus, and its control lines 12, 13, and 14. FIG. 3 is a diagram for explaining the operation of the bus master on the common bus line, and shows the interface between the bus master 11 and one computer, that is, the bus master of the computer 10c in FIG. 2 in the figure.

The bus master 11 has the output of the clock generator 15 AND
It is connected to the clock input of a counter 17 through a gate 16, and the output of the counter 17 becomes control lines 13 and 14, that is, TSI and TSO, and enters the bus interface of each computer. Therefore, the control lines 13 and 14 are the counter 17
While the clock is on, the cycle is ``11,'' 0.
Repeating I. The AND gate 16 receives a busy signal (B) from each computer indicating that the common bus 19 is in use.
SY), 12 is a gate that prohibits the output of the clock generator 15 from entering the counter 17. 18a,
18b is an exclusive 0R gate, 19 is an AND gate, and these three gates convert the TSI and TSO signals into predetermined signals (
This circuit detects when the common bus use request signal (REQ) 22 reaches /'1 using its output signal 20 as a trigger, and sets the recognition flip-flop (ACKF/F) 21. .

A signal 23 generated when the use of the common bus is finished is connected to the ACKF/F reset terminal, and its output negative signal is connected to the BSY signal 12. FIG. 4 is a block diagram showing an example of the main parts of an information transfer device according to the present invention, which transfers data without synchronization between computers using the common bus control device shown in FIG.

This is an example in which data is requested from the computer 10c to the computer 10b, and 25 is similar to the one shown in FIG. Address signal 3 indicating address
2 is connected to the common bus 28 through the gate 31. This address signal 32 is input to a decoder 35 in the computer 10b, which detects that the computer is its own computer, and outputs data 38 according to its contents to the common signal bus 29 through a gate 36. On the other hand, the gate 37 has data 38
The contents of TSI and TSO are returned to the computer 10c as a CDR signal in response to the READY signal 39 indicating that the data is ready and the output of the decoder 35. CD in computer 10c
The decoder 30 of the R signal detects that it is the own unit number, and the signal is connected to the gate 23 in order to input the contents of the data signal bus 29 into the computer. Fifth
The figure is a diagram showing waveforms of each part.

(0SC), (TSI), (TSO), (REQ), (
GATE) and (CMP) are shown in FIG. 15,1 each
4, 13, 22, 24, 23 signals, (ADD)
, (DATA), (CDR) are 28, 29 shown in Figure 4.
, 27 signals. FIG. 6 shows an embodiment in which the bus master is made redundant, and in addition to the 0SC15 shown in FIG. 3, there is a spare 0SC40.

These two clocks are connected to AND gates 41, 42, 0R.
Pass through gate 43 and enter game gate 6.

The 0R gate 43 outputs an output clock if either the gate 41 or 42 outputs an output.

Clock oscillator 0SCI15 is clock stop detection circuit 4
4 is constantly monitored, and gates 41 and 42 are switched by its output. Gate 16 is the same as the gate shown in FIG. 3, and its outputs are 17a, 17b, 17
The outputs input to the three counters of c are outputted to the bus line as TSI and TSOl using a 2/3 selection circuit for each output bit of each counter. Next, the function and operation of the control device shown in FIGS. 2 to 6 will be explained.

In general, common bus control devices can be broadly divided into two problems: competition for requests to use the common bus, and problems regarding data exchange methods. That is, in FIG. 2, 10a~
What to do when four computers in 10d issue requests to use the common bus at the same time, and how to transfer the desired data after the computer in 10a acquires the right to use the common bus. The question is whether First, the former will be explained with reference to FIG. To make the explanation easier to understand, the number of computers connected to the common bus is limited to four, and each computer is assigned a unit number of #0 to #3.Now, from all of the computers 10a to 10b, If there is no request to use the bus, the BSY control signal of the BSY Kōkyō line 12 is "1", so the game gate 6
The output of the clock generator is directly input to the counter 17.The counter 17 can use a 2-bit binary counter that can count from 0 to 3 at the minimum.Of the output of the counter, 2 bits are TSO and 2l bits are TSI. If connected to T8l and TSO, steps 0 to 3 will be repeated cyclically.

If the unit number of the computer 10c is 2, TSI=″1
'', when TSO=IOI, the signal 20 becomes ``11'' and RE
If the Q signal 22 is "11", ACK is received at the rising edge of the signal 20.
Set F/F2l.

If there is no REQ signal 22, ACKF/F2l will not be set, and TSI and TSO will become TSI = 1, T on the next clock.
S0=1, and the signal 20 becomes IO''.At this time, even if the REQ signal 22 comes, the ACKF/F is set.If the REQ signal is present and the ACKF/F is set, the BS
Since the Y control signal becomes "11" and the bus master gate 16 is closed, the counter remains at its current state.

In other words, since it stops with the TSI and TSO signal states when REQ is detected, the ACKF/F of other unit numbers
becomes impossible to set. Therefore, the fact that ACKF/F is set means that the own computer can use the common bus.

The computer 10c outputs a CMP signal 2 when it finishes using the bus.
3 and resets ACKF/F.

As a result, the gate 16 is opened, the counter 17 starts operating, and a signal is applied to the trigger terminal of the ACKF/F cyclically to unit numbers #3, #0, #1, and #2. FIG. 4 shows an example of data exchange using a common bus, using the bus master interface circuit 25 shown in FIG.

The bus master interface circuit 25 is connected to the three buses TSI, TSO, and BSY as a common bus, and as mentioned above, the computer 10c can obtain the right to use the bus, and the GATE signal 24 at that time allows the computer 10c to obtain the right to use the bus. The side address signal 32 is passed through the gate 31 to the address bus ADD28.
Output to. Usually, there are a plurality of address signal lines, each of which is composed of a unit number connected to the common bus DATA 29 and a data address within the other unit. If an address signal is now being sent from computer 10c to computer 10b, the decoder 35 of computer 10c decodes the unit number and data address and outputs the necessary data 38 to the common bus DATA 29, and the data 38 is ready. At that point, the READY signal 39 is generated and the current TS
The contents of the I, TSO 26 are sent back to the computer 10c as a return line CDR signal 27. In this way, the computer 10b
can be operated without synchronizing with the computer 10c. The CDR signal 27 is received by the computer 10c and sent to the decoder 30.
By decoding it with , it can be detected that it is the same as its own unit number, and it can be seen that there has been a response to its own transfer command. That is, the common bus line D
Know that the data commanded to ATA29 is being output. Therefore, the data 34 can be obtained by using the output signal of the decoder 30 as a trigger to open the gate 33. After storing the data 34 in the computer 10c, a CMP signal is generated to complete the use of the common bus 29, and the ACKF/F of the bus master interface circuit is reset.
Transfer the common bus 29 to another unit. Even if you wish to continue using the common bus, you will need to wait until TSI and TSO become your own unit number again. Such a control device is effective in slow-speed computers such as microcomputers because other machine cycles such as memory access are much longer than the dedicated time of the common bus actually used. Further, since the frequency of 0SC15 is usually about 100 KHz to 1 MHz, it is thought that there is almost no effect even if the detection is completed once as described above. FIG. 5 shows a time chart of the above operation.

Figure 6 shows an example in which a redundant circuit is made possible by simplifying the bus master. In this circuit, 0SC15 and counter 17
is made redundant. In the same figure, clock stop detection circuit 4
4, the oscillation of the 0SC115 is stopped, and while the 0SC115 is oscillating, the inverter 45 opens the gate 41 and closes the gate 42. If 0SC115
When the oscillation of 0SC240 stops, the stop detection circuit 44 operates, and the gate 41 closes and the gate 42 opens.
oscillation is output. Counters 17a, 17b, 17
If c is a simple binary counter, 3 choices 2 circuits 4
6 makes it easy to create a highly reliable counter. However, the counters 17a, 17b, and 17c must include a circuit that synchronizes at a certain count value, but the method for doing so is not the purpose of the present invention and will therefore be omitted here. In addition, in the above embodiment, TSI,
The TSO had two control lines 13 and 14, but by increasing the number of bits of the counter 17 to two or more, the maximum number of computers that can be connected to the common signal line is 2n (n = TSO, TS
number of I...).

Also, in FIG. 4, the CDR signal 27 is TSO, TSI 26
The contents of are used by the gate 37, but the same effect can be obtained by sending a special signal line from the computer 10c to the computer 10b at the same time as outputting the address signal separately and using the contents instead of TS and TSO. It is possible. Furthermore, although FIG. 6 shows the oscillator 15 and counter 17 made redundant, it is natural that each circuit including the gate circuit 16 can be made redundant. The counter 17 is not limited to a binary counter, and may be any means that can achieve the same effect.

In the above explanation, each unit releases the counter 17 by releasing the AND gate 16 when the use of the common bus is completed.
If the counter is reset at the falling edge of the BSY signal 12, the counter will start again from the initial value. In this way, the initial value (normal output is 00) will always have the highest priority in bus contention, and the unit whose unit number is the highest value in the counter output will have the lowest priority, and the unit of the prioritized common bus will have the highest priority. You can do the legs. The control device shown in FIGS. 2 and 3, which is a part of the present invention, has the following effects.

(1) In a method using a bus master, the number of devices connected to a common bus is 2, where n is the number of lines connecting the bus master and each computer (the number of TSIs and TSOs in the above example).
It is possible to use up to n units, and the number of wires can be reduced.

For example, if n=4, up to 16 devices are possible. (2) Since it can be configured with a simple bus master and interface, the reliability of the common bus can be improved.

(3) Since the bus master is simple, a redundant circuit can be provided, making it even more reliable.

The following effects can be obtained by the configuration shown in FIG. 4, which is the main part of this invention. The computer that receives commands during data transfer is RE
Since the CDR signal is sent back using the ADY signal, transfer is possible even if the computers are not essentially synchronized with each other.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional control device;
FIG. 3 is a diagram showing a partial configuration of the control device of the present invention,
FIG. 4 is a diagram showing an example of the main configuration of the information transfer device according to the present invention, FIG. 5 is a waveform explanatory diagram of FIG. 4, and FIG. 6 is an example in which the bus master is made redundant. In the figure, 9 and 10 are common bus lines, 10a, 10b, 1
0c, 10d are calculators, 12 is a busy line, 13, 14,
26 is a control line, 15 is an oscillator, 16 is a gate circuit, 17
, 17a, 17b, and 17c are counters, 21 is a recognition circuit such as a recognition flip-flop, 22 is a common bus use request signal, 25 is a computer bus master interface circuit, 27 is a return line, 28 is an address signal line, and 32 is an address. signal, 33 is a gate that reads data from the common bus;
35 is a decoder, 36 is a gate that outputs data to a common bus line, and 37 is a gate that outputs a count value to a return line.

Claims (1)

[Claims] 1. In a device that controls the transfer of information between multiple computers, a common bus that is commonly connected to the multiple computers and serves as a path for information transmission, a counter that cyclically outputs output bits, and a counter that cyclically outputs the output bits of this counter. A control line for deriving the contents of the output, a detection circuit provided in each of the above-mentioned computers to read the count value derived from the control line and outputting it when the count value reaches a predetermined value, the output of this detection circuit and the above-mentioned detection. A recognition circuit that outputs when there is a use request signal for the common bus line from the computer in which the circuit is installed, a gate circuit that stops the counting of the counter by the output of this recognition circuit, and a gate circuit that causes the counter to stop counting when the recognition circuit outputs A circuit that outputs an address signal specifying a computer to an address signal line commonly connected to each computer, a decoder that reads the address signal of the address signal line and generates an output when the address signal is its own address, this decoder. A circuit that outputs data from its own computer to the common bus line when the decoder outputs the data, a circuit that outputs the counted value of the control line to the return line commonly connected to each computer when the decoder outputs the signal, and a signal of the return line. is a predetermined value, the circuit reads the data on the common bus line, controls the common bus line to compete for usage rights, and sends the count value on the control line as a return signal during data transfer to a return line common to each computer. An information transfer control device characterized in that the information can be sent back to the computer and transferred asynchronously between computers.