JPS5930312B2 - Address control circuit in direct data transfer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address control circuit for direct data transfer that facilitates processing of data stored in a memory.

Conventional direct data transfer (DirectMemoryAc
cess) (hereinafter referred to as DMA), as shown in Figure 1, the start address (ADRS) of the memory to be transferred and the number of memories (N) to be transferred are specified, and one data is transferred to the memory. Each time, the address is incremented or decremented by one and N pieces of data are transferred to the memory.

However, in an information processing system that performs pattern recognition such as character recognition, the black and white state of a pattern such as the character A shown in FIG.
, D31, D41, D51, . . . , the entire surface is scanned by moving in the horizontal direction while scanning in the vertical direction.

When the detected data is directly transferred to memory, in conventional direct data transfer, the data is stored in the memory in the order of occurrence as shown in Figure 3, and the relationship between the position on the data pattern and the memory address is Although there is a one-to-one correspondence, it is not a simple correspondence, so it is often inconvenient when you want to check whether data has been processed or not.
The present invention takes the above points into consideration, and provides an address control circuit for data transfer immediately after the relationship between the position of the data on the pattern and the address where the data is stored is convenient for subsequent data processing. Filled with things to offer,
Next, this invention will be explained in detail with reference to the drawings from FIG. 4 showing one embodiment thereof. In FIGS. 4 and 5, 1 is a comparator that converts a video signal a obtained by vertically scanning the black and white level of a pattern into a 20 digital signal, and 2 is a comparator that pulse-shapes the digital signal to generate a signal a'.
3 and 4 convert the serial signal a' into a parallel binary 16-bit data signal M.

..., shift register storing as M15, 56,
T is a one-shot monomulti for inputting the clock pulse to the first AND gate 8, 9 is a sample pulse c
10 is a second AND gate that passes the line start pulse e in accordance with the output of the first flip-flop 9; 11 is a second AND gate 10;
The second flip-flop 12 is set by the output of the line end pulse d and reset by the line end pulse d. A carry signal f is output every time a certain number of times are counted, and a memory write start signal g is output via the one-shot monomulti 13. Note that the clock pulse b that has passed through the first AND gate 8 is also input to the shift registers 3 and 4. Also, in FIG. 6, 14, 15, 16, 17 are DMA start pulses h
The address one address before the transfer start address (ADRS) is preset by the sample pulse c, and the horizontal counter counts the horizontal position of the bit pattern.The data is a binary 16-bit H
.

,...,H,5. 18 is cleared by sample pulse c and memory cycle end pulse i
Vertical counters 19, 20, 21 that count up the bit pattern in the vertical direction
is a sample counter to which the number N+1 of sample positions in the horizontal direction is preset by the DMA start pulse h, and is counted down by the sample pulse c.

22 is a one-shot monomulti which is driven by the signal j from the sample counters 19, 20, and 21 and outputs the DMA end pulse k; 23 is a constant multiplier that multiplies the output A of the vertical counter 18 by N times, that is, 16 times. circuit, 24, 25
, 26, and 27 are adders that add the output AN of the constant multiplier circuit 23 and the outputs B of the horizontal counters 14, 15, 16, and 17, and output the addition result AN+B, and the output is a binary 16 Bit A.

,...,Al,. Further, in the circuit described above, the address, data, and control of the memory 5 are set in a direct transfer mode, and data writing is performed only at necessary times.

Next, the operation of the above embodiment will be explained.

First, when a DMA start pulse h is generated, the horizontal counters 14, . Number N
+1 is preset. Considering the case where a linear sensor (not shown) scans the line L at the l-th sample position from the left of the pattern in FIG. The black and white levels at corresponding positions on the horizontal line L are detected in sequence, and a video signal a is output. This video signal a is converted into a digital signal by a comparator 1, and is pulse-shaped by a one-shot monomulti 2.
The black level of the video is "607" and the white level is input to the shift registers 3 and 4 as a digital signal a'.The sample pulse c, which indicates that the linear sensor has come to the line L, is sent to the first flip-flop. 9 is set, the second AND gate 10 is opened, and the line start pulse e passes through the gate 10 and is output to the second flip-flop 1.
1 and opens the first AND gate 8.

And clock pulse b is one shot mono multi 11
, 12 for a certain time, passes through the first AND gate 8, and is input to the shift registers 3 and 4, and converts the serial digital signal a' into parallel data M.

,..., convert to Ml5. This clock pulse b is counted by a counter 12, and a carry signal f is output every time 16 clock pulses are counted.
A memory write pulse g is output through 3. On the other hand, when the sample pulse c generated at the start of sampling is on the first line, the horizontal counters 14, 15, 16, 17 are moved from the preset transfer start address (ADRS) - 1 to the transfer start address. (A.D.
RS), and when the sample position is on the second line L, the horizontal counters 14, 15,
16 and 17 are counted up from address ADRS+2-1 to address ADRS+l.

Further, the sample pulse b clears the vertical counter 18 (A=0) and counts down the sample counters 19, 20, and 21.

Therefore, when the linear sensor samples on the line L, the output of the adders 24, . . . , 27 is initially AN
+B=ADRS+! -1, and shift registers 3 and 5
Parallel signal MO of data D2l inputted to 4,
. . , Ml5 is set to bit A of memory 5 at the same time as the memory write pulse g is generated. , . . . is written to address ADRS+'-1 indicated by Al5. When this writing is completed, the memory 5 generates a memory cycle end pulse i, which causes the vertical counter 18 to count up and the sample counter 1 to count up.
Count down 9, 20, 21. When the vertical counter 18 is counted up, the adders 24, . . . 2
The output of 7 is AN+B=N+ADRS+2-1, and the next generated data D2l is written at this address, and similarly data D3l, 3N+A is written at address 2N+ADRS+2-1.
Data D4l is written to address DRS+2-1.

When the sample on line L is finished, the linear sensor is scanned in the horizontal direction, and when the next sample position is reached, the sample pulse c counts up the horizontal counters 14,..., 17, and the sample counters 19,... , 21, and repeat the same operation as above.

Then, when the linear sensor finishes scanning at the rightmost sample position, the contents of the sample counters 19, 20, and 21 become O, generating a boro-1 signal j, and a DMA end pulse k via the one-shot monomulti 22. Output.

When direct data transfer is performed as described above, the data transferred to the memory 5 is arranged in horizontal patterns Dil, Di2, . . . , Dil6 in succession as shown in FIG. Moreover, it has become extremely convenient for data processing and data checking.

In the above embodiment, the number of data generated at one sample position is four, but this number is not limited, and it goes without saying that any number can be used. Next, the configuration of the constant multiplier circuit 23 will be explained.

In the case where the sample position N=16 and n is represented by N=2 as in the above embodiment, the constant multiplier circuit 23 can be constructed by simply shifting each bit of the vertical counter 18 by n bits to the left. However, if N is, for example, 50, the circuit configuration must be as shown in FIG.

That is, in the figure, 28 is a first adder which takes the fourth bit output R of the vertical counter 18 as an input X1, uses the input X1 as it is as the first bit output Z1, and outputs the second to fourth outputs Z2, Z3 and Z4 are O.

Further, reference numeral 29 uses the first to fourth bit outputs 0, P, Q, R of the vertical counter 18 as one of the first to fourth bit inputs Xl, X2, X3, X4, and the fourth pit output R of the counter 18. is the other first bit output Yl, and the first to third bit outputs '0, P, Q are the second to fourth bit inputs Y2, Y3, Y4. As bit output Zl,...,Z4,
The first adder 28 and the second adder 29 are interconnected to perform a carry.

The first bit output C1 of the constant multiplier circuit 23 is O, and the first to third bit outputs of the vertical counter 18 are 0, P,
Q is the second to fourth bit output C2 of the constant multiplier circuit 23,
C3, C4, the first to fourth bit outputs Zl, Z2, Z3, Z4 of the second adder 29 are the fifth to eighth bit outputs C5, C6, C7, C, of the constant multiplier circuit 23, the first adder 2
The first to fourth outputs Zl, Z2, Z3, Z4 of 8 are the 9th to 12th bit outputs C, , ClO of constant multiplier circuit 28
, Cll, Cl2.

With this circuit configuration, as shown in FIG. 2B, twice, twice, and twice the output of the vertical counter 18 are added, resulting in an output that is 2+2+2=50 times the output.

As described above, according to the address control method for direct data transfer of the present invention, a horizontal counter, a vertical counter, a constant multiplier, and an adder are provided, and by controlling the address to be transferred to memory, data processing, Data can be stored in memory in an arrangement convenient for data checking, and the present invention exhibits a very remarkable effect.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the state in which N pieces of data have been transferred to memory by conventional direct data transfer, Figure 2 is a diagram showing the data position when character A is scanned by a linear sensor, and Figure 3 is a diagram showing the data position when character A is scanned by a linear sensor. A diagram showing the data storage state of the memory when the data shown in the figure is transferred by conventional direct data transfer, Figure 4 is a block circuit diagram of direct data transfer, and Figure 5 is a diagram showing the state of data stored in memory when the data is transferred using conventional direct data transfer. FIG. 6 is a block circuit diagram of one embodiment of the address control circuit for direct data transfer of the present invention, and FIG. 7 is a linear sensor sample to explain the operation of the circuit in FIG. 6. A diagram showing the position, Figure 8 is a waveform diagram of each part of the circuit in Figure 4,
FIG. 9 is a diagram showing the data storage state of the memory when direct data transfer is performed using the circuit of the above embodiment;
0A is a block circuit diagram of one embodiment of the constant multiplier circuit, and FIG. 0B is a diagram showing an equation for explaining the operation of the circuit. 14, 15, 16, 17... horizontal counter,
18... Vertical counter, 23... Constant multiplier circuit, I, 25, 26, 27... Adder.

Claims (1)

[Claims] 1. In pattern recognition, etc., a horizontal counter counts the horizontal position of a bit pattern, a vertical counter counts the vertical position of the bit pattern, and a constant multiplier circuit multiplies the output of the vertical counter by a constant. , an adder that adds the output of the horizontal counter and the output of the constant multiplier circuit, and data is transferred to a memory address specified by the output of the adder while scanning the pattern in the vertical direction. An address control circuit for direct data transfer, characterized in that: