JPS5930335B2 - Auto-reset circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an auto-reset circuit composed of MO8 type transistors.

A main object of the present invention is to provide a circuit that automatically outputs a reset signal to initialize a logic circuit when power is turned on.

The conventional auto-reset circuit, as shown in Figure 1,
It is constructed by connecting a charging capacitor 3 and a resistor 4 for providing a time constant to a RESET terminal 2 of a logic circuit 1.

To explain the operation of the conventional circuit, immediately after the power is turned on to the logic circuit 1, the capacitor 3 is not charged with any electric charge, so the level is low.
It's on the level.

Therefore, the RESET terminal 2 is in a state where a reset signal is output.

Thereafter, the capacitor 3 is charged through the resistor 4 and reaches the "Hu" level, so that the reset signal to the logic circuit 1 is released.

The time from when the reset signal is issued to when it is released is the time constant C.
Determined by R.

In an actual circuit, R is approximately IOKΩ to several M, Q,
C is approximately 0.01 μF'-1 μF, so the time constant is 1-100 m5ec.

The resistance value that can be achieved with semiconductor integrated circuits is usually several MΩ or less.
Since the capacitor C is 10 PF or less, the realizable time constant is several tens of microseconds.

Therefore, it is very difficult to implement the conventional auto-reset circuit into an IC, and it has the drawback of requiring an external capacitor.

The present invention is based on the drawbacks of the conventional circuits (
That is, the present invention solves the problem that the capacitor 3 cannot be incorporated as an internal circuit of an IC, but is attached externally, and provides an auto-reset circuit that can be easily constructed on a single semiconductor substrate.

FIG. 2 shows a circuit configuration according to the present invention, which will be explained in detail below.

In Fig. 2, 5, 6, and 7 are P-channel type MOS transistors, 8 and 9 are CMO8 type O8 converters, 10 is a charging capacitor, 11 is a clock signal terminal, and 2 is a reset signal input terminal of logic circuit 1. It is.

The source of the P-channel MOS transistor 5 is connected to the power supply terminal 12, and the drain is connected to the source of the P-channel MO8) transistor, and the drain of the transistor 6 is connected to one end of the capacitor 10 and the input terminal of the CMO8 type O8 inverter 8. This constitutes a charging circuit that charges the capacitor 10 through on/off operations, and the other end of the capacitor 10 is connected to a fixed bias terminal, that is, ground.

15 is a flock oscillation circuit operated by power supply voltage VDD.

The P-channel MOS transistor 8) for maintaining the voltage level has its source connected to the power supply terminal 12 and its drain connected to the drain of the P-channel MOS transistor 6.
The gate is connected to the output part of the CMO8 type O8 inverter 8.

The output part of the CMO8 type O8 converter 8 is connected to the reset signal input terminal 2 of the logic circuit 1.

Further, the clock signal terminal 11 is connected to the gate of the P-channel type MOS transistor 5 and the input part of the CMO8 type O8 inverter 9.

The output part of the inverter 9 is connected to the gate of the P-channel type MOS transistor 6.

Next, the operation of the present invention will be explained in detail.

When the power supply voltage is applied to the reset circuit 14, FIG.
As shown in the figure, it takes a finite time ta to rise from O volts to VDD.

Since the capacitor 10 is in a completely discharged state when the power is turned on, the connection portion 13 of the capacitor 10 is in the "L" level state.

Therefore, the H'' level appears at the reset terminal 2 through the inverter 8, and the logic circuit 1 is in a reset state.

Therefore, the gate of P-channel MOS transistor 7 is 0.
Since it is in the H'' level state, it becomes non-conductive.

As shown in FIG. 3, as the power supply voltage rises, the clock signal CL of the clock signal oscillator 15 rises and enters an oscillation state.

The time from when the power is turned on to when the clock signal is input is indicated by ta in the time chart of FIG.

When the clock signal is input to the terminal 11, the clock signal is input to the gate of the P-channel MOS transistor 6 through the inverter 9, so that the transistors 5 and 6 repeat conduction and non-conduction states in opposite phases.

Since the P-channel MOS transistors 5 and 6 become conductive at the same time when the clock signal is switched, the capacitor 10 is gradually charged as shown in FIG. 3C.

When the potential at the connection point 13 of the capacitor 10 exceeds the threshold voltage VTR of the CMOS inverter 8, the output level of the inverter 8 is reversed and becomes ``L'' as shown in FIG. 3d.
” level, and the logic circuit 1 is released from the reset state.

As a result, the P-channel MOS transistor 7 becomes conductive, and the potential of the connection portion 13 of the capacitor 10 is held at the H'' level as shown in FIG. 3C, regardless of the subsequent clock signal.

In the time chart of FIG. 3, the time ta from the input of the clock signal to the release of the reset signal is substantially the pulse width of the reset signal, and in an actual circuit corresponds to several tens of pulses of the clock signal.

As is clear from the above operation, the circuit of the present invention is characterized in that the reset signal is output immediately after power is turned on, and the reset state of the logic circuit is released after the clock signal becomes stable.

In the circuit of the present invention, the resistor 4 is unnecessary and the capacitor 10 can have a small capacity, so there is no need to use external components.

Therefore, it has the advantage of being easily constructed within a single semiconductor substrate.

In the embodiment, the P-channel MO8I-transistor can be replaced with an n-channel MOS transistor.

Further, the charging circuit can be constructed by connecting a plurality of P or N type transistors in series.

The present invention can be applied as an auto-reset circuit that can be incorporated into any integrated circuit having a clock signal source such as a microcomputer or a clock.

[Brief explanation of the drawing]

FIG. 1 shows a conventional auto-reset set circuit, FIG. 2 shows an auto-reset circuit of the present invention, and FIG. 3 shows a time chart in the circuit of FIG. 2. 1...Logic circuit, 5, 6, 7...P channel MOS transistor, 8.9...CM
OS inverter, 10... Capacitor, 15.
...Clock oscillation circuit.

Claims (1)

[Claims] 1. A charging capacitor having one end coupled to a first fixed potential terminal of a power source, and a first capacitor connected to a locking source operated by the power source.
A MOS inverter is connected in series between a second fixed potential terminal of the power source and the charging capacitor, the gates of some MOS transistors are directly connected to the clock source, and the gates of the remaining MOS transistors are connected to the first fixed potential terminal. a charging circuit that is composed of a plurality of MOS transistors connected to the output section of the CMOS inverter and charges the charging capacitor through on/off operations; and a second charging circuit that outputs a reset signal when the other end of the charging capacitor reaches a predetermined potential. a CMOS inverter, and a CMOS inverter that connects the second fixed potential to the other end of the charging capacitor to maintain the charge level of the charging capacitor at the power supply potential when the reset signal is input to the gate electrode.
O8I-An auto-reset circuit consisting of a transistor. 2. The auto-reset circuit according to claim 1, wherein the MOS transistor is a P-type or N-type MOS transistor.