JPS5930349B2 - Out-of-sync detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an out-of-synchronization detection method that can be used in a phase-locked loop (hereinafter referred to as PLL) used in a frequency synthesizer such as a local oscillator of a transmitter/receiver.

When a PLL is used as a local oscillator in a transceiver, it is necessary to prevent the output from being transmitted to the next stage when the output frequency of the PLL exceeds a permissible range, such as when switching the output frequency.

Conventionally, there has been a circuit as shown in FIG. 1, for example, as a PLL out-of-synchronization detection circuit.

In this figure, two input terminals 1a, 1 of the phase comparator 1
A reference signal (frequency Fr) and a controlled signal (if synchronized, both frequency and phase match the reference signal) are given to b.

The phase comparator 1 compares the phase of the controlled signal with respect to the reference signal, and in the case of an advanced phase or the frequency of the controlled signal is low, the first output terminal 1c is used, and in the case of a delayed phase or the controlled signal When the frequency is high, a negative pulse having a width proportional to the phase difference is applied to the second output terminal 1d.

Inverters 2 and 3 are connected to the respective output terminals 1c and 1d, and the respective outputs are inverted and sent to the next stage culm wave number fine adjustment circuit (
(not shown) and is controlled to match its phase and its frequency to the reference signal by changing the frequency of the controlled signal.

The two output terminals 1c and 1d of the phase comparator 1 are connected to the OR circuit 4.
The output terminal of the OR circuit 4 is connected to the base of the transistor 5 via an integrating circuit including a resistor R1 and a capacitor C1.

The OR circuit 4 generates a negative pulse having a width corresponding to the frequency difference when the frequencies of the two signals applied to the phase comparator 1 are different.

The collector of the transistor 5 is connected to the base of the transistor 6 which amplifies the output of the PLL circuit, and when it is on, the base voltage of the transistor 6 is lowered and the transistor 6 is
This is what makes it inoperable.

In such a conventional out-of-synchronization detection circuit, if the frequency difference between the reference signal and the control signal is large and the positive pulse width of the OR circuit 4 is greater than a predetermined value, the waveform as shown in Figure 2 (a) and (c) is detected. Then, a positive voltage is applied to the base of the transistor 5 by an integrating circuit including a resistor R1 and a capacitor C1.

Therefore, as shown in FIG. 2, transistor 5 is conductive and transistor 6 is cut off.

Therefore, the conventional out-of-synchronization detection circuit does not operate unless an error pulse of a predetermined width or more determined by one period (1/Fr) of the reference signal and the time constant of the integrator circuit is applied to the integrator circuit, as shown in Figure 2A. , it was not possible to inhibit the PLL circuit output.

The present invention has been made in order to eliminate such conventional drawbacks, and provides an out-of-synchronization detection circuit that operates even when the width of the error pulse is narrow and can change the width of the operating error pulse by adjustment. The purpose is to provide.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention, and the configurations of the phase comparator 1, inverter 2.3, and OR circuit 4 are the same as in the conventional example.

In the present invention, the output of the OR circuit 4 is applied via an inverter 7 to a variable monostable multivibrator MM1 that can change the time width of the output pulse.

The monostable multivibrator MM1 provides a pulse for a preset period to the next stage after a minute delay time ta has elapsed when there is an input pulse.

Further, to the output terminal of the inverter 7, in order to cancel the delay time ta of the monostable multivibrator MM1, a delay circuit 11 having a delay time ta, consisting of inverters 8, 9, 10, a resistor R2, and a capacitor C2 is connected.

, the outputs of the monostable multivibrator MM1 and the delay circuit 11 are given to a NAND circuit 12, and the AND output thereof is given as an input to the next stage monostable multivibrator MM2.

The monostable multivibrator MM2 has one period of the reference signal (
1/Fr), and its output is given to the base of the switching transistor 5.

As in the conventional example, the collector of the transistor 5 is connected to the base of the PLL output amplifying transistor 6.

Next, the operation of this embodiment will be explained with reference to FIG.

FIG. 4 is a waveform diagram showing the operation of each part of this embodiment.

A in the figure shows an output waveform of the inverter 7 indicating an error pulse, and shows a case where the frequencies of the reference signal and the controlled signal are different.

In the figure, the minute delay time ta is determined by the output of the inverter 7.
After the elapse of time, a negative output generated by the monostable multivibrator MM1 is shown for a preset time tb from time t2.

The output of the delay circuit 11 is delayed by a minute delay time ta from the output of the inverter 7, as shown in FIG. 4C, and is inverted.

However, the width of the positive pulse is equal to the error pulse, and its rise is simultaneous with the rise of the monostable multivibrator MM1.

These outputs are given to the NAND circuit 12, and a negative output appears only when the error pulse width is longer than the set time tb of the monostable multivibrator MM1 and at the same time is at the Ht+ level.

Figure 4-2 shows this negative pulse, which causes the monostable multi-bibreak MM to be activated at time t3.
2 is triggered.

Since the set time of this monostable multivibrator MM2 is greater than or equal to 1/Fr, which is the period of the error pulse, the width of the error pulse is greater than or equal to the set time tb of the monostable multivibrator MM1, as shown in Figure 4 A and E. As long as it is retriggered before the pulse of monostable multi-bibreak MM2 ends.

In Fig. 4 E, this pulse end time t, the previous time t
It will be retriggered at 4 and this positive pulse will continue.

This pulse causes transistor 5 to operate, and the output of the PLL circuit is stopped by transistor 6 being inoperable.

As described above, according to the configuration of the present invention, the pulse width of the monostable multivibrator MM1 can be freely set, so the allowable range of the output frequency of the PLL circuit can be freely determined.

Furthermore, since an integrating circuit is not used as in the conventional case, the operation is reliable.

The out-of-synchronization detection circuit according to the present invention can be applied to various circuits such as a frequency synthesizer and a final stage automatic tuning circuit of a transmitter/receiver.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional out-of-synchronization detection circuit, FIG. 2 is a waveform diagram of each part thereof, FIG. 3 is a block diagram showing an embodiment of the out-of-synchronization detection circuit of the present invention, and FIG. 2 is a waveform chart showing the operation of each part of this embodiment. FIG. 1... Phase comparator, 2, 3, 7, 8, 9, 10
...Inverter, 4...OR circuit, 5
, 6...Transistor, MMLMM2...
... Monostable multivibrator, 12... NAND circuit.

Claims (1)

[Scope of Claims] 1. A phase comparator that compares the phases of a reference signal and a controlled signal and outputs outputs from two output terminals when the phase is delayed or the frequency is high or low, and the logic of the two outputs. a first gate circuit that calculates the sum; a first monostable multi-bi break that receives the output of the first gate circuit as an input and has a predetermined operating time; and a first monostable multi-bibreak connected to the output terminal of the first gate circuit a delay circuit having a delay time practically equal to the minute operation delay time of the first monostable multi-bi break; a second gate circuit that performs an AND operation of the first monostable multi-bi break and the delay circuit; a second monostable multivibrator whose operating time is set to a time width equal to or greater than the period of the reference signal based on the output of the second gate circuit; An out-of-synchronization detection circuit is characterized in that the output of a phase-locked loop circuit is stopped based on the timing.