JPS593055B2 - Frame synchronization prevention method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for preventing frame synchronization in wireless PCM lines and the like.

In wireless PCM communication systems, PCM pulse trains are often transmitted using a phase modulation system.

FIG. 1 is a block diagram showing the configuration of a transmitting/receiving device for a wireless PCM communication system using a four-phase phase modulation system. In FIG. 1, 1 indicates a transmitting side carrier terminal device (■■).

The output of MUXI is bipolar (
B) - After performing unipolar conversion, serial (S) and parallel (P) conversion is performed to convert into two PCM pulse trains. Further, logic conversion such as PN scraping is performed to rearrange the PCM pulse train, and further frame pulses and control signal pulses are inserted. The output of the line switching device is subjected to differential conversion by differential logic in the PCM radio transmitting device 3, and then subjected to four-phase phase modulation on a predetermined carrier wave, and is sent out via the antenna 4 as a radio signal. The radio signal received via the antenna 5 undergoes frequency conversion in the PCM radio receiving device 6, demodulates it to extract a pulse train, performs differential conversion using differential logic, and converts it into two pulse trains. Reproduce.

The output of the PCM receiving device 6 is subjected to logical conversion in the line switching device T, which is the opposite of that on the transmitting side, and the pulse strings are rearranged, and then the pulses inserted on the transmitting side are extracted. Furthermore, parallel (P) and serial (□) conversion is performed, and uni-bolar to bi-bolar (B) conversion is performed to reproduce the original signal and input it to the receiving side carrier terminal unit (DMUX) 8.
In this way, in the case of the four-phase phase modulation method, the combination of two PCM pulses is transmitted as phase information, but the absolute phase cannot be detected on the receiving side, and the phase of the reference carrier wave for coherent detection is also four. Since the states can change, the synchronous detection output can also have four output states for one reception phase.

Therefore, in order to eliminate the need for an absolute reference phase on the receiving side, a phase difference modulation method is used in which differential conversion is performed on the transmitting side and then transmitted. In the phase difference modulation method, the phase of the immediately preceding time slot is always used as a reference, and the phase difference with this is 0.
Which of 0, 900, 1800 and 270 is to be taken is determined depending on the combination of 2 bits of the PCM pulse train. Now, two series of PCM pulse trains generated by serial-to-parallel conversion on the transmitting side are named PCM1 and PCM2, respectively.

After the pulse trains PCM1 and PCM2 are differentially converted by the transmission differential logic, the carrier wave is phase-modulated according to the combination of codes to generate a radio signal, and on the receiving side, after demodulating the received radio signal, Reverse differential conversion is performed by the receiving differential logic to regenerate the original PCM pulse train. Figure 2 shows the PCM on the transmitter and receiver sides of the device in Figure 1.
FIG. 3 is a diagram showing conversion of a pulse train.

In FIG. 2, A and b indicate PCM pulse trains PCM1 and PCM2, respectively, generated by serial-to-parallel conversion and added as transmission differential logic inputs, e indicates the output after transmission differential logic processing, and D and e 3 respectively show the PCM pulse trains PCMV and PCM2'' reproduced after receiving differential logic processing. Also, FIG. 3 shows the correspondence between the sign of the input and the phase angle in four-phase phase modulation. Fig. 3a shows the gray phase plane A, and Fig. 3b shows the natural phase plane B. Now, the numbers of the pulses in the input PCM pulse trains PCMl and PCM2 shown in Figs. It is assumed that the immediately preceding bit in the transmission logic processing is 01.

01 is a spoon on the phase plane B in FIG. 3b.

The bits of the corresponding pulse numbers 1 and 2 of PCM1 and PCM2 are 01, which is true on the phase plane A in FIG. 3a. Therefore, the output after the transmission logic processing is the second
00 as shown in Figure c. PC as follows
The amount of phase shift determined by the corresponding bits of the M pulse trains PCM1 and PCM2 produces the transmission logic processing output shown in FIG. 2c, thereby performing phase modulation. The phase modulated wave generated in this way is demodulated on the receiving side, and
Added to receive differential logic.

Since the previous bit in the input is 01 and the next bit is 00, the phase difference between them is z on the phase plane B. Therefore, the output after differential logic processing is 10 on the phase plane A, which corresponds to the phase angle ♂. Thereafter, the PCM pulse trains PCMV and PCM7 are reproduced on the receiving side in this manner. Now, pulse number 5 in Fig. 2 A, b,
If the output should be 01 in the transmission logic in response to a PCM signal of 6, but it becomes 11 due to the occurrence of error b, then the PCM pulse train generated after differential logic processing on the receiving side will be , pulse numbers 5, 6, 7, and 8 are erroneous as shown in FIGS. 2D and 2e. Note that the outputs indicated with arrows in FIG. 2C, d, and e indicate incorrect seconds. Furthermore, if a 1-bit error occurs in the transmission logic processing corresponding to pulse numbers 15, 16; 31, 32; 41, 42 in FIG. Two-bit errors occur at numbers 16, 18; 32, 33; 41, and 44, respectively.

Errors similar to error D in transmission logic also occur during wireless transmission due to noise and other causes.

Now, if no error occurs in the wireless transmission path including the transmission logic, the pulse train at the transmission input as described above,
The pulse train in the received output matches. However, when a one-bit error occurs in the transmission path, the error in the received output is not limited to one bit, but tends to be two or four bits. In the wireless PCM system, usually
A common method is to perform differential logic conversion on the signal from the transmitting carrier terminal equipment and modulate the carrier wave.In this case, the number of code errors that occur on the receiving side after passing through the transmission system is always an even number. .

In the case of the four-phase phase modulation method, the errors that occur after parallel-to-serial conversion typically take the four types shown in FIGS. 1-4.

On the other hand, in carrier terminal equipment, synchronization pulses may be inserted in a concentrated manner for a certain number of bits.

If 3 bits are used as a frame pulse, and if such a frame pulse falls in the four positions shown in Figure 4, 1 to 4, at least 2 of the 3 bits or all of the frame pulses will be erroneous D. Therefore, frame synchronization cannot be achieved, and the transmission path becomes unsynchronized, making it impossible to perform normal transmission. In this way, in the conventional wireless PCM communication system, a 1-bit error in the transmission path causes an even-numbered bit error in the reception output, so if synchronization pulses are inserted in a concentrated manner, the synchronization will be lost and the normal state will be lost. There was a drawback that transmission was no longer possible.

The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to create a signal in which a 1-bit error D in the transmission path does not cause multiple errors 9 in the reception output in a concentrated manner. The aim is to enable transmission methods.

In order to achieve this object, the frame synchronization prevention method of the present invention provides a digital communication transmitter/receiver that performs phase modulation and demodulation using differential logic. means for rearranging one pulse train and the other pulse train, respectively, according to a certain law, and means for rearranging both pulse trains received on the receiving side in reverse order, respectively, according to the same law as on the transmitting side; It is characterized by comprising means for delaying the other pulse train by the same amount of delay as that on the transmitting side, thereby scattering erroneous rebits in the demodulated signal to prevent frame synchronization. Examples will be described below.

FIG. 5 shows an embodiment of the frame synchronization prevention method of the present invention.

The figure shows a case where the method of the present invention is applied to a transmitting/receiving device for wireless PCM communication, and 11 is a transmitting side carrier terminal device (
MUX), 12 is a bipolar unipolar converter (B/
U), 13 is a delay circuit (DL), 14-314-2 is a transmitting side pulse train rearrangement circuit (SCR), 15 is a differential logic circuit, 16 is a wireless transmitter, 17 is a transmitting antenna, 18
19 is a receiving antenna, 19 is a radio receiving device, 20 is a differential logic circuit, 21-1 and 21-2 are receiving side pulse train rearrangement circuits (DSCR), 22 is a delay circuit, and 23 is a unipolar-bipolar converter (U/B ), 24 is a receiving side carrier terminal equipment (DMUX). In FIG.
By performing bipolar-unibolar conversion and series-parallel conversion, two series of PCM pulse trains PCMl and PC
M2 is produced.

One PCM pulser station C2 is delayed by an appropriate number of bits n in the delay circuit 13, and the pulse train PCM2''
occurs. Thereafter, the two series of PCM pulse trains are rearranged by the transmitting side pulse rearranging circuits 14-1 and 14-2 according to a fixed rule for each fixed number of bits, thereby producing pulse trains PCMlA and PCM7A. .
The rearranged two series of PCM signals are subjected to differential conversion in the transmitting side differential logic circuit 15. In the wireless transmitting device 16, the carrier wave is phase-modulated using the differentially converted output, and the output phase-modulated wave is sent out from the transmitting antenna 17. The phase modulated wave input from the receiving antenna 18 is transmitted to the wireless receiving device 1.
After being decoded at 9, differential conversion is performed at a receiving differential logic circuit 20 to generate two PCM pulse trains.

This pulse train is processed by the receiving side pulse rearranging circuit 21.
-1, 2L2, the order is reversed to that on the transmitting side. Among the rearranged signals, PCM on the transmitting side
The pulse train corresponding to l is delayed by the same delay amount as on the transmitting side by the delay circuit 22. After that, the unipolar-bipolar conversion circuit 23 performs parallel-to-serial conversion and unipolar-bipolar conversion to convert the PCM.
The signal is reproduced and input to the receiving side carrier terminal device 24. FIG. 6 is a diagram showing the conversion of PCM pulse trains on the transmitting side and the receiving side in the embodiment of FIG. 5.

In Fig. 6, A and b are two series of PCM pulse trains PCM1 and PCM generated by series-to-parallel conversion on the transmitting side.
CM2 is shown with its corresponding pulse number. One PCM pulse train PCM2 is delayed by 4 bits to produce a pulse train PCM2'' shown in FIG. 6c.

Pulse trains PCM1 and PCM7 are rearranged according to the same rule. In the case of this embodiment, as shown in FIG. 6D and e, for example, 5, 1, 7, 3, 6, 2, 8, 4, etc.
・The pulse trains PCMlA,P are rearranged as follows, respectively.
yields CM7A. Pulse train PCMlA, PCM2″A
is differentially converted to produce a phase modulated signal.

The correspondence between the input sign and the phase angle in this case is the same as that shown in FIG. FIG. 6f shows the signal thus generated after the transmitting side differential logic processing. That is,
In this case as well, if the leading bit is 01 for pulse numbers 13 and 6 in FIGS. 6D and 6e, then pulse number 13,
Since 6 is 00, the phase shift angle is O on the phase plane A in Figure 3a.
Therefore, the position on the phase plane B does not change, and therefore the output is 01. Thereafter, the output shown in FIG. 6f is produced in the same manner. On the receiving side, the input signal is differentially converted again.

In the above case, the phase difference between the preceding bit 01 and the next bit 01 is O on the phase plane B, and is 1. Therefore, the output after differential processing is 00 on the phase plane A, which corresponds to a phase angle of 0. In the same manner as shown in FIG. 6G. produces the output shown at h. In this way, on the receiving side, the PCM pulse train PCMlA
, PCM7A is played back.

Now, suppose that, for example, a 1-bit error v occurs at pulse number A in the signal after the differential logic processing on the transmitting side shown in FIG. 6f. The resulting error in the differential conversion output on the receiving side is a maximum of 4 bits, as in the case of the example shown in FIG. However, in this case, the 4-bit error b is the 6th
As shown in Figures G and h, pulse numbers 21, 14, 1
7 and 10. Therefore, the received differential logic output is rearranged and delayed by a pulse rearranging circuit and a delay circuit on the receiving side, and the P after performing parallel-to-serial conversion is
The position of the above-mentioned error bit in the CM pulse train is the 6th
As shown in Figure i, it occurs discretely and is not concentrated as in the prior art.

This is because, in the case of the method of the present invention, the transmitting side delays one of the pulse trains and rearranges both pulse trains, and the receiving side performs an operation to restore this. As mentioned above, an error ν similar to that in the differential logic processing on the transmitting side occurs in the transmission path due to the influence of noise and the like.

However, according to the method of the present invention, a 1-bit error occurring in the transmission system including the transmitting side differential logic will generate multiple errors after receiving differential logic processing, but by delaying and rearranging the PCM pulse train. When it is reproduced, it is discrete, so even if synchronization pulses are inserted intensively, frame synchronization is maintained and normal transmission is possible. As explained above, according to the frame out-of-sync prevention circuit of the present invention, even when synchronization pulses are intensively inserted at the carrier end station in a differential phase modulation wireless device, there is no possibility that out-of-sync will occur on the receiving side. It is possible to perform stable transmission with less noise, and excellent effects can be obtained. In the above embodiment, the case of four-phase phase modulation was explained, but the frame synchronization prevention method of the present invention
Needless to say, the present invention can be easily extended to the case of n-phase phase modulation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a transmitter/receiver for a wireless PCM communication system using a four-phase phase modulation method. Figure 3 is a diagram showing the correspondence between the sign of the input and the phase angle in four-phase phase modulation, Figure 4 is a diagram showing the form in which error D occurs in the four-phase phase modulation method, and Figure 5 is a diagram showing the frame synchronization of the present invention. FIG. 6 is a diagram illustrating an embodiment of the prevention method, and is a diagram illustrating conversion of pulse trains on the transmitting side and the receiving side in the embodiment of FIG. 5. DESCRIPTION OF SYMBOLS 1... Transmitting side carrier terminal equipment (MUX), 2... Line switching device, 3... PCM radio transmitting device, 4... Transmitting antenna, 5... Receiving antenna, 6... PCM Radio receiving device, 7... Line switching device, 8... Receiving side carrier terminal device (DMUX), 11... Transmitting side carrier terminal device (MUX), 12... Bipolar uni-bolar converter (B/U), 13...Delay circuit (DL), 14-1,
14-2... Transmission side pulse train rearrangement circuit (SCR)
, 15... Differential logic circuit, 16... Wireless transmitter,
17... Transmitting antenna, 18... Receiving antenna, 1
9... Radio receiving device, 20... Differential logic circuit, 21
-1, 21-2... Receiving side pulse train rearrangement circuit (D
SCR), 22... Delay circuit (DL), 23... Unipolar bipolar converter (U/B), 24... Receiving side carrier terminal equipment (DMUX).

Claims (1)

[Claims] 1. In a digital communication transmitter/receiver that performs phase modulation and demodulation using differential logic, means for delaying one of the parallel pulse trains on the transmitting side, and means for delaying the delayed pulse train and the other pulse train, respectively, according to certain rules. means for rearranging both pulse trains received at the receiving end according to the same law as at the transmitting end; and means for delaying the other pulse train by the same amount of delay as at the transmitting end. 1. A method for preventing frame asynchronization, comprising means for preventing frame asynchronization by dispersing error bits in a demodulated signal.