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JPS593068B2 - solid-state image sensor - Google Patents
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JPS593068B2 - solid-state image sensor - Google Patents

solid-state image sensor

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Publication number
JPS593068B2
JPS593068B2 JP53112589A JP11258978A JPS593068B2 JP S593068 B2 JPS593068 B2 JP S593068B2 JP 53112589 A JP53112589 A JP 53112589A JP 11258978 A JP11258978 A JP 11258978A JP S593068 B2 JPS593068 B2 JP S593068B2
Authority
JP
Japan
Prior art keywords
picture element
film
solid
photoconductive film
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53112589A
Other languages
Japanese (ja)
Other versions
JPS5538782A (en
Inventor
一文 小川
隆夫 近村
和也 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53112589A priority Critical patent/JPS593068B2/en
Publication of JPS5538782A publication Critical patent/JPS5538782A/en
Publication of JPS593068B2 publication Critical patent/JPS593068B2/en
Expired legal-status Critical Current

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  • Transforming Light Signals Into Electric Signals (AREA)

Description

【発明の詳細な説明】 本発明は光導電体膜を有する高感度、高密度固体撮像素
子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-sensitivity, high-density solid-state imaging device having a photoconductor film.

固体撮像素子は第1図aに上面図、同bに同XX断面図
を示す様に、下地基板1上の中心部には例えば光学像を
感知するホトダイオード、光学信号を転送する電荷転送
素子等よりなる絵素部2(後述)を設け、この絵素部2
の周囲には絵素部を駆動するシフトレジスタ等の駆動部
3が設けられている。
As shown in FIG. 1A, a top view, and FIG. A picture element part 2 (described later) is provided, and this picture element part 2
A driving section 3 such as a shift register is provided around the pixel section 3 to drive the picture element section.

尚、駆動部3上には絶縁物が形成されている。この駆動
部3の端子と、絶縁膜の開孔を5 介して接続され外部
配線用パッド部4に及ぷ金属配線5が設けられている。
また絵素部2上には光導電膜(ZnSe−Znl−xC
dxTe)6、透明電極Tがそれぞれ設けられている。
さて、上記した固体撮像素子を製造する工程で、10下
地基板1上に絵素部2と駆動部3及び金属配線5を形成
した後、光導電膜(れ象H弘11口灯e)6を装着する
際、一般の半導体装置の製造に用いるホトリングラフィ
ック法では、湿式であるために光導電膜6の光導電特性
が劣化してしまうので採15用できず、従来は下地基板
1に形成された駆動部3の金属配線5部を蒸着マスクで
被い、絵素部2上に光導電膜6および透明電極7を蒸着
する(マスク蒸着方式という)方法が用いられている。
Note that an insulator is formed on the drive section 3. A metal wiring 5 is provided which is connected to the terminal of the drive part 3 through an opening 5 in the insulating film and extends to the external wiring pad part 4.
Furthermore, a photoconductive film (ZnSe-Znl-xC
dxTe) 6 and a transparent electrode T are provided respectively.
Now, in the process of manufacturing the above-described solid-state image sensor, after forming the picture element part 2, the driving part 3, and the metal wiring 5 on the base substrate 1, the photoconductive film 6 is formed. When attaching the photoconductive film 6 to the base substrate 1, the photolithographic method used in the manufacture of general semiconductor devices cannot be used because it is a wet method and the photoconductive properties of the photoconductive film 6 deteriorate. A method (referred to as a mask vapor deposition method) is used in which the formed metal wiring 5 of the drive section 3 is covered with a vapor deposition mask, and the photoconductive film 6 and the transparent electrode 7 are vapor deposited on the picture element section 2.

しかしながら、マスク蒸着方式を用いた場合、20マス
ク合せ精度が数百ミクロン程度で非常に悪いので、合せ
ズレの許容範囲A、すなわち絵素部2と配線5までの距
離が狭いと第2図に示す様に、光導電膜6や、その上に
付ける透明電極Tが所定部から著しくズレた場合、金属
配線5と光導電膜256との膨張率の違いにより、駆動
部3上の金属配線(たとえばAl配線)5と重なつた光
導電膜6に割れAが生じたりして、このひび割れ部Aで
暗電流が増加する。また、透明電極Tがズレた場合には
、金属配線5間で短絡Bが生じる恐れがある。30以上
のような欠点を除去するため、従来法では合せズレの許
容範囲Aを大きく取ることで解決していた。
However, when using the mask evaporation method, the 20 mask alignment accuracy is very poor, on the order of several hundred microns. As shown, if the photoconductive film 6 or the transparent electrode T attached thereon is significantly deviated from the predetermined position, the metal wiring on the drive section 3 ( For example, cracks A may occur in the photoconductive film 6 overlapping the Al wiring (5), and dark current increases at the cracks A. Furthermore, if the transparent electrode T is misaligned, there is a risk that a short circuit B will occur between the metal wirings 5. In order to eliminate defects such as 30 or more, the conventional method solves the problem by increasing the tolerance range A of misalignment.

しかしながら、合せズレの許容範囲Aを大きく取る方法
では、当然のことながら固体撮像素子のチップサイズが
非常に大きくなつてしまう35欠点がある。本発明は絵
素部周囲に設けられた金属配線上を光導電膜と同程度の
線膨張率を持つ絶縁膜で被うことにより、光導電膜形成
時のマスク合せズレによる不良発生を少なくしようとす
るものである。
However, the method of increasing the tolerance range A for misalignment has the disadvantage that the chip size of the solid-state imaging device becomes extremely large. The present invention aims to reduce the occurrence of defects due to misalignment of the mask during formation of the photoconductive film by covering the metal wiring provided around the picture element with an insulating film having a coefficient of linear expansion similar to that of the photoconductive film. That is.

以下本発明を図面を用いて実施例とともに説明する。第
3図は本発明の一実施例を示す断面図である。
The present invention will be described below with reference to the drawings and embodiments. FIG. 3 is a sectional view showing one embodiment of the present invention.

シリコン基板11上に、通常のMOSプロセスを用いて
光学像を感知するホトダイオードと、BBD素子とより
なる絵素部12と、MOS素子等により構成されたシフ
トレジスタ等よりなる駆動部13を形成した後、前記B
BD素子の絵素部12および駆動回路部13の電極を取
り出す金属配線14のパツド部15を除いて絶縁膜16
を形成してある。このとき、後の工程で形成する光導電
膜の線膨張係数と絶縁膜16の線膨張係数が著しく異る
場合、たとえば、光導電膜としてZnSe−Znl−X
CdxTeを用い、絶縁膜とし通常のCVD法、あるい
はPVD法によるSiO2を用いた場合には、ZnSe
−Znl−XCdxTeの線膨張係数(70〜80×1
0−7Deg−1)に比べて、SiO2の線膨張係数(
5x10−7Deg−1)が非常に小さいので、SiO
2に重つた部分でのZnSe−Znl一XCdxTe膜
に従来のようにヒビ割れが生じる。従つて、光導電膜と
してZnSe−Znl−XCdxTeを用いる場合には
、線膨張係数が20〜130×10−7Deg−1程度
の絶縁膜、たとえぱ、Si3N4(39×10−7),
Al2O3(70×10−7Deg−1),10〜20
%P2O5を含むリンガラス(約50×10−7Deg
−1),SiO(40×10−7Deg)などを用いる
必要がある。ところで、絵素部12およびパツド部15
の絶縁膜16を除去する方法としては第4図A,bにそ
の工程を示すように絶縁膜形成面にエツチング防止膜1
7で絵素部12およびパツド部15を被つた後、PVD
法あるいはCVD法を用いて、絶縁膜16を全面に堆積
する(第4図a)。
On a silicon substrate 11, a photodiode for sensing an optical image, a picture element section 12 consisting of a BBD element, and a driving section 13 consisting of a shift register etc. constituted by a MOS element etc. were formed using a normal MOS process. After, the above B
The insulating film 16 is removed except for the pad portion 15 of the metal wiring 14 from which the electrodes of the pixel portion 12 and drive circuit portion 13 of the BD element are taken out.
has been formed. At this time, if the linear expansion coefficient of the photoconductive film to be formed in a later step is significantly different from that of the insulating film 16, for example, ZnSe-Znl-X may be used as the photoconductive film.
When CdxTe is used and SiO2 is used as the insulating film by the usual CVD method or PVD method, ZnSe
-Linear expansion coefficient of Znl-XCdxTe (70-80×1
0-7Deg-1), the linear expansion coefficient of SiO2 (
5x10-7Deg-1) is very small, so SiO
Cracks occur in the ZnSe-Znl-XCdxTe film at the overlapped portions as in the prior art. Therefore, when using ZnSe-Znl-XCdxTe as a photoconductive film, an insulating film with a linear expansion coefficient of about 20 to 130 x 10-7 Deg-1, for example, Si3N4 (39 x 10-7),
Al2O3 (70×10-7Deg-1), 10-20
Phosphorous glass containing %P2O5 (approximately 50 x 10-7Deg
-1), SiO (40×10 −7 Deg), etc. must be used. By the way, the picture element part 12 and the pad part 15
As a method for removing the insulating film 16, as shown in FIGS.
After covering the picture element part 12 and pad part 15 in step 7, PVD
An insulating film 16 is deposited over the entire surface using a method or a CVD method (FIG. 4a).

その後、前記エツチング防止膜17の反転パターンを持
つホトレジストパターン18を用いて、写真蝕亥1法に
より前記エツチング防止膜17上の絶縁膜16をエツチ
ング除去し、絶縁膜16を形成する。
Thereafter, the insulating film 16 on the etching preventive film 17 is removed by etching using a photoresist pattern 18 having an inverse pattern of the etching preventive film 17 by photoetching method 1, thereby forming the insulating film 16.

なお、このとき絶縁膜として、CVD法により、P2O
5濃度が10〜20%のリンガラスを堆積したり、スパ
ツタ法でAl2O3やSi3N4を蒸着するのであれば
、厚さ1〜2ミクロンの通常のホトレジストパターンを
エツチング防止膜として用いることができる。また、ホ
トレジストパターンをエツチング防止膜として用いた場
合、ポストベーキングに、N2またはAr2等の不活性
ガスプラズマを用いる方が、レジストパターンのエツヂ
流れが防げられる(第4図b)。次に、エツチングに用
いたレジストパターン18、およびエツチング防止膜1
7を除去することにより、第3図に示す素子が得られる
。尚、このときエツチング防止膜として、レジストパタ
ーンを用いた場合には、多少炭化されていたとしても、
エツチングに用いたレジストパターンとともに02プラ
ズマで同時にエツチング除去できる利点がある。絵素部
12のホトダイオードと光導電膜を接続するに際し、写
真蝕刻法を用いて絵素部12の各ホトダイオード上の絶
縁物にそれぞれコンタクト窓を開口し(図示せず)、M
Oの電極を開孔部に形成した後(図示せず)、蒸着マス
クを用いて、光導電膜19と透明電極20を順次蒸着す
ることにより、第5図に示す光導電膜付の固体撮像素子
が得られる。
At this time, P2O was used as the insulating film by CVD method.
If phosphorus glass with a concentration of 10 to 20% is deposited or Al2O3 or Si3N4 is deposited by sputtering, a conventional photoresist pattern with a thickness of 1 to 2 microns can be used as an anti-etching film. Further, when a photoresist pattern is used as an etching prevention film, edge flow of the resist pattern can be prevented by using an inert gas plasma such as N2 or Ar2 for post-baking (FIG. 4b). Next, the resist pattern 18 used for etching and the etching prevention film 1 are
By removing 7, the device shown in FIG. 3 is obtained. In addition, if a resist pattern is used as the etching prevention film at this time, even if it is slightly carbonized,
There is an advantage that the resist pattern used for etching can be removed by etching at the same time using 02 plasma. When connecting the photodiodes of the picture element section 12 and the photoconductive film, a contact window (not shown) is opened in the insulator on each photodiode of the picture element section 12 using photolithography.
After forming an O electrode in the opening (not shown), a photoconductive film 19 and a transparent electrode 20 are sequentially deposited using a vapor deposition mask, thereby producing a solid-state image sensor with a photoconductive film shown in FIG. An element is obtained.

なお、ここで、ホトダイオードの絶縁物にコンタクト窓
を開ける工程は、前記絶縁膜16の形成工程前に行つて
おいてもよい。以上の様に、本発明は金属線部14を光
導電膜19と同程度の膨張係数を持つ絶縁膜16で被つ
ているので1光導電膜16が金属配線部14に重つても
、膨張率の違いによる割れやハガレが起こらないので、
光導電膜16のリーク電流が生じない。
Note that here, the step of opening a contact window in the insulator of the photodiode may be performed before the step of forming the insulating film 16. As described above, in the present invention, since the metal wire portion 14 is covered with the insulating film 16 having the same expansion coefficient as the photoconductive film 19, even if one photoconductive film 16 overlaps the metal wiring portion 14, the expansion coefficient is There will be no cracking or peeling due to differences in
No leakage current occurs in the photoconductive film 16.

2金属配線14が絶縁膜16で被れているので透明電極
20の合せズレが生じて、透明電極20が金属配線14
上に及んでも、配線14間の短絡が起こらない。
Since the two metal wirings 14 are covered with the insulating film 16, misalignment of the transparent electrodes 20 occurs, and the transparent electrodes 20 are covered with the metal wirings 14.
A short circuit between the wiring lines 14 does not occur even if the wires are connected to the top.

3金属マスクの合せズレが多少生じたとしても、光導電
膜16の・・ガレや配線14間シヨートの問題が生じな
いので、第5図に示す合せズレ許容範囲Bを広く取る必
要が無く素子面積を狭くでき、高集積化に適している。
3. Even if there is some misalignment of the metal mask, there will be no problem of scratching of the photoconductive film 16 or shorting between the wiring lines 14, so there is no need to take a wide misalignment tolerance range B shown in FIG. The area can be reduced, making it suitable for high integration.

4絵素部12以外も光導電膜19で被うことが出来るの
で、光導電膜19をシフトレジスターやその他能動素子
を有する駆動部13の光遮蔽膜としても利用できる。
Since areas other than the four picture element parts 12 can be covered with the photoconductive film 19, the photoconductive film 19 can also be used as a light shielding film for the drive part 13 having a shift register or other active elements.

5絶縁膜16形成工程であらかじめ絵素部12およびパ
ツド部15をエツチング防止膜17で被つておくことに
より、絵素部がエツチング液で侵されることがないので
、歩留良く、固体撮像素子を形成出来る。
5. By covering the picture element part 12 and the pad part 15 with the etching prevention film 17 in advance in the step of forming the insulating film 16, the picture element part is not attacked by the etching solution, so that the solid-state image sensor can be manufactured with high yield. Can be formed.

等の効果を奏する。It has the following effects.

ここで、第5図の断面図における絵素部12の一部Cの
拡大断面図を第6図aに示し、第6図bに示す同平面図
及び第7図A,bに示す動作図を用いて、絵素部の構造
及び動作について説明する。
Here, an enlarged sectional view of a part C of the picture element section 12 in the sectional view of FIG. 5 is shown in FIG. 6a, a plan view thereof shown in FIG. 6b, and an operation diagram shown in FIGS. The structure and operation of the picture element section will be explained using the following.

まず、第6図A,bにおいて、n+型拡散領域21はP
型基板11とホトダイオードを形成する。n+領域22
はBBDを構成する拡散領域であり、また第1ゲート電
極23に電圧を加えることによりn+領域21からチヤ
ージ電荷を移送する領域である。24,25はそれぞれ
絶縁物である。
First, in FIGS. 6A and 6B, the n+ type diffusion region 21 is P
A mold substrate 11 and a photodiode are formed. n+ area 22
is a diffusion region constituting the BBD, and is a region where charge charges are transferred from the n+ region 21 by applying a voltage to the first gate electrode 23. 24 and 25 are insulators, respectively.

電極26はMOで形成されn+領域21と電気的に接続
され、正孔阻止層27の電極ともなつている。第2ゲー
ト電極28は、BBDのゲートを構成している。さて、
第6図A,bに示した固体撮像素子の光情報読み込み動
作を第7図A,bを用いて説明する。
The electrode 26 is made of MO, is electrically connected to the n+ region 21, and also serves as an electrode of the hole blocking layer 27. The second gate electrode 28 constitutes the gate of the BBD. Now,
The optical information reading operation of the solid-state image sensor shown in FIGS. 6A and 6B will be explained using FIGS. 7A and 7B.

第6図aにこの素子を駆動するパルスパターンを同図b
にはn+領域21における電位変化を示した。
Figure 6a shows the pulse pattern for driving this element.
shows the potential change in the n+ region 21.

時間tにおいて第1ゲート電極23にVCHなる読み込
みパルスを印加すると領域21における電位は第7図b
に示した如く(VCH−VT)にチヤージされる。ここ
でVTはn+領域21,22および第1ゲート電極23
より構成されるFETの閾値電圧である。今、入射光が
あると光導電体19において電子正孔対が生成され、そ
れぞれ電極26,20に到達して電極26、すなわち領
域21の電位が低下する。この電位低下は入射光量に比
例し、1フイールド期間蓄積されるのでVSまで低下す
る。さらに時間T2において第1ゲート電極23にVC
Hを印加すると、その下の半導体基板11の表面電位は
上昇し、その結果n+領域21からn+領域22に電子
の移送が行なわれる。その結果、n+領域21の電位は
再び上昇し、(CH−T)となる。従つて、n+領域2
2に移動した電荷の総量は入射光の照度に対応する。こ
の様にして、n+領域22に読み込まれた光情報は第7
図aに示す転送パルスを、第2ゲート電極28に印加す
ることによつてBBD電荷転送の形で光情報は紙面の上
下方向に転送される。
When a read pulse VCH is applied to the first gate electrode 23 at time t, the potential in the region 21 changes as shown in FIG.
It is charged to (VCH-VT) as shown in FIG. Here, VT is the n+ region 21, 22 and the first gate electrode 23.
This is the threshold voltage of the FET consisting of Now, when there is incident light, electron-hole pairs are generated in the photoconductor 19, which reach the electrodes 26 and 20, respectively, and the potential of the electrode 26, that is, the region 21, decreases. This potential drop is proportional to the amount of incident light, and is accumulated for one field period, so that the potential decreases to VS. Furthermore, at time T2, VC is applied to the first gate electrode 23.
When H is applied, the surface potential of the underlying semiconductor substrate 11 increases, and as a result, electrons are transferred from n+ region 21 to n+ region 22. As a result, the potential of n+ region 21 rises again and becomes (CH-T). Therefore, n+ region 2
The total amount of charge transferred to 2 corresponds to the illuminance of the incident light. In this way, the optical information read into the n+ region 22 is
By applying the transfer pulse shown in Figure a to the second gate electrode 28, optical information is transferred in the vertical direction of the paper in the form of BBD charge transfer.

すなわち、ホトダイオードで光電変換された信号を2相
のクロツク信号で出力段に送り出すことが出来る。以上
、本発明は駆動部上の金属配線を絶縁膜で被つているの
で、透明電極の合わせずれ等による金属配線間短絡を防
止出米るのみならず、−絵素部と金属配線を狭く形成出
来、固体撮像素子の高集積化構成を容易にする等の効果
を有する。
That is, the signal photoelectrically converted by the photodiode can be sent to the output stage as a two-phase clock signal. As described above, since the metal wiring on the drive part is covered with an insulating film, the present invention not only prevents short circuits between the metal wiring due to misalignment of transparent electrodes, etc., but also - allows the pixel part and the metal wiring to be narrowed. This has the effect of facilitating the highly integrated configuration of solid-state imaging devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A,bは光導電膜を有する固体撮像素子の平面図
及び断面図、第2図は従来の同素子の不良発生説明図、
第3図,第5図は本発明の固体撮像素子の一実施例を示
す断面図、第4図A,bは同実施例の製造工程図、第6
図A,bは同実施例の要部拡大断面図及び平面図、第7
図A,bは同実施例の動作説明図である。 11・・・・・・半導体基板、12・・・・・・絵素部
、13・・・・・・駆動部、14・・・・・・金属配線
、15・・・・・・電極パツド部、16・・・・・・光
導電膜と類似の張張係数を有する絶縁膜、17・・・・
・・エツチング防止膜、18・・・・・・ホトレジスト
パターン、19・・・・・・光導電膜、20・・・・・
・透明電極、21,22・・・・・・n+拡散層、23
,28・・・・・・ゲート電極、24,25・・・・・
・絶縁膜、26・・・・・・電極、27・・・・・・正
孔阻止層。
FIGS. 1A and 1B are a plan view and a cross-sectional view of a solid-state image sensor having a photoconductive film, and FIG.
3 and 5 are cross-sectional views showing one embodiment of the solid-state imaging device of the present invention, FIGS. 4A and 4B are manufacturing process diagrams of the same embodiment, and FIGS.
Figures A and b are an enlarged sectional view and a plan view of the main parts of the same embodiment, and
Figures A and b are explanatory diagrams of the operation of the same embodiment. 11... Semiconductor substrate, 12... Picture element section, 13... Drive section, 14... Metal wiring, 15... Electrode pad Part 16...Insulating film having a tensile coefficient similar to that of the photoconductive film, 17...
...Etching prevention film, 18...Photoresist pattern, 19...Photoconductive film, 20...
・Transparent electrode, 21, 22...n+ diffusion layer, 23
, 28... gate electrode, 24, 25...
- Insulating film, 26... electrode, 27... hole blocking layer.

Claims (1)

【特許請求の範囲】 1 光学像を感知し転送する絵素部と、前記絵素部の前
記感知部分上に接続形成された光導電膜と、前記絵素部
を駆動する駆動回路部と、前記駆動回路部と外部接続用
パッド電極とを接続する導体配線とを有し、前記導体配
線上には前記光導電膜とほぼ同じ膨張係数を有する絶縁
物が形成されてなることを特徴とする固体撮像素子。 2 駆動回路部上に絶縁物を介して光導電膜が形成され
てなることを特徴とする特許請求の範囲第1項記載の固
体撮像素子。
[Scope of Claims] 1. A picture element section that senses and transfers an optical image, a photoconductive film connected and formed on the sensing section of the picture element section, and a drive circuit section that drives the picture element section; It has a conductor wiring that connects the drive circuit section and an external connection pad electrode, and is characterized in that an insulator having approximately the same expansion coefficient as the photoconductive film is formed on the conductor wiring. Solid-state image sensor. 2. The solid-state image pickup device according to claim 1, wherein a photoconductive film is formed on the drive circuit portion with an insulating material interposed therebetween.
JP53112589A 1978-09-12 1978-09-12 solid-state image sensor Expired JPS593068B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53112589A JPS593068B2 (en) 1978-09-12 1978-09-12 solid-state image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53112589A JPS593068B2 (en) 1978-09-12 1978-09-12 solid-state image sensor

Publications (2)

Publication Number Publication Date
JPS5538782A JPS5538782A (en) 1980-03-18
JPS593068B2 true JPS593068B2 (en) 1984-01-21

Family

ID=14590514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53112589A Expired JPS593068B2 (en) 1978-09-12 1978-09-12 solid-state image sensor

Country Status (1)

Country Link
JP (1) JPS593068B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60171A (en) * 1984-05-30 1985-01-05 Hitachi Ltd solid-state image sensor
JPS60210869A (en) * 1984-06-29 1985-10-23 Hitachi Ltd Solid-state image pickup element

Also Published As

Publication number Publication date
JPS5538782A (en) 1980-03-18

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