JPS5931108B2 - Three-digit separated information interrupt method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a positive digit separator information interrupt method for inserting strict separator information together with decimal point information into numerical information of a set number or an operation result number in, for example, an electronic calculator equipped with a print function. It is something. In general, when printing multi-digit numbers on electronic calculators with print functions, in order to make it easier to see numerical units, etc., one digit is used as a delimiter for each positive digit for numbers beyond the decimal point. A method has been adopted in which numerical information is output and printed by inserting it into an appropriate location, and more recently, the method of outputting and printing the maximum number of significant digits within a predetermined number of significant digits has been adopted. Therefore, if the Ξ digit separator is inserted as one-digit information, and there is a risk that the above numerical information may overflow, an electronic type with a print function that prints out without inserting the positive digit separator. Desktop calculators have also been developed, but conventional ones require special circuits such as delay circuits and flip-flops to carry up numerical values, and positions for each positive digit to insert strict delimited information between predetermined numerical values. A counter or the like for detection is required, which has the disadvantage of complicating the circuit configuration and increasing the cost. Furthermore, since the circuit is complicated, its control is also complicated. The present invention has been made in view of the above circumstances. For example, in an electronic calculator equipped with a print function, it is possible to simplify the configuration, and also to reliably interrupt strict delimited information. It is an object of the present invention to provide a strict separator information interrupt method that does not interrupt strict separator information if the contents of a register cause an overflow during execution. Embodiments of the present invention will be described below with reference to the drawings. In Fig. 1, reference numeral 1 denotes a circulating register that stores print information such as set numbers or calculation results in BCD code (binary coded decimal code), and internally includes a decimal point information storage section 2 that stores decimal point information as numerical information. It is equipped with a synchronization signal pulse (
(not shown), and outputs the contents sequentially starting from the least significant digit while shifting the contents to the right. The output of this circulating register 1 is returned to its own input side via a recirculating circuit consisting of a liner 7, an AND circuit 3, an OR circuit 4, a one-digit delay circuit 5 for timing adjustment, an AND circuit 6, and an OR circuit T. In addition, the output of the circulation register 1 is output from the AND circuit 8.
and is applied to the adder circuit 10 via the OR circuit 9. The output of this adder circuit 10 is a 3-input OR circuit 11,
and is returned to its own input side via the 3-input AND circuit 12 and the OR circuit 9, and is also sent to the circulation register 1 via the AND circuit 13, the OR circuit 4, the delay circuit 5, the AND circuit 6, and the OR circuit 7. . On the other hand, 14 is the circulation register 1 to the printing section (not shown).
A control unit that generates various control commands before transferring the contents of the control unit 14, which outputs a decimal point interrupt command S1, carry commands S2, S6, decimal point information insertion commands S3, (YO+Dp), Three-digit delimiter information insertion command S8, (
YD+gamma), digit down instruction S,, judgment instruction S5 to determine whether there is a value greater than or equal to the specified digit, OR circuit 1 for the logical sum of (YD/0)
5 to one input terminal of AND circuits 16 and 17, and to the first input terminal of a three-input AND circuit 18. Further, the control unit 14 further sends an instruction S4, (D1) to add the numerical value "4" to the contents of the decimal point counter, and an instruction to determine whether there is a numerical code in the most significant digit of the circular register 1. A command such as S7 (YM8E/O) is output to control a predetermined gate, which will be described later, to execute a predetermined operation. The other input terminal of the AND circuit 16 receives a digit timing signal TDP that designates the decimal point storage section 2, that is, a digit timing signal TDP that is generated every time the contents of the decimal point counter 2 are outputted from the output side of the circulation register 1.
'． is added to the other input terminal of the AND circuit 17, and a signal outputted from the Q side output terminal of the flip-flop circuit 19 is applied to the other input terminal of the AND circuit 17. The output signal of the AND circuit 17 is applied together with the output of the AND circuit 20 via an OR circuit 21 to each input terminal of an AND circuit 22, an AND circuit 23, and an AND circuit 24. Further, the output signals of the AND circuits 16 and 17 are applied to the AND circuit 8 via an OR circuit 25 and also to the AND circuit 12 via an inverter 26. This AND circuit 12 is further provided with a digit timing signal specifying the most significant digit of the circulating register 1, that is, a digit generated by the timing generator 27 every time the content of the most significant digit is output from the output side of the circulating register 1. Timing signal TE is applied via inverter 28. That is, since the most significant digit of the circulation register 4.1 stores code data indicating the sign, sign, etc. of the numerical information, the circulation of the adder circuit 10 at the time of specifying the code digit is controlled by applying the timing signal TE. It is designed to prohibit data input. The timing generator 27 also includes a digit timing signal TMSO that specifies the most significant digit of the area for storing numerical data in the circular register 1, and a decimal point digit timing signal T as described above.
P and various other timing signals necessary for this computer are generated under the control of the control section 14. The timing signal TMSD generated from the timing generator 27 is applied to the AND circuit 20 together with the command signal S7 output from the control section 14. The AND circuit 18 also has a decimal point counter designation timing signal TD at its second input terminal.
P is applied via an inverter 29, and an output signal from the Q side output terminal of the flip-flop circuit 19 is applied via an inverter 30 to the third input terminal. The output signal of the AND circuit 18 is combined with the -1 signal [containing a subtraction instruction to the adder circuit 10 and the code "000r"] outputted from the code generation circuit 31 in synchronization with the digit movement of the circular register 1, and the AND circuit 18. The code generation circuit 31 also outputs a +4 signal [including an addition instruction to the adder circuit 10 and the code ゛0100''゜], and this +4
The signal is sent from the control unit 14 to the decimal value by adding the value "
4] is applied to the AND circuit 33 together with the command signal S4 outputted at the step of adding
The output of 33 is applied to one input terminal of the adder circuit 10 via an OR circuit 34. A code detection circuit 35 for detecting a numerical value "O" code is connected to the adder circuit 10, and a flip-flop 19 is set by the detection signal of the code detection circuit 35. Further, the flip-flop circuit 19 is reset by a timing signal TE specifying the most significant digit of the register 1. Furthermore, the output signal on the Q side output side of the flip-flop circuit 19 is sent to an AND circuit 36.
, 3T are applied to each one input terminal. This AND circuit 3
The command signal S3 output from the control section 14 is applied to the other input terminal of the AND circuit 37, and the command signal S8 is applied to the other input terminal of the AND circuit 37. and AND circuit 36,3
Each of the 7 output signals is applied to a code generation circuit 38. This code generation circuit 38 outputs a decimal point code in response to the output signal of the AND circuit 36, and outputs a decimal point code to the AND circuit 37.
In response to the output of , a three-digit separator code is output, and both outputs are applied to the second and third input terminals of the OR circuit 11, respectively. The output of this OR circuit 11 is applied to the AND circuit 13 as described above, and is also applied to one input terminal of the AND circuit 39. The output of a delay type flip-flop 40 is applied to the other input terminal of the AND circuit 39.
The output of the AND circuit 39 is input to the circulation register 1 via the OR circuit 7. The output of the flip-flop 40 is further connected to the second circuit of the AND circuit via an inverter 41.
It is also input to the input terminal of . This flip-flop 40 is supplied with a timing signal TD for writing information into the decimal point storage section 2. On the other hand, AND circuits 22, 23, 24 to which the output of the OR circuit 21 is applied
Among them, the second input terminal of the AND circuit 22 has a control circuit 1s1.
The command signals S3 and S8 generated from the OR circuit 4
9, command signals S2, S3, and S6 are applied to the second input terminal of AND circuit 23, and command signal S9 is applied to the input terminal of AND circuit 24. The output signal from the output terminal between the least significant digit and the next second digit of the circular register 1 is applied to the third input terminal of the AND circuit 24. The output signal of the AND circuit 22 is applied to the AND circuit 42 together with the output signal from the OR circuit 11. The output signal of this AND circuit 42 is the fourth output signal of the OR circuit 4.
is input to the input terminal of Further, the output signal of the AND circuit 23 is applied to the other input terminal of the AND circuit 13, and the output of the AND circuit 24 is applied to the input terminal of the OR circuit 4. The outputs of the AND circuits 22, 23 and 24 are also applied to the input terminal of the AND circuit 3 via inverters 43, 44 and 45, respectively. The output of the OR circuit 21 is 3
It is also applied to a second input terminal of an input AND circuit 46, and command signals S5 and S7 generated from the control section 14 are applied to a first input terminal of this AND circuit 46 via an OR circuit 47. , the third input terminal is connected to the circular register 1.
The output signal from is added. And this AND circuit 4
The flip-flop 48 is set by the output signal of 6. This flip-flop circuit 48 is reset by a timing signal TE specifying the most significant digit of register 1. Furthermore, a set output signal from the Q side output terminal of the flip-flop circuit 48 is applied to the control section 14. Next, the operation in the above configuration will be explained. When the various command signals S1 to S9 are not output from the control section 14, the outputs of the AND circuits 22, 23, and 24 are O' (that is, the OR circuit 15, the AND circuit 20, and the OR circuit 21).
is "0", so the output of the AND circuit 22 is "0", and the AND circuits 23 and 24 output "0" because the command signals S1 to S9 are not output), and the outputs of the inverters 43, 44, and 45 are "1". The gate of the AND circuit 3 is opened.The gates of the AND circuits 13, 42, and 46 are closed.Therefore, the data stored in the circulation register 1 is transferred to the line 11, the gate of the AND circuit 3 is opened. Circuit 3 and OR circuit 4
, a delay circuit 5, an AND circuit 6, and an OR circuit 7. For example, after completing a certain operation [12345678
901.1] is obtained, the numeric value [123456] is stored in circulation register 1 as shown in Figure 3a.
789011] is input, and the decimal point data [1] is stored in the decimal point information storage section 2. In this state, the control unit 14 controls the first
When the command signal S for executing the step operation is output, it is applied to the AND circuit 16 via the OR circuit 15, so that the decimal point counter designation timing signal TDP shown in FIG. The signal is output from the OR circuit 25 as shown in FIG. 4e. The output signal of this OR circuit 25 is applied to the AND circuit 8 and opens its gate, so that the content "1" of the decimal point information storage section 2 read from the circulation register 1 at this time is transferred to the AND circuit 3, the OR circuit 4, and the delay circuit. 5, is inputted to the input side of the circulation register 1 via an AND circuit 6 and an OR circuit 7, and is also applied to an input terminal a of an adder circuit 10 via an AND circuit 8 and an OR circuit 9.
At this time, the input signal at the input end b of the adder circuit 10 is "0", so the content "1" of the decimal point storage section 2 is delayed by 4 bits (from [1+O]) and sent to the AND circuit 12. Added. The output time width of the OR circuit 25 is 4
Since the TDP signal is "0" at the time when the above content "1" is output from the adder circuit 10, the output of the AND circuit 16 is "O". Therefore, the output of the inverter 26 is "1" - and since the digit timing signal TE specifying the most significant digit of the register is not generated at this point, the output of the inverter 28 is also "1", and the gate of the AND circuit 12 is opened. , the output data "1" of the adder circuit 10 is applied to its own input side, that is, the input terminal a, via the AND circuit 12 and the OR circuit 9. On the other hand, at this point, the command signal S1 and the timing signal T specifying the decimal point storage section 2 are present. , is given at a different timing, the AND circuit 18 outputs the "1" signal, and the gate of the AND circuit 32 is opened. Therefore, the [-1] signal [subtraction instruction to the adder circuit and numerical code "'0001"] output from the code generation circuit 31 is sent to the input terminal b of the adder circuit 10 via the AND circuit 32 and the OR circuit 34. It is added in synchronization with the right shift operation of the contents of circular register 1. As a result, the adder circuit 10 performs a subtraction operation of [1-1]. As a result, the output data of the adder circuit 10 is

It becomes [0]. The code detection circuit 35 detects this state and sets the flip-flop circuit 19. If the decimal point information above is
1'', the adder circuit 10 performs one [-1] operation. Therefore, the content decimal point information [1] of the circulation register 1 and the content [1] of the lowest digit are the AND circuit 3,
The signal is input to the delay circuit 5 through the OR circuit 4. The flip-flop circuit 19 is set by the output of the code detection circuit 35, and at this time, the control section 14 outputs a carry operation command signal S2 for the second step operation, and the AND circuit 17 is opened. Since the output of the AND circuit 17 is applied to the AND gate 23 via the OR circuit 21, the logical condition of the AND circuit 23 is satisfied, and the AND circuit 23 outputs a "1" signal as shown in FIG. 4e. The inverter 44 closes the gate of the AND circuit 3, that is, the normal recirculation, and opens the gate of the AND circuit 13. As a result, the output data of the adder circuit 10, that is, the numerical value "0" is transmitted to the OR circuit 11, the AND circuit 13, and the OR circuit. 4 through delay circuit 5
At the same time, the content "1" written in the delay circuit 5 is written to the input side of the circular register 1 via an AND circuit 6 and an OR circuit 7. At the same time, the "1" signal from the AND circuit 17 opens the gate of the AND circuit 8 via the OR circuit 25, and closes the gate of the AND circuit 12 via the inverter 26, closing the feedback loop of the adder circuit 10. The contents of digits beyond the decimal point output from the circular register 1 are sequentially sent to an AND circuit 8 and an OR circuit 9.
is input to the adder circuit 10 via the adder circuit 1.
After a 4-bit delay at 0, OR circuit 11, AND circuit 1
3. The numerical value "O" is sequentially written into the circular register 1 via the OR circuit 4, the delay circuit 5, the AND circuit 6, and the OR circuit 7. As a result, the contents of the circulation register 1 become [1234567890101] as shown in FIG. 3b. Further, the contents of the decimal point storage section 2 remain unchanged and remain [1]. In this way, the carry operation that is the second step is executed, and the process moves to the next third step (S3 in FIG. 2). When entering this third step, the command signal S3 is outputted by the control section 14, and this S3 is applied to the AND circuit 16 via the OR circuit 15, so that the decimal point is The contents of the storage section 2 are introduced into the adder circuit 10 via the AND circuit 8 and the OR circuit 9,
In synchronization with the digit right shift operation of the contents of circular register 1.
It is subtracted by 1. And the above subtraction result is

When the signal becomes [0], the code detection circuit 35 outputs a detection signal and the flip-flop 19 is set. At this time, the content decimal point information [1] of the circulation register 1 is input to the circulation register 1, and the content [1] of the least significant digit is input to the delay circuit 5, respectively. When the flip-flop 19 is set, the AND circuit 17 is opened, and the output of the AND circuit 17 causes the AND circuit 23 to output the output signal "1" as described above, and the gate of the AND circuit 3 is closed. The normal recirculation of is closed and the AND circuit 13 is opened. On the other hand, at this time, that is, when the command signal is being output, when the flip-flop 19 is set, the output signal "1" is output from the AND circuit 36 and applied to the code generation circuit 38.
A decimal point code signal [x], for example, "1011" is output from. As a result, since the output of the adder circuit 10 is the numeric value "O" code at this point, the decimal point code signal is sent to the OR circuit 10.
1, is written to the delay circuit 5 through the AND circuit 13 and the OR circuit 4, and the content [1] written in the delay circuit 5 is written to the input side of the circulation register 1. Thereafter, in the same operation as explained in the first step, the contents of the digits above the decimal point pass through the adder circuit 10, the OR gate 11, and the AND circuit 13, and are stored in the circulation register 1 as a decimal point code [x].
are written sequentially. As a result, the contents of circulation register 1 are as shown in FIG.
]. In this way, the third step, the decimal point code insertion step, is completed, and the next fourth step (the second step) is completed.
Moving on to Figure S4). In this fourth step, a value 4 is added to the content [1] of the decimal point storage section 2 in the circular register 1. That is, the command signal S is sent from the control unit 14.
4 is output, this command signal S4 is applied to the AND circuit 16 via the OR circuit 15, and the timing signal TD
Since P is output, ``1'' is output from the AND circuit 16, and the contents [1] of the decimal point storage section 2 are transferred from the circular register 1 to the input of the adder circuit 10 in the same manner as explained in the first step. Added to the ends. At this time, the AND circuit 33 is opened by the command signal S4, and the numerical code 4' output from the code generation circuit 31 is applied to the input terminal b of the adder circuit 10 via the AND circuit 33 and the OR circuit 34. Therefore, in the adder circuit 10, the decimal point content [
1] and the numerical value 4 are performed. On the other hand, the flip-flop circuit 40 reads the timing signal TDP in synchronization with the clock pulse 40 outputted at the 4th bit of each digit, and outputs the timing signal TDP with a delay of 4 bits, that is, one digit. The output of this flip-flop circuit 40 and the command signal S
4 opens the gate of the AND circuit 39, and the addition result [5] ([1]+[4]) in the adder circuit 10 is sent to the circulation register 1 via the AND circuit 39 and the OR circuit 7.
and written into the decimal point information storage section 2. As a result, the contents of the circulation register 1 become as shown in FIG. 3d. In this way, the fourth step is completed, and the next step is the fifth step. This fifth step is a step for determining whether or not the contents stored in the decimal point storage section 2 in the circulating register 1 have a numerical code written in more than the specified digit. If there is no three-digit delimiter code, there is no need to write the three-digit delimiter code to a predetermined digit in the circular register 1, and the process can be terminated without performing the operation of inserting the three-digit delimiter code, so this determination is made. That is, when the command signal S5 is output from the control section 14, the contents [5] of the decimal point storage section 2 are first introduced into the adder circuit 10 by the same operation as explained in the first step, and the adder circuit 10 The contents [5] are subtracted by 1 in synchronization with the digit right shift operation of the contents of the circular register 1, and when the contents become zero, the flip-flop 19 is set. Since the flip-flop 19 is set, the AND circuit 17 is opened and its output signal "1" is applied to the AND circuit 46 via the OR circuit 21, so that the gate of the AND circuit 46 is opened. That is, the code signal of the contents of the circular register 1 of digits higher than or equal to the digit designated by the contents "5" of the decimal point storage section 2 (contents of the 6th digit and higher) is applied to the flip-flop circuit 48 through the AND circuit 46. This flip-flop circuit 48 is set by outputting an output signal of "1" from the AND circuit 46 if there is a numerical value in the contents of the circulation register 1.In this embodiment, as shown in FIG. Since a numerical code has been written, the flip-flop 48 is set when the numerical code is output from the output side of the circular register 1, and the set output signal is sent to the control section 14. After receiving the set output signal, the command signal S
It outputs 6 and enters the operation of the 6th step. This command signal S
When 6 is output, the contents of the decimal point storage section 2, that is, the contents of the circular register 1 of the digit or more specified by [5] are shifted up by one digit in the same manner as described in the second step. As a result, the contents of circulation register 1 are as shown in Figure 3 e [1234
56780901×1], and the process moves to the next seventh step (S7 in FIG. 2). In this seventh step, the control unit 14 outputs the command signal S7, and the timing generator 27 outputs the timing when the contents of the most significant digit of the numerical storage area of the circular register 1 is output from the output side of the circular register 1. Signal TMSD is output. Therefore, at the above timing, the AND circuit 20 outputs the output signal "1", and this output signal "1n" is applied to the AND circuit 46 via the OR gate 21. As a result, the gate of the AND circuit 46 is opened and the circulation starts. The code signal of the most significant digit of the numerical storage area of register 1 is applied to the flip-flop circuit 48 through the AND circuit 46.Then, depending on whether the flip-flop circuit 48 is set or not, the code signal of the most significant digit of the numerical storage area of the circular register 1 is applied. It is determined whether a numerical code has been written in the most significant digit.In the case of this embodiment, as shown in FIG. 3e, there is no numerical value in the most significant digit, so the process proceeds to the next eighth step. In the eighth step, when the command signal S8 is output from the control section 14, the three-digit delimiter code Y (for example, "1110") is output from the code generation circuit 38 in the same manner as explained in the third step. ) is inserted in the fifth digit between the numerical values "8" and "9" of the numerical information stored in the circular register 1, and as shown in FIG.
Y901×1]. Next, the process returns to the fourth step, and by the above-described operation, the numerical value [4] is added to the content [5] of the decimal point storage section 2, and the content is

[9] becomes. In the fifth step, the contents of the decimal point storage section 2 updated in the previous step 4 are

It is determined whether there is a numerical value in the digits specified by [9] or higher, that is, in the 9th digit or higher of the circular register 1. In the case of this embodiment, as shown in FIG.
Since there is a numerical value in the 9th digit or above, proceed to the sixth step. Thereafter, the operations of the 6th, 7th, and 8th steps are performed in the same manner as described above, and when the operations of the 4th, 5th, and 6th steps are performed again, the state of the circulating register 1 becomes as shown in FIG. 3g. There is a numerical value in the most significant digit of circular register 1 [12
0345Y678Y90×1]. In this state, the process proceeds to the seventh step shown in FIG. 2, S7. In this seventh step, as described above, in response to the command signal S7 from the control section 14 and the timing signal TMSD output from the timing generator 27, the AND circuit 20 sets the contents of the most significant digit of the circulation register 1 to the output side of the register 1. The gate of the AND circuit 46 is opened by the "1" output signal of the AND circuit 20, and the code signal of the content [1] of the most significant digit of the circulation register 1 is added to the flip-flop circuit 48. The flip-flop circuit 48 is set. The set signal of this flip-flop circuit 48 is
Sent to 4. This causes the control section 14 to output the command signal S.
9 is output, so the process goes to step S9 in FIG.
In order to restore the contents of the third and higher digits to their original values, a down-down operation of one digit is executed. That is, in the ninth step, when the command signal S9 is output from the control section 14, the contents [13] of the decimal point storage section 2 are introduced into the adder circuit 10 by the same operation as in the carry step of the sixth step. and this value [13
] is sequentially subtracted by 1 in the adder circuit 10 in synchronization with the shift of the contents of the circular register 1 to the right. When the result of this subtraction becomes zero, the code detection circuit 35
A detection signal is outputted, the flip-flop circuit 19 is set, and the set signal causes the AND circuit 17 to output an output signal "1". The output signal "1" of this AND circuit 17 is applied to the AND circuit 24 via the OR circuit 21. On the other hand, since the command signal S9 is applied to this AND circuit 24, the gate of the AND circuit 24 is opened. At this time, the "0" signal, which is the inverted signal of the output signal "1" of the AND circuit 24, is applied to the AND circuit 3 via the inverter 45, and the AND circuit 3 is closed, so that the normal circulation loop of the circulation register 1 is Closed. Therefore, the contents of the circulation register 1 are processed at this point, that is, from the contents of the 13th digit and above, from the output section of the digit one digit higher than the output section of the circulation register 1, to the AND circuit 24, the OR circuit 4, and the delay circuit 5. , an AND circuit 6, and an OR circuit 7, and are sequentially returned to the input side of the circulation register 1. As a result, the contents of the 13th and above digits of the circular register 1 are shifted to the right by one digit, that is, are down-shifted by one digit, and the down-down operation is completed as shown in FIG. 3h. In this embodiment, numerical information and decimal point position information are stored in the same register, but it is of course possible to store both in separate registers, and in this embodiment, decimal point position information Although an example has been shown in which a code detector detects a zero code by sequentially subtracting , the present invention is not limited to this, and it goes without saying that control can be performed to detect a specific value. In short, the present invention is not limited to the above embodiments, but
Various modifications may be made without departing from the spirit of the invention. As described above, according to the present invention, when interrupting information separated by three digits in a computer equipped with a print function, for example, the delay element of the adder circuit is skillfully used and the numerical code is placed in the most significant digit of the register. This method inserts three-digit delimiter information between numerical information while determining whether or not there is a
It is possible to provide a three-digit delimiter information interrupt method that can simplify the configuration by omitting a circuit, can reliably process three-digit delimiter information, and can output the maximum number of significant digits.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a flowchart to explain the operation of the block diagram, and Fig. 3 shows the contents of a circulation register to explain this embodiment. figure,
FIG. 4 is a time chart for explaining the operation of the same embodiment. 1... Circulation register, 10... Adder circuit, 14... Control section, 19... Flip-flop circuit, 27... Timing generator , 31, 38... code generation circuit, 48...
...flipflop.

Claims (1)

[Claims] 1. A register for storing numerical information to be output, decimal point information storage means for storing decimal point position information of the numerical information in a code, means for adding a specific value to the decimal point position information of this means, and means for incrementing the contents of the register above the digit specified by the information specified by the above register by one digit;
When a carry operation is performed by this carry means, there is a means for determining whether or not a numerical code exists in the most significant digit of the register, and a means for determining whether or not a numerical code exists in the most significant digit of the register, and a means for determining whether or not a numerical code exists in the most significant digit of the above register, and if it is determined that there is no numerical code by this determining means, the above decimal point position. A means for writing a three-digit separator code in the digit position of the register specified by the information, and if the above judgment means determines that there is a numerical value, prohibits the insertion of the three-digit separator code and lowers the carried content. A triple-digit information interrupt method characterized by comprising: