JPS5931213B2 - How to bond a semiconductor wafer to a lap surface plate - Google Patents
How to bond a semiconductor wafer to a lap surface plateInfo
- Publication number
- JPS5931213B2 JPS5931213B2 JP52139064A JP13906477A JPS5931213B2 JP S5931213 B2 JPS5931213 B2 JP S5931213B2 JP 52139064 A JP52139064 A JP 52139064A JP 13906477 A JP13906477 A JP 13906477A JP S5931213 B2 JPS5931213 B2 JP S5931213B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- surface plate
- semiconductor wafer
- lap
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Description
【発明の詳細な説明】
この発明は多数の半導体素子を作り込んだ半導体ウェハ
の厚みを調整するために、上記半導体ウェハをラップ定
盤に接着する方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method of bonding a semiconductor wafer to a lapping surface plate in order to adjust the thickness of a semiconductor wafer on which a large number of semiconductor elements are fabricated.
一般に半導体素子を製造する際には、第1図に示すよう
に、1枚の半導体ウェハ1内に多数の半導体素子2を作
り込んだ後、半導体ウェハ1を分割して個々の半導体素
子2を得るのが普通である。Generally, when manufacturing semiconductor devices, as shown in FIG. It is normal to get
ところで半導体素子2は150μ前後の厚みに仕上げる
ことが望ましいが、ウェハ1中への半導体素子2の形成
途中の熱処理工程或は化学処理工程に於りる破損を防止
する為、通常は300μ以上の厚みのウェハ1を用い、
半導体素子2を形成した後、ウェハ1の裏面部の不要な
部分1aを削りとつて所要の150μ厚を得るのが普通
である。この削り取り工程はラッピングによつて行なわ
れるので、通常バックラッピングと呼んでいる。このよ
うなバックラッピングを行うためにウェハをラップ定盤
に接着する従来の方法は、第2図に示すように、ラップ
定盤4の接着面5に熱可塑性の接着剤6を塗布し、半導
体ウェハ1の表面をこの接着面に密着させた後、これを
加熱処理することによりラップ定盤4のウェハ1を固定
させるものであつた。以上のようにしてラップ定盤4に
接着剤6にて固定されたウェハ1の裏面は、ラップ盤と
すり合わされて所定の寸法までラッピングされる。By the way, it is desirable to finish the semiconductor element 2 to a thickness of about 150μ, but in order to prevent damage during the heat treatment or chemical treatment process during the formation of the semiconductor element 2 in the wafer 1, it is usually finished with a thickness of 300μ or more. Using a wafer with a thickness of 1,
After the semiconductor element 2 is formed, the unnecessary portion 1a of the back surface of the wafer 1 is usually removed to obtain the required thickness of 150 μm. Since this scraping process is performed by lapping, it is usually called back lapping. The conventional method of bonding a wafer to a lap surface plate for performing such backlapping is as shown in FIG. After the surface of the wafer 1 was brought into close contact with this adhesive surface, the wafer 1 was fixed on the lapping surface plate 4 by heat-treating the surface. The back side of the wafer 1 fixed to the lapping platen 4 with the adhesive 6 in the manner described above is rubbed against the lapping plate and lapped to a predetermined size.
しかし乍ら、上記のような方法では、ラップ定盤4に接
着剤6をいちいち塗布することに多大の工数を要するば
かりでなく、ウェハ1を定盤4に密着させる際に、表面
配線部3が硬いラップ定盤4に直接触れて損傷を受りる
危険がある。J この発明はこのような点に鑑みてなさ
れたもので、繊維素よりなり熱可塑性接着剤を含浸させ
たシートをラップ定盤と半導体ウェハの間に介在させて
加熱圧着することにより、ラップ定盤へのウェハの接着
工数を削減し、しかも接着時の配線面;に対する損傷を
防止出来るようにしたものである。However, in the above method, not only does it take a lot of man-hours to apply the adhesive 6 to the lapping surface plate 4 one by one, but also the surface wiring portion 3 There is a risk of damage due to direct contact with the hard lap surface plate 4. J This invention was made in view of the above-mentioned points, and a sheet made of cellulose impregnated with a thermoplastic adhesive is interposed between a lap surface plate and a semiconductor wafer and bonded under heat, thereby achieving lap fixation. This reduces the number of steps needed to bond the wafer to the board, and also prevents damage to the wiring surface during bonding.
以下、この発明の一実施例を第3図に基づいて説明する
。先ずラップ定盤4の接着面に、繊維素よりなり熱可塑
性接着剤を含浸させた接着シートTを乗せ、Oその上に
ウェハ1の電極を形成した表面を接着シート7に密着さ
せるように乗せ、これを加熱された錘8で押圧する。An embodiment of the present invention will be described below with reference to FIG. First, an adhesive sheet T made of cellulose and impregnated with a thermoplastic adhesive is placed on the adhesive surface of the lap surface plate 4, and the surface of the wafer 1 on which the electrodes are formed is placed on top of it so that it is in close contact with the adhesive sheet 7. , this is pressed with a heated weight 8.
すると接着シートTに含浸された熱可塑性接着剤がウェ
ハ1側とラップ定盤4側の両側に溶出し、ウェハ1が接
着シート7を介”5 してラップ定盤4へ結合される。
その後、錘8を取り去つて上記溶出した接着剤9をウェ
ハ1およびラップ定盤4とともに冷却すると、ウェハ1
がラツプ定盤4に強固に接着される。このようにして接
着されたウエハ1は、従来と同様にラツプ盤とすり合わ
され、所定のバツクラツピングBj行われる。以上述べ
たようにこの発明の方法によれば、従来方法のようなラ
ツプ定盤の表面に接着剤を塗布するための工数を削減す
ることが可能であるとともに、バツクラツピングの工程
中に発生するウエハの配線面の損傷を防止することB3
できる効果がある。Then, the thermoplastic adhesive impregnated into the adhesive sheet T is eluted to both sides of the wafer 1 and the lap platen 4, and the wafer 1 is bonded to the lap platen 4 through the adhesive sheet 7.
Thereafter, the weight 8 is removed and the eluted adhesive 9 is cooled together with the wafer 1 and the lap surface plate 4, and the wafer 1
is firmly adhered to the lap surface plate 4. The wafer 1 bonded in this manner is rubbed against a lapping machine in the same manner as in the prior art, and a predetermined back lapping Bj is performed. As described above, according to the method of the present invention, it is possible to reduce the number of man-hours required to apply adhesive to the surface of the lap surface plate unlike the conventional method, and it is also possible to reduce the number of steps required to apply adhesive to the surface of the lap surface plate, which is required in the conventional method. To prevent damage to the wiring surface of B3
There is an effect that can be achieved.
なお上述の実施例においては、バツクラツピングをする
ウエハとしてトランジスタを作り込んだウエハを例にと
つて説明したが、バイポーラICやモスCを作り込んだ
ウエハのバツクラツピングに適しても同様の効果を奏す
る。In the above-described embodiments, a wafer in which transistors are formed is used as an example of a wafer to be back-clapped, but the same effect can be obtained even if the present invention is suitable for back-clapping a wafer in which bipolar ICs or MOS Cs are formed.
第1図は多数のトランジスタを作り込んだ半導体ウエハ
を示す部分断面図、第2図は従来方法を示す断面図、第
3図はこの発明の一実施例を示す断面図である。
図において、1は半導体ウエハ、4はラツプ定盤、7は
接着シート、8は錘、9は熱可塑性接着剤である。FIG. 1 is a partial sectional view showing a semiconductor wafer in which a large number of transistors are fabricated, FIG. 2 is a sectional view showing a conventional method, and FIG. 3 is a sectional view showing an embodiment of the present invention. In the figure, 1 is a semiconductor wafer, 4 is a lap surface plate, 7 is an adhesive sheet, 8 is a weight, and 9 is a thermoplastic adhesive.
Claims (1)
ートを介して半導体ウェハをラップ定盤上に載置し、次
いで上記半導体ウェハを上記ラップ定盤に対して加熱加
圧することを特徴とする半導体ウェハのラップ定盤への
接着方法。1. A semiconductor wafer is placed on a lapping platen via an adhesive sheet made of cellulose and impregnated with a thermoplastic adhesive, and then the semiconductor wafer is heated and pressed against the lapping platen. A method of adhering semiconductor wafers to a lap surface plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52139064A JPS5931213B2 (en) | 1977-11-18 | 1977-11-18 | How to bond a semiconductor wafer to a lap surface plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52139064A JPS5931213B2 (en) | 1977-11-18 | 1977-11-18 | How to bond a semiconductor wafer to a lap surface plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5471980A JPS5471980A (en) | 1979-06-08 |
| JPS5931213B2 true JPS5931213B2 (en) | 1984-07-31 |
Family
ID=15236643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52139064A Expired JPS5931213B2 (en) | 1977-11-18 | 1977-11-18 | How to bond a semiconductor wafer to a lap surface plate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5931213B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4512113A (en) * | 1982-09-23 | 1985-04-23 | Budinger William D | Workpiece holder for polishing operation |
| JPS6290944A (en) * | 1985-10-17 | 1987-04-25 | Toshiba Ceramics Co Ltd | Silicon wafer bonding device |
| DE102008028213A1 (en) * | 2008-06-06 | 2009-12-10 | Gebr. Schmid Gmbh & Co. | Method for attaching a silicon block to a support therefor and corresponding arrangement |
-
1977
- 1977-11-18 JP JP52139064A patent/JPS5931213B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5471980A (en) | 1979-06-08 |
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