JPS5931228B2 - MOS - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a silicon gate type MOS field effect semiconductor device.

Conventionally, silicon gate type MOS field effect semiconductor devices have generally been manufactured by a method as shown in FIG.

That is, first, a thick silicon dioxide film 2 and a thin silicon dioxide film that will become a gate insulating film are grown on the surface of a semiconductor substrate 1, and polycrystalline silicon 4 that will become a gate electrode is used as a wiring region on the thin silicon dioxide film 3. Polycrystalline silicon 5 is formed on thick silicon dioxide film 2 (see FIG. 1a).
). Next, the thin silicon dioxide film is removed by etching using the polycrystalline silicon 4 and 5 as a mask (FIG. 1b). In this etching process, the surface of the thick silicon dioxide film 2 is also etched, and the etching solution flows around the side edges of the silicon dioxide film covered with the polycrystalline silicon 4 and 5 to the bottom of the polycrystalline silicon 4 and 5. Constriction 6, T formed. Next, an impurity having a polarity opposite to that of the semiconductor substrate 1 is diffused from the exposed surface of the semiconductor substrate to form source and drain diffusion layers 8 and 9. Next, silicon dioxide films 12, 13, 10 and 11 are formed on the surfaces of the diffusion layers 8 and 9 and the polycrystalline silicon 4 and 5, respectively (FIG. 1c).
At this time, since the aforementioned constrictions 6, T are formed in the silicon dioxide film under the side edges of the polycrystalline silicon 4, 5, the newly grown silicon dioxide film 12, 13, 10,
11 as well, constrictions 14 and 15 as shown in FIG. The constriction 1 at the lower side edge of the polycrystalline silicon layer 4 used as a gate electrode
When 4 is used as a MOS field effect transistor,
This causes a significant decrease in the breakdown voltage between the gate electrode 4 and the source and drain diffusion layers 8 and 9. Also, a constriction 15 at the lower side edge of the polycrystalline silicon 5 used as a wiring region
When a metal wiring layer is formed across the top of the polycrystalline silicon 5, the metal wiring layer is likely to be disconnected at the constricted portion 15, resulting in a significant decrease in the yield rate of devices. )
The present invention completely eliminates the constriction of the silicon dioxide film that occurs at the lower side edge of polycrystalline silicon in the conventional manufacturing method of a silicon gate type MOS field effect semiconductor device, and improves the breakdown voltage between the gate, source, and drain. The present invention provides a method for manufacturing a silicon gate type MOS field effect semiconductor device that can prevent disconnection of a metal wiring layer that crosses polycrystalline silicon.

Hereinafter, the present invention will be described in detail based on examples and with reference to FIG. 2.

First, a thick silicon dioxide film 22 of about 1.0 μm and a thin silicon dioxide film 23 of about 1000 layers to be used as a gate insulating film are formed on the surface of an N-type silicon substrate 21, and a multilayer silicon dioxide film 23 of about 0.8 μm thick to be used as a gate electrode is formed. crystalline silicon 24
A polycrystalline silicon 25 of about 0.8 μm, which will be used as wiring, is formed on the thick silicon dioxide film 22 (FIG. 2a).

Next, by processing in a high-temperature phosphorus atmosphere, phosphorus is diffused into the polycrystalline silicon 24, 25 to form polycrystalline silicon layers 27, 28 containing high concentration of phosphorus. At the same time, silicon dioxide films 22, 23 and polycrystalline silicon 24
, 25 is formed with a phosphor glass layer 26 (second
Figure b). As for the phosphorus diffusion conditions, for example, the thickness of the polycrystalline silicon layers 27 and 28 containing high concentration of phosphorus is reduced to 0.3μ by heat treatment in a phosphorus atmosphere at 900° C. for several minutes, and the thickness of the phosphorus glass layer is set to approximately 500λ. It is possible to control the Next, the phosphor glass layer 26 is removed by etching.
As a result, about 500 chunks of the thin silicon dioxide film 23 not covered with the polycrystalline silicon 24 are formed (FIG. 2c).
Next, the surface of the silicon dioxide film is removed by etching approximately 500λ, and the thin silicon dioxide film 23 that is not covered with the polycrystalline silicon 24 is removed to define exposed openings 29 and 30 in the silicon substrate ( Figure 2 d).

In this etching process, a thick silicon dioxide film 22 is removed.
It is also etched by about 500λ. In addition, in this etching process, the silicon dioxide film below the side edges of the polycrystalline silicon is also etched in the lateral direction, resulting in constrictions 31,
32.

This constriction has about 300 people. Next, the polycrystalline silicon layers 27 and 28 containing phosphorus at a high concentration of 3 degrees are removed by etching (FIG. 2e). In this etching process, the openings 29 and 30 of the silicon substrate and the polycrystalline silicon 24 and 25 that do not contain a high concentration of phosphorus are also exposed to the etching atmosphere; Polycrystalline silicon containing a high concentration of phosphorus has an etching rate several to several tens of times faster than silicon that does not contain a high concentration of phosphorus, so under appropriate conditions, polycrystalline silicon containing a high concentration of phosphorus layer 27,2
When etching approximately 0.3μ of the silicon substrate, the thickness of the openings 29 and 30 of the silicon substrate and the polycrystalline silicon 24 and 25 that do not contain a high concentration of phosphorus is etched away to a thickness of several hundred Å.
It is easy to do the following.

In this etching step, the polycrystalline silicon layers 27 and 28 containing high concentration phosphorus, which were protruding above the constrictions 31 and 32 of silicon dioxide below the side edges of the polycrystalline silicon layer, are etched away. Polycrystalline silicon 24, 25
The constriction of the silicon dioxide film underneath is eliminated. Next, from the openings 29 and 30 of the silicon substrate, the silicon substrate 2 is
P-type impurity is diffused into the inside of 1 to form P-type diffusion layers 33 and 34.
is formed, and then treated in a high-temperature oxidizing atmosphere to cover the openings 29 and 30 with silicon dioxide films 35 and 36, and simultaneously cover the polycrystalline silicon 24 and 25 with silicon dioxide films 37 and 38 ( Figure 2 f).

In this step, the silicon dioxide films 35, 36 and the silicon dioxide film 37 and the silicon dioxide film 22 and the silicon dioxide film 38 are smoothly connected, and the polycrystalline silicon 24,
Since the silicon dioxide film on the side edges of the electrode 25 never becomes constricted, the breakdown voltage between the polycrystalline silicon gate electrode 24 and the source/drain diffusion layers 33 and 34 is significantly improved. When a metal wiring layer made of aluminum or the like is installed across the upper part of the polycrystalline silicon 25, disconnection defects are extremely unlikely to occur in the silicon dioxide film 32' covering the side edges of the polycrystalline silicon. In the above embodiments, a P-channel type silicon gate MOS field effect semiconductor device has been described, but the manufacturing method of the present invention can also be applied to an N-channel type device.

In that case, the semiconductor substrate 21 should be a P-type semiconductor, and the source
The drain diffusion layers 33 and 34 may be N-type diffusion layers.
Further, in the above embodiment, it is also possible to perform the etching removal of the phosphor glass layer 26 and the etching removal of the thin silicon dioxide film 23 in the same process. As described above, according to the manufacturing method of the present invention, a silicon gate type MO with no constriction of the silicon dioxide layer at the lower part of the side edge of polycrystalline silicon can be obtained.
According to the present invention, it is possible to obtain an S field effect semiconductor device, and therefore, according to the present invention, the breakdown voltage between the gate and source/drain diffusion layers is significantly improved, and the silicon has the characteristics that there are very few disconnection defects in the metal wiring layer. A gate type MOS field effect semiconductor device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the process order for explaining a conventional manufacturing method, and FIG. 2 is a cross-sectional view of the process order for explaining the manufacturing method of the present invention. 1... Semiconductor substrate, 2... Thick silicon dioxide film, 3... Thin silicon dioxide film to serve as gate insulating film, 4... Polyester for gate electrode. Crystalline silicon, 5...Polycrystalline silicon for wiring, 6.-
...Constriction at the bottom of the polycrystalline silicon side edge for gate electrode, 7...Constriction at the bottom of the polycrystalline silicon side edge for wiring, 8, 9... Source/drain diffusion layer, 1
0... Silicon dioxide film covering polycrystalline silicon for gate electrode, 11... Silicon dioxide film covering polycrystalline silicon for wiring, 12, 13... Source/drain diffusion Silicon dioxide film covering the layer, 14...
...Constriction of the silicon dioxide film at the bottom of the side edge of polycrystalline silicon for gate electrode, 15...Constriction of silicon dioxide film at the bottom of the side edge of polycrystalline silicon for wiring, 21...
... Semiconductor base, 22 ... Thick silicon dioxide film, 23 ... Thin silicon dioxide film serving as gate insulating film, 24 ... Polycrystalline silicon for gate electrode, 25・・・・・・Polycrystalline silicon for wiring, 26
... Phosphorus glass layer, 27 ... Polycrystalline silicon layer containing high concentration of phosphorus formed on the surface of polycrystalline silicon for gate electrode, 28 ... For wiring Polycrystalline silicon layer containing high concentration of phosphorus formed on the surface of polycrystalline silicon, 29, 30... exposed opening of semiconductor substrate, 31... polycrystalline silicon layer for gate electrode; Constriction at the lower side edge of crystalline silicon, 32...Constriction at the lower side edge of polycrystalline silicon for wiring, 32'...
...Silicon dioxide film covering the side edges of polycrystalline silicon for wiring, 33, 34... Source/drain diffusion layer, 35, 36...... On the surface of the source/drain diffusion layer Formed silicon dioxide film, 37...
・Silicon dioxide film covering the surface of polycrystalline silicon for gate electrode, 38...Silicon dioxide film covering the surface of polycrystalline silicon for wiring.

Claims (1)

[Claims] 1. A step of selectively forming polycrystalline silicon on a silicon dioxide film provided on the surface of a semiconductor substrate, a step of forming a region containing a high concentration of phosphorus on the surface of the polycrystalline silicon, and a step of forming a region containing high concentration of phosphorus on the surface of the polycrystalline silicon. a step of exposing a part of the surface of the semiconductor substrate by selectively etching away the silicon dioxide film using a mask; a step of etching away a region of the polycrystalline silicon surface containing a high concentration of phosphorus; A method for manufacturing a MOS field effect semiconductor device, comprising the step of introducing impurities into the interior of the semiconductor substrate through the exposed surface.