JPS5931230B2 - Method for manufacturing MOS type semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MOS type semiconductor integrated circuit which requires a short channel and high breakdown voltage.

In recent years, MOS type semiconductor integrated circuits have been required to have higher density, and it has become necessary to reduce the element dimensions.

On the other hand, in a MOS transistor, as the gate length becomes shorter, the contribution of the drain depletion layer charge increases, causing problems such as a decrease in the threshold voltage Vt and deterioration of the source-drain breakdown voltage.

The present invention is an n-channel MO in which an extremely thin n-type region is formed in a part of the drain region to prevent deterioration of breakdown voltage and Vt.
The present invention provides a method for manufacturing an S integrated circuit.

Next, a conventional example of a method for manufacturing a MOS transistor, which is a component of a MOS integrated circuit, will be described.

FIG. 1 shows the most common manufacturing example, and an N-channel type will be explained. First, a field oxide film 2 is formed on a p-type silicon substrate 1 to a thickness of about 1 μm by thermal oxidation.
Next, an opening is made in the oxide film 2 in a region where a transistor is to be formed, and a gate oxide film 3 is formed to a thickness of about 1000Λ. Further, about 5000 polycrystalline silicon 4 is deposited on 2 by thermal decomposition of SiH4. The condition of the kofu is shown in Figure 1A. Next, using a photoresist, the polycrystalline silicon is removed except for the gate region 41 and wiring region 42.

Next, the gate oxide film is etched using the gate 41 as a mask, and then phosphorus is diffused to a depth of approximately 1 μm to form N-type source/drain regions 5, 5'. At this time, polycrystalline silicon 41, 42 is etched. Phosphorus is also diffused into
This state is shown in B. Next, a silicon oxide film 6 is formed on the entire surface to a thickness of about 5000λ by the CVD method to serve as an insulating layer, and a contact area is opened using a photoresist. This state is shown in C. Next, an aluminum film 7 for wiring is deposited to a thickness of about 8000λ by vacuum evaporation, and a wiring pattern is formed using a photoresist.
Finish the process.

This state is shown in D. By the above process, normal MOS
type transistors have been manufactured, but as they become more highly integrated,
As transistor dimensions decrease, various problems arise with this structure.

The most notable of these is a decrease in the threshold voltage Vt. It has been reported that when the effective gate length of a transistor becomes 4 μ or less (hereinafter referred to as short channel), Vt rapidly decreases as shown in FIG. This tendency becomes more pronounced as the source/drain diffusion depth increases. Therefore, for short channels, the diffusion depth is approximately 0.
．． It is necessary to keep it below 3μ. However, since an aluminum-silicon alloy layer is formed in the contact region with the aluminum wiring, in a thin diffusion layer, the aluminum may be pushed toward the substrate during recrystallization, causing a problem. For this reason, short channel transistors employ a structure as shown in FIG. 3A. That is, source/drain diffusion 5, 5
' respectively into two regions 5, 16' and 5', 16'
It has a structure in which the contact part is deep and the side part of the gate is shallow. Normally, the thickness of 5, 5' is 1 to 2 μm, and the thickness of 16, 16'' is about 0.3 μm. The steps to realize this structure are as follows. First, a p-type substrate 1 with a thickness of about 1 μm is A field oxide film 2 is formed by thermal oxidation, and then a photoresist is used to open an area corresponding to 5.5'', and phosphorus is diffused to a depth of about 1 μm. Next, after removing the oxide film in the region where the transistor is to be formed using a photoresist, a gate oxide film 3 is formed to a thickness of about 1000A by thermal oxidation, and polycrystalline silicon is further deposited on top of this. It is deposited by CVD method to a thickness of about 5000 mm. Again, using photoresist, form the gate 4, and apply phosphorus over the entire surface at an acceleration voltage of about 120 KV, 1×1.
Ion implantation is performed to a concentration of 015CT1L-2. Due to this step, field oxide 2 and silicon gate 4 are thick, so phosphorus is not implanted directly beneath them, but only into regions 16, 16'' under the thin gate oxide.

This forms diffusion layers 16, 16' with a thickness of approximately 0.3μ.
This is shown in Figure 3B. Thereafter, a transistor is formed in substantially the same steps as those shown in FIG. The above is the conventionally implemented MOS type integrated circuit or short channel MO
This is an example of a method for manufacturing an S-type integrated circuit. The present invention provides a method for forming a thin Pn junction that can be applied to short channel transistors, and at the same time achieves a self-aligned structure and improved breakdown voltage.

First, let's explain the basic process.

High resistivity silicon wafers (e.g. impurity concentration 10
15? -3 or less) at 60KV, 2 x 1012c
After implanting to the dose of TL-2, 10001C,3
When oxidized in wet oxygen for 0 minutes, since the segregation coefficient of boron is greater than 1, boron is sucked out into the grown oxide film, resulting in a profile as shown in FIG. 4A.
That is, the surface concentration is significantly reduced. On the other hand, Rin is 10
When implanted at 0 KV and at a dose of 1.times.10@12 cm@-2, after a similar oxidation treatment, it accumulates on the surface as shown in FIG. 4B. Therefore, if both are implanted and then oxidized, a low-concentration Pn junction is formed at a depth of about 0.2 μm from the surface, as can be seen by overlapping Figures A and B. The present invention utilizes this thin n-type region as part of the drain of a transistor.

That is, the present invention selectively implants an n-type impurity having a segregation coefficient of less than 1 into a substrate into which silicon/silicon oxide has been implanted with a p-type impurity having a segregation coefficient of less than 1, or onto the surface of a substrate containing the same impurity. Oxidation is performed to form at least part of the source and drain regions of the MOS transistor.

Next, a manufacturing process of a MOS transistor to which the present invention is applied will be explained.

First example This will be explained with reference to FIG.

First, a silicon substrate 1 containing 0.5 to 1.times.10@15 cm@-3 of boron is thermally oxidized to form a field oxide 2 with a thickness of about 1 .mu.m. Next, a region where a transistor is to be formed is opened using photoresist, and a gate oxide film 3 is formed to a thickness of about 500 Å. Next, apply boron 40K, 2X1012crIL'-
Ions are implanted as shown by the arrow at a dose of 2, and phosphorus ions are also implanted at a dose of 70K and 1.5×10 12 cTrL−2.

Since the field oxide 2 is thick, phosphorus and boron do not reach the silicon substrate directly below it, but are implanted only directly below the thin gate oxide film 3. This state is shown in FIG. 5A. Next, the areas where the source/drain contact regions 5, 5'' are to be formed are opened using photoresist, and polycrystalline silicon 4 containing phosphorus is coated over the entire surface to a thickness of approximately 6000 mm using the CVD method. Let it precipitate.

Alternatively, polycrystalline silicon that is not doped with impurities may be deposited, and phosphorus may be diffused over the entire surface to form polycrystalline silicon containing phosphorus. Next, the polycrystalline silicon is etched off except for source/drain contact portions 4 and gate portions 41 using a photoresist. This state is shown in FIG. 5B. At this time, gate oxide film 3 may be etched using polycrystalline silicon as a master. Next, the wafer is oxidized in wet oxygen at 1000° C. for 30 minutes to form an oxide film 20 of about 2700λ between the polycrystalline silicon, and a portion of the polycrystalline silicon is oxidized to form an oxide film 51.

At this time, low concentration n-type layers 61, 6', which become thin source/drain regions, are formed by sucking out boron and accumulating phosphorus into the oxide film 20, and at the same time, phosphorus is diffused from the polycrystalline silicon 4 into the substrate. N-type diffusion layers 5, 5 which become source/drain contact regions! is formed. . mold layer 61
The thickness is approximately 0.2μ. This state is shown in FIG. 5C. This forms the main part of the transistor.
After this, according to the normal process, polycrystalline silicon 4
, 41, and aluminum (not shown) is vapor deposited to form a wiring pattern to complete the integrated circuit. In the manufacturing process above c, the boron concentration is implanted directly under the gate oxide film. is larger than that of phosphorus, and t of the transistor is determined only by the amount of boron implanted. That is, since the area immediately below the gate is not oxidized, there is no suction of boron, and since the amount of phosphorus implanted is lower than the amount of boron implanted, it does not affect Vt, and Vt can be controlled accurately and easily.

Further, due to the suction of boron, the impurity concentration becomes lower in the part 61, 6' of the source/drain region than directly under the gate oxide film, and the depletion layer spreads to 61, 6', so that the drain breakdown voltage does not decrease. Second Example The order of injection is as follows.

First, boron is implanted in the state shown in FIG. 5A, and phosphorus is implanted in the state shown in FIG. 5B. Thereafter, oxidation is performed in the process of Example 1. Third Embodiment In the above process, boron and phosphorus are implanted using a high resistivity silicon substrate containing boron, but in this embodiment, boron implantation is omitted.

That is, since boron is originally contained in the substrate, a substrate containing the required amount of boron is used as a starting point. First, 1.
A p-type silicon substrate 1 containing boron of 0x1016 F-3 is thermally oxidized in wet oxygen to form a field oxide 2.
form. Next, a region where a transistor is to be formed is opened using photoresist, and a gate oxide film 3 is formed therein to a thickness of about 500 nm. This is shown in FIG. 5A. At this time, in the case of an oxide film of 500 nm, the surface concentration of boron hardly decreases, and Vt reaches the value where the substrate concentration has been achieved. next,
Open the gate oxide film in regions 5 and 5' where source/drain contacts will be made, deposit phosphorus-doped polycrystalline silicon over the entire surface, and use photoresist to form source/drain contact regions 4 and gate regions. Form 41. At this time, non-doped polycrystalline silicon may be precipitated and then phosphorus may be diffused over the entire surface. Next, apply phosphorus to the entire surface from above at 70KV, 2×1012Cr1L-2
Ion implantation is performed at a dose of . This state is shown in FIG. 5B. This wafer was processed into 1000 wafers as in the first embodiment.
Oxidize in wet oxygen at 30°C for 30 minutes. The growing oxide film has a thickness of about 2700λ, and at this time boron and phosphorus segregation occurs only in the region where phosphorus ions are implanted into the substrate, that is, in the region where the gate oxide film is exposed in FIG. mold layer 61
, 6', and diffusion regions 5 and 5' made of polycrystalline silicon are formed by heat treatment during the formation of the oxide film 20. The thickness of 61 is approximately 0.2μ.

Further, after FIG. 5B, the gate oxide film 3 may be etched off using the polycrystalline silicon 4, 41 as a mask. With this, the main part of the transistor is formed, and then it is completed according to the normal process. This embodiment has the same excellent features as the first embodiment with one ion implantation. Fourth Embodiment In the third embodiment, the order of injection is as follows.

Injection of phosphorus is carried out in the state shown in FIG. 5A. In the case of the third and fourth embodiments as well, the surface concentration of the implanted phosphorus is lower than the boron concentration in the substrate, so it does not affect Vt.
takes a value determined by the substrate concentration.

As is clear from the description of the embodiments above, according to the method of manufacturing a MOS integrated circuit according to the present invention, (1) the impurity concentration in the thin region that becomes part of the drain is higher than the impurity concentration directly under the gate; Since the depletion layer is low, the depletion layer spreads toward the drain side, and there is no deterioration in breakdown voltage.

(2) Since the thickness of the thin n-type region mentioned above is about 0.2 μm in cell core line contact in cell core line contact, there is little decrease in Vt due to the shoot channel. (3) Ion implantation enables highly accurate control.

Based on the above effects, the present invention makes it possible to realize a MOS integrated circuit process capable of short channels and large scale integration.

[Brief explanation of the drawing]

FIG. 1A-D is a cross-sectional view showing the process of a normal MOS integrated circuit, FIG. 2 is a diagram showing a decrease in Vt due to a short channel,
Figures 3A and B are cross-sectional views showing the conventional conventional process that can be applied to shortening the channel, and Figures 4A and B are changes in the surface state due to oxidation (segregation effect) after boron and phosphorus ion implantation, respectively.
FIGS. 5A to 5C are diagrams showing M according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the manufacturing process of an OS type integrated circuit. 1... Silicon substrate, 2... Field oxide, 3... Gate oxide film, 4, 41
...Polycrystalline silicon, 5,5'...Source, drain contact region, 61,6'...
- Thin source and drain regions, 20... oxide film.

Claims (1)

[Scope of Claims] 1. P-type impurity ions having an impurity segregation coefficient of greater than 1 at the silicon-silicon oxide film interface and n-type impurity ions having the same segregation coefficient of less than 1 are selectively added to a part of the silicon substrate surface. The double implantation process and the growth of a thermal oxide film on part or all of the double implanted region prevent the p-type impurity from being sucked out into the oxide film and the n-type impurity from accumulating on the silicon surface. and a step of forming an n-type region near the surface of the substrate, and the n-type region formed in the step is arranged so as to constitute at least a part of the drain region of the MOS transistor. A method for manufacturing a MOS type semiconductor integrated circuit. 2 Selectively add n-type impurity ions with a segregation coefficient of less than 1 to a part of the silicon substrate surface containing p-type impurities with an impurity segregation coefficient of greater than 1 at the silicon-silicon oxide film interface within a range that does not exceed the substrate concentration. A step of implanting ions to a concentration of
a step of accumulating type impurities on the silicon surface to form an n-type region near the surface of the substrate; 1. A method of manufacturing a MOS type semiconductor integrated circuit, comprising arranging the circuit so as to configure the MOS semiconductor integrated circuit.