JPS5931231B2 - Floating gate non-volatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory, and particularly to a nonvolatile semiconductor memory that can be written to at low voltage and has improved rewriting reproducibility.

A conventional floating gate nonvolatile semiconductor memory with a control gate has a control gate 2 on a floating gate 1, as shown in the first diagram.
However, since the floating gate 3 was made of polycrystalline or metal particles, the withstand voltage of the insulating film 2 grown on the gate was low and its reproducibility was poor.

For this reason, the thickness of the insulating film 2 cannot be reduced, and the write voltage has to be increased. On the other hand, some devices took advantage of the low withstand voltage of the insulating film 2 to draw charges from the floating gate 1 to the control gate 3 to write (or erase) information; It changed every time I performed an introductory operation.

In FIG. 1, 10 is a semiconductor region (in this case, the substrate), 1
1 and 12 are source and drain regions for information detection.
In view of the above, the present invention has been made with the main purpose of reducing the voltage required in the potential control area during write operation and improving the reproducibility of the write voltage. The purpose of this invention is to increase the withstand voltage of an insulating film between a floating gate region, a potential control region, and a charge inflow/outflow region, and to improve its reproducibility.

Note that the charge inflow/outflow region is defined here as a region in which carrier charges flow into or flow out from the floating gate region. To outline the basic configuration of the present invention that achieves the above object, a floating gate region, a potential control region, a charge inflow/outflow region, and a first semiconductor region, each of which is at least partially opposed to the floating gate region through an insulating film. In the non-volatile semiconductor memory which is also a non-volatile semiconductor memory, in at least one of the opposing relationships between the floating gate region and the potential control region, and the floating gate and the charge inflow/outflow region, a surface on which the insulating film is grown between the opposing region is formed. The region having the crystal is semicrystalline or single crystalline (preferably single crystalline).
That is, when an insulating film is grown on the surface of the potential control region and/or the charge inflow and outflow regions and a floating gate region is provided thereon, the potential control region and/or the charge inflow and outflow regions are semi-crystalline (preferably single crystal). When forming a potential control region and/or a charge flow/inflow region through an insulating film grown on the floating gate region, the floating gate region should be semicrystalline (preferably single crystal). .

This is based on the knowledge that insulating films grown on single-crystal or semi-crystalline surfaces have superior properties such as withstand voltage and reproducibility compared to those grown on polycrystalline surfaces. It is.

As a result, the floating gate region (hereinafter simply referred to as floating gate) and the potential control region or the charge inflow/outflow region face each other via an insulating film with high dielectric strength and good reproducibility, so that the intervening insulating film The thickness can be reduced, and the voltage required for the potential control region during write operation can be lowered.

Further, since this insulating film has good reproducibility of VI characteristics in a micro current range, a nonvolatile semiconductor memory with good write voltage reproducibility can be obtained. In the present invention, the term "semicrystal" is used to refer to crystals obtained by making the crystal grains of a polycrystalline film significantly larger than the film thickness by means such as laser annealing or electron beam annealing, or by making the crystal grains into a single crystal.
O is a general term for single crystal films grown or constructed on insulating films using epitaxial or ion implantation technology.
In addition, the potential control region, the charge injection region, and the first semiconductor region are not included in the present invention in view of their functions, not only when they are independent, but also when two or more regions are formed in common. The same applies to cases in which the two roles alternate depending on the write information (1 to 0).

Next, the present invention will be explained through examples.

FIG. 2 shows a cross-sectional view of an embodiment of the present invention, in which 1 is a floating gate, 3 is a potential control region, and 5 is a charge inflow/outflow region, which is a region of the opposite conductivity type to the first semiconductor region 10. . Each region faces the floating gate via insulating films 2, 4, and 6 formed on each region. Therefore, in this case, compared to the conventional method, if either the potential control region 3 having the surface on which the insulating films 2 and 4 are grown and the charge inflow/outflow region 5 are made of at least semicrystal or single crystal, it is possible to However, in this embodiment, both regions 3 and 5 are made of single crystal. Writing to this element increases the potential of the charge inflow/outflow single crystal region 5 in the first direction, creates a potential difference with the floating gate, applies a strong electric field to the insulating film 4, and performs Fauler-Nordheim tunneling. Alternatively, by a strong electric field conduction mechanism such as direct tunneling, carrier charges are caused to flow into or out of the region 5 from the region 5 to the region 5 through the insulating film 4, thereby changing the charging state of the floating gate 1.

Generally, in order to perform the write operation as described above, the capacitance Ci between the charge inflow/outflow single crystal region and the floating gate, the total capacitance Cfl of the floating gate, the insulating film between the floating gate and the charge outflow/inflow single crystal region, Conduction voltage (voltage at which sufficient carrier charge transfer occurs to change the charging state of the floating gate)
Ci/(Cf
-Ci) Vtf/Vti It is necessary to select the opposing area, insulation film thickness, type of insulation film, etc. between the floating gate and each region so that the relationship (1) is satisfied. It turns out that there is.

In Fig. 2, an example is shown in which the insulating film 4 is thinner than the other insulating films 2 and 6, but if the insulating films 2, 4, and 6 are uniform, have the same thickness, and are of the same type, it is simple. The objective is achieved by designing the opposing area between the floating gate and the charge inflow/outflow single crystal region to be smaller than the opposing area between the floating gate and other regions. Also,
The insulating film is partially composed of a silicon nitride film with higher conductivity, for example, between the floating gate and the charge inflow and outflow regions, and the insulation film with lower conductivity, such as silicon oxide film, is formed between the floating gate and other regions. If it is composed of a membrane (single layer or multiple layers), (
It has also been found that the condition of equation 1) can be realized without imposing severe restrictions on planar dimension design. In order to return the charged state of the floating gate to the initial state, the potential of the potential control single crystal region 3 is increased in the first direction, thereby coupling this potential to the floating gate 1, which is different from that at the time of writing. By applying a voltage in the opposite direction between the floating gate and the charge inflow/outflow single crystal region, the charge can be moved through the insulating film 4 and the charging state of the floating gate can be returned to the direction of the state before the write state. .

The charged state of the floating gate can be read out based on the surface state of the semiconductor region 10.

That is, if the floating gate is more positively charged with respect to the potential of the semiconductor region 10, the surface of the semiconductor region 10 is in a state where more electrons are induced or fewer holes than in the equilibrium state, and the surface is negatively charged. The opposite is true if the device is charged, so it may be due to a change in capacitance between the information detection region and the semiconductor region, which are provided under the floating gate and partially opposed to each other through the insulating film, or due to the information detection. The charged state of the floating gate can also be determined by other known methods, such as providing a plurality of regions and measuring changes in electrical conductivity between them. In the above embodiment, the semiconductor region 10 is a semiconductor substrate, but it may be a semiconductor region on an insulating substrate or a semiconductor region formed on the surface of a semiconductor substrate of the opposite conductivity type. The conductivity type of the region, the charge inflow/outflow single crystal region, and the potential control single crystal region may be either p type or n type. Furthermore, the semiconductor region and other regions may be made of different materials. In this case, even if the semiconductor region 10 constitutes the substrate, the other regions may be p-type or n-type as long as they are formed of a material that constitutes a barrier with the semiconductor region 10. Now, specific examples of elements having the information detection regions 14 and 15 are shown in FIGS. 3 and 4.

The regions 14 and 15 are provided so as to be in contact with the surface of the semiconductor region 10 and partially face the floating gate 1 with insulating films 19 and 20 interposed therebetween. Region 13 is provided so as to face floating gate 1 with insulating film 17 in between. In this case, regions 10, 13, 14, and 15 that satisfy the condition of equation (1) can be used as charge inflow and outflow single crystal regions if they are single crystal regions, and other regions can be used as potential control single crystal regions. Can be used as a region. This is semiconductor region 1
It can be manufactured by using a single crystal region as the region 10 and selectively introducing impurities of opposite conductivity type into the surface of this region 10. Furthermore, if the semiconductor region 10 is formed on an insulating substrate or a substrate of the opposite conductivity type, and is electrically insulated from the substrate, the information detection region can be of the same conductivity type as the semiconductor region 10 to prevent floating It is also possible to eliminate the portion facing the gate 1. This also applies to the embodiment of the semi-crystalline floating gate described later. In FIGS. 3 and 4, A shows a plan view, B shows a cross-sectional view taken along the line YY'', and C shows a cross-sectional view taken along the line YY''.

FIG. 4 shows a specific example in which a part of the insulating film between the floating gate 1 and the region 14 is made thinner than the other insulating films in order to use the region 14 as both a charge inflow/output region and an information detection region.
In this case, the explanation will be made with the region 13 fixed as a potential-controlled single crystal region. When reading information from this element, the region 13 can be seen as the gate of an insulated gate field effect transistor, the region 15 as the drain, the region 14 as the source, and the region 10 as a channel forming region. In this case, it can be considered that the gate threshold voltage of this field effect transistor differs depending on the charging state of the floating gate, so the region 1
When the voltage applied to the floating gate 3 is fixed, changes in the charged state of the floating gate can be determined by the current flowing between the regions 14 and 15 or the change in the conductance between the regions 14 and 15. The cross-sectional view of the device in FIG. 4 in the Xx'' direction is the same as that in FIG. This is a measure to prevent information from being written in area 1.
This is done by increasing the potential of 4 in the first polarity direction and causing carrier charges to flow in and out of the floating gate through the thinnest insulating film, thereby changing the charging state. On the other hand, by increasing the potential of the region 13 in the first polarity direction, this potential is coupled to the floating gate, and the voltage between the floating gate and the region 14 is changed in the polarity direction opposite to that during writing,
Rewriting or writing of reverse information can be performed by causing carrier charges to flow in and out in the opposite direction through the thinnest insulating film and returning the charged state of the floating gate 1 to its initial state. When this element is incorporated into an XY matrix array, a necessary characteristic is a write blocking function. This function is achieved, for example, by applying a potential change of the same polarity to region 13 when applying a potential change of the first polarity to region 14. Generally speaking, a design is possible in which writing can be blocked by applying a potential change in the same direction as the charge inflow/outflow region to the potential control region. Returning to FIG. 3, when the area facing the region 13 and the floating gate is designed to be small, the region 13 becomes a charge inflow and outflow region, and either one of the first semiconductor region 10 or the information detection regions 14 and 15 or Both can be used as potential control regions. In the embodiment shown in FIG. 2, when regions 3 and 5 are designed to also serve as information detection regions, when a large potential of the first polarity is applied to potential control region 3, a large current flows between regions 3 and 5. It becomes difficult to reverse the change in the charging state of the floating gate.

In order to solve this problem, as shown in FIG.
It is preferable to provide a structure in which an opening is provided in the floating gate 1 which is provided across the thin insulating film 6 between the openings, and the second conductive gate 21 is opposed to the semiconductor region 10 with the insulating film 22 interposed therebetween. Of course, the floating gate and the second gate are insulated by the insulating film 22a. With this configuration, when writing and rewriting information, if a potential in the channel closing direction is applied to the second gate 21, the areas 3 and 5
Information can be written or rewritten without a large current flowing between them. In the above embodiment, the potential control region and the charge inflow and outflow regions were formed on the surface of the semiconductor region 10, but when formed on an insulating substrate, for example, the potential control region and the charge inflow and outflow regions are in contact with the semiconductor region 10. There's no need to be. As another embodiment of the present invention, a specific example in which the floating gate is made of a single crystal or a semi-crystal will be described. In this case, as an example is shown in FIG. 6, floating gate 1 faces semiconductor region 10 with an insulating film interposed therebetween. It is sufficient that only the information detection region 31 is in contact with the semiconductor region 10, and the potential control region of the insulating film and the charge inflow and outflow regions do not need to be single crystal or semicrystalline, as understood from what was stated at the beginning. . For example, a conductive thin film 33 provided via the insulating films 2 and 4 on the floating gate,
It has been proven that 35 is also good. Of course, as shown in the previous embodiment, the information detection region, the charge inflow/outflow region, the potential control region, and the first semiconductor region are mutually common regions, and the number of regions itself is It is also possible to reduce For example, as shown in Figure 7, a semi-crystalline floating gate and a potential control region 33.1! The semi-crystal floating gate is extended over the thick insulating film 8 in order to significantly increase the opposing area of the semi-crystal floating gate and the first semiconductor region 10 and the information detection regions 31 and 32. If they are made to face the potential control region 31, both the first semiconductor region 10 and the information detection regions 31 and 22 can be used as charge flow/inflow regions. Regarding the method of forming the floating gate 1 as a single crystal or a semi-crystal, for example, a silicon polycrystalline film is grown on the insulating film 6 and formed into a prescribed shape using a well-known method such as photo-etching. When annealing is performed using a laser beam having a wavelength that is absorbed by the silicon polycrystalline film or an electron beam having a range within the thickness of the silicon polycrystalline film, the silicon polycrystalline film has a thickness of 20 to 30μ in plan view. If it is less than a corner and has a thickness of about 1 μm, it becomes a single crystal, and if it is larger than the above-mentioned size in plan view, it becomes a collection of crystal grains that are larger than the thickness and have a planar grain size of 20 to 30 μm or more. Normally, floating gates of non-volatile memory often have a planar figure of several tens of microns or less, so the number of grain boundaries that appear in one planar figure must be drastically reduced from the initial number to the order of several or less. It turned out that it can be done. As mentioned above, this crystal is referred to as a semi-crystal in the present invention. Therefore, it has been confirmed that the insulating film grown on this floating gate exhibits good reproducibility and uniformity of current-voltage characteristics similar to that of an insulating film grown on a single crystal. In an element having such a floating gate, the first semiconductor region, the floating gate, the potential control region or the charge inflow and outflow region can be stacked, so the device has a small planar dimension, a low write voltage, and good retention characteristics. A semiconductor nonvolatile memory with good reproducibility of rewrite characteristics can be obtained.
Therefore, it is possible to realize an LSI including a non-volatile memory array that has a higher density and smaller size than conventional non-volatile memories, and has an improved number of rewrites. In any case, according to the present invention, in addition to the basic effects of enabling low-voltage writing and improving reproducibility, it also becomes possible to reduce the size and density of the array peripheral circuitry due to the reduction in voltage. Another important effect is that it contributes to the high density and small size of the entire LSI including the.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a typical example of a conventional floating gate type nonvolatile semiconductor memory with a control gate, FIG. 2 is a configuration diagram of one embodiment of the present invention, and FIG. 3A is a planar configuration of another embodiment. figure,
Figure 3B is a sectional view along the line YY' of Figure 3A (7).
Figure C is a sectional view taken along line A (7)
5A is a plan view of another embodiment; FIG. 5B is a sectional view taken along the Y'Y' line of FIG. 5A; FIG. FIG. 7A is a plan configuration diagram of yet another embodiment, FIG. 7B is a sectional view taken along the YY' line of FIG. 7A, and FIG. 7C is a diagram of FIG. 7AOXX! It is a cross-sectional view along the line. In the figure, 1 is a floating gate region, 2, 4, and 6 are insulating films, 3 is a potential control region, 5 is a charge inflow and outflow region, 10 is a first semiconductor region, and 13, 14, and 15 are charge inflow and outflow regions, respectively. 21 is a second conductive gate region, and 33 and 35 are conductive thin films.

Claims (1)

[Claims] 1. A floating gate type nonvolatile device having a floating gate region, a potential control region, a charge inflow/output region, and a first semiconductor region, each of which faces at least a portion of the floating gate region through an insulating film. In the semiconductor memory, in at least one of the opposing relationships between the floating gate region and the potential control region, and the floating gate region and the charge inflow/outflow region, a surface on which the insulating film is grown between the opposing region. 1. A floating gate nonvolatile semiconductor memory characterized in that one region of the memory is semi-crystalline or single-crystalline. 2. The memory according to claim 1, wherein the first semiconductor region has at least one information detection region in contact with the first semiconductor region. 3. The memory according to claim 2, wherein the charge inflow/outflow region and the information detection region or the first semiconductor region are a common region. 4. The memory according to claim 2 or 3, wherein the potential control region and the information detection region or the first semiconductor region are a common region. 5. Claim 1, characterized in that the insulating film 3 between the charge inflow and outflow regions and the floating gate region has a partially thin part, and charge inflow and outflow is performed in the thin part. Memory described in any one of 4 to 4. 6. A patent characterized in that the insulating film between the charge inflow/output region and the floating gate region is partially composed of a silicon nitride film, and the insulating film between the other regions and the floating gate region is composed of a silicon oxide film. A memory according to any one of claims 1 to 4. 7. The floating gate has a partial opening above the first semiconductor region, and a second conductive gate is further provided in the opening, which is insulated from the first semiconductor region and the floating gate by an insulating film. The memory according to claim 2, characterized in that: