JPS5931754B2 - coin sorting device - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a device for sorting coins by measuring characteristics such as material, thickness, diameter, etc. of coins using an electrical method, and accurately determines the authenticity of coins by incorporating an error range. It brings about change.

One embodiment will be described in detail below with reference to the drawings.

Inspection of the characteristics of coins using electrical methods generally involves the frequency of the excitation coil, which is caused by eddy current loss within the coin, which is caused by placing the coin in an alternating magnetic field induced by the excitation coil.
This is done by inspecting changes in intagtance or by adding a detection coil and measuring the phase difference between the excitation coil and the detection coil, which is also based on the eddy current loss.

The measurement results obtained by such an electrical method are expressed in analog quantities, and the operation of determining the coin's authenticity and denomination is started by first converting this analog quantity into a digital quantity. Figure 1 shows a detector 1 that tests the characteristics of coins by measuring phase differences.
2 shows an inspection circuit 2 that outputs information necessary for a coin judgment operation in digital quantities based on the inspection results.

The configuration of the detector 1 is such that an excitation coil IA and a detection coil IB are arranged to sandwich a coin passage 4, and a voltage or current change in the excitation coil IA and the detection coil IB based on the passage of a coin 5 is output to the inspection circuit 2. It is. The test circuit 2 inputs AC signals indicating voltage or current output from the excitation coil IA and the detection coil IB into waveform shaping circuits 6 and 7, converts them into rectangular waves, and sends the rising outputs of both to a set of flip-flop circuits 8 and 7. The phase difference is detected by using it as a reset input. Therefore, the Q of the flip-flop circuit 8
The output is generated during a period corresponding to the phase difference width, and this phase difference is measured by counting clock pulses during the period when the flip-flop circuit 8 generates the Q output. There is. For example, if the inspection circuit 2 is configured so that the gate 9 is opened by the Q output of the flip-flop circuit 8 and the clock pulses output from the clock pulse generator 10 are counted by the counter 11, the measured phase difference, that is, the clock pulse necessary for the coin judgment operation is calculated. Inspection circuit 2 where information is in digital quantity
This is why it occurs. While the coin 5 rolls through the coin path 4 and is inspected by the detector 1, this phase difference is not always constant, and its value becomes maximum when the detector 1 and the coin 5 overlap. Therefore, while the coin 5 is being inspected by the detector 1, the oscillation frequency of the excitation coil 1A is set so that the flip-flop circuit 8 detects many different phase differences. The largest one is captured and used as a measurement result for information on determining the authenticity and denomination of the coin 5. FIG. 2 shows the configuration of a maximum value detection circuit U that extracts the maximum phase difference from the inspection circuit 2.

The comparison circuit 13 compares the count value C of the counter 11 included in the test circuit 2 with the content R of the register 14, and outputs an a signal if C>R and a b signal if R>C.
In the initial state, the content C of the register 14 is "0", so when a certain value indicating the phase difference is counted by the counter 11, since C>R, a signal is generated and the AND gate is activated. Input to Al, A2, A3, A4, A5. Since one of these AND gates Al, A2, A3, A4, and A5 is connected to each bit of the counter 11, the count content C of the counter 11 is changed to the register 1 when the signal a arrives.
It will be transferred to 4. Eventually, the counter 11 counts a value indicating the next phase difference, and the comparator 13 compares this value with the value transferred to the register 14 earlier. At this time as well, C>R, the a signal is generated, and the count contents of the counter 11 are transferred to the register 14 again. In this way, each time there is an output from the flip-flop circuit 8 indicating a phase difference, the count counted by the counter 11 is sequentially compared with the previous count by the comparator 13. Eventually, as described above, when the coin 5 reaches the position where it overlaps the detector 1, the phase difference will show the maximum value, but at this stage it cannot be confirmed that it is the maximum, and this value is also transferred to the register 14. Ru. Then, when the coin 5 moves slightly away from the overlapping position, the phase difference becomes smaller, and the comparator 13 detects that the value counted by the counter 11 is smaller than the maximum value stored in the register 14, and the R>COb signal becomes It occurs. Therefore, when the b signal is generated, it is confirmed that the value currently stored in the register 14 is the maximum value, and the value of the register 14 is changed to the AND gate All2Al29Al3raAl4raAl
It can be shown as the maximum value via 5. In this way, the authenticity and coin type of the coin 5 are determined based on the phase difference maximum value information outputted from the maximum value detection circuit U, but the maximum value detection circuit U in particular is not essential to the present invention. This may be omitted if this determination is made using the total phase difference information outputted from the inspection circuit 2 as a measurement result. FIG. 3 shows a circuit for coin determination based on phase difference maximum value information outputted from the maximum value detection circuit u. The readout memory 3 is composed of, for example, a diode matrix, the input lines are provided corresponding to the number of bits indicating the maximum phase difference value information, and the output lines are flip-flop circuits FFl, 7FF2, 7FF2, FF2, FF1, FF2, FF1, FF2, FF2, FF1, FF1, FF2, FF2, FF2, FF1, FF2, FF2, FF1, FF2, FF2, FF2, etc. F
It is connected to the set end and unset end of F3 and FF4. The readout memory 3 uses the detector 1, the inspection circuit 2, and the maximum value detection circuit to locate real coins of each coin type along addresses represented by 5-bit input lines indicated by binary codes "1" and "0". Upper limit value of the range that can be shown when measuring phase difference
Each lower limit value is stored. When the set address is presented via the input line, the read memory 3 outputs the stored upper limit value or lower limit value information via any output line. Flip-flop circuit FFl, FF2
, FF3, FF4 connect output lines indicating lower limit value information of the corresponding coin type to the set terminal, and output lines indicating upper limit value information to the reset terminal. The circles shown in FIG. 3 indicate the state in which the output line and the input line are short-circuited by forward connection of the diode 16 as shown in FIG. 4, and storage is performed by the combination of these. The operation of determining the coin 5 from the readout memory 3 and flip-flop circuits FFl, FF2, FF3, and FF4 based on the maximum phase difference value measured by the maximum value detection circuit will be explained. The adder 15 sequentially reads out values in the range from O to the maximum phase difference value and shows them as addresses in the memory 3. Information stored in this range of values as addresses is read out successively and is applied to the corresponding flip-flop circuits FFl, FF2, The signal is output to either FF3 or FF4 and set or reset is performed. and adder 15
The values shown are for each flip-flop circuit FFl, FF.
When the address indicates the lower limit value of FF2, FF3, and FF4 or is between the address indicating the lower limit value and the address indicating the upper limit value, the flip-flop circuit enters the set state. However, a flip-flop circuit whose lower limit value is specified by an address larger than the maximum phase difference value will not be set, and a flip-flop circuit whose upper limit value is specified by an address smaller than the maximum phase difference value will be reset again even if it is set once. As a result of such a scan operation, only one flip-flop circuit or all of the flip-flop circuits are brought into a reset state. When all are in the reset state, the maximum phase difference value is outside the range of the addresses indicating the respective lower and upper limits. Therefore, when the adder 15 outputs the maximum phase difference value, if all coins are in the set state, the coin 5 is determined to be counterfeit, and if one is set, it is determined that the coin type corresponds to the flip-flop circuit. is revealed. The present invention, which has been described in detail above, relates to a coin sorting device that determines coins by inspecting their characteristics based on electrical methods, and extracts information to be determined from the inspection results by a detector and converts this information into digital data. The present invention proposes that an inspection circuit is provided to output a measurement result in terms of quantity, and the coin is judged by digital processing at a later stage.

Therefore, the measurement results for genuine coins, which serve as reference values, are read out in advance and stored in the memory, but by setting the upper and lower limits in consideration of the allowable error range and performing the scan operation. Since the addressing signal which ensures reliable coin sorting and commands the readout of memory in the readout memory is the same as the signal output from the inspection circuit, the circuit can be easily constructed.

[Brief explanation of drawings]

FIG. 1 shows the detector and test circuit, FIG. 2 shows the configuration of the maximum value detection circuit, FIG. 3 shows the readout memory and a flip-flop circuit that produces a coin determination output, and FIG. 4 shows the structure of the maximum value detection circuit. Show details.

Claims (1)

[Claims] 1. A detector that electrically tests the characteristics of a coin, a test circuit that outputs a measurement result to be judged based on the test results based on the characteristics as a digital amount of a predetermined number of bits, and a A readout memory that stores upper and lower limit values of measurement results based on the characteristics of the coin along the addresses indicated by the number of bits, and a reset input and a signal indicating the upper and lower limit values read from the meseri, respectively. It consists of a flip-flop circuit arranged corresponding to the coin type as a set input, and the memory is sequentially addressed by the number of bits from "0" to the value obtained by the inspection circuit every time a coin is inspected. A coin sorting device characterized in that the type of coin is determined based on the set state of the flip-flop circuit.