JPS5932894B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a self-alignment method for manufacturing a semiconductor device with high precision.

Generally, in the manufacture of semiconductor integrated circuit devices (hereinafter abbreviated as IC), when an opening is formed in an insulating film deposited on the main surface of a semiconductor substrate to form an electrode region by diffusing impurity substances into the semiconductor substrate, a wiring metal layer is formed. Many masks are used when patterning.

Operations performed using a mask involve pitch deviation, rotation, and aligner misalignment; pitch deviation is usually ±1 μ per 50 mm, and rotation is ±1.
μ, the aligner misalignment is about ±1μ, so I
When designing C, it is necessary to provide a margin in the pattern so that any of the above-mentioned "shifts" will not hinder the formation of the circuit, and this margin is approximately ±2μ in total. When the minimum pattern width is about 6μ, this margin ±2μ does not have much effect on the increase in mask size, but when it is 4μ or less, the mask size increases in order to maintain this margin.
Therefore, in IC manufacturing, the accuracy of the IC depends on the precision of the mask.
The disadvantage was that the minimum pattern width was limited. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device using a self-alignment method, which eliminates the above-mentioned drawbacks of the conventional method and reduces the pattern margin depending on mask precision.

A method for manufacturing a semiconductor device according to the present invention includes depositing a first insulating coating on one main surface of a semiconductor substrate of a first conductivity type, laminating this, and depositing a second insulating coating made of a different material. providing a first opening; using the second insulating film as a mask, over-etching the first insulating film to provide a second opening having a larger area than the first opening; using the first insulating film as a mask; forming a first impurity region by diffusing a second conductivity type substance having a conductivity type opposite to the first conductivity type into the semiconductor substrate through the second opening; a step of depositing a coating, then a step of forming a third opening in a portion of the third insulating coating using a portion of the first insulating coating defining the second opening and the first resist layer as a mask; Using the first and third insulating films as masks, a first conductivity type substance is diffused into the semiconductor substrate through the third opening to form a second impurity region, and a fourth insulating film is added here to close the third opening. the step of forming a film;
providing a fourth opening for forming a contact electrode in the second impurity region by subjecting the insulating film to ion etching or sputter etching using the second resist layer and the eaves-shaped second insulating film as a mask; 1st
A fifth opening for providing a contact electrode in the first impurity region is provided in the third insulating film in the opening by performing ion etching or sputter etching using the third resist layer and the eaves-shaped second insulating film as a mask. It is characterized by comprising a process.

Next, one embodiment of the present invention will be explained in detail with reference to the drawings.

(1) In Figure 1, 1 is the base and the specific resistance is 0.4Ω? A silicon oxide film 2 (hereinafter referred to as oxide film) is deposited on the upper surface of this N-type region, and is formed by thermal decomposition of monosilane (SilI4) and ammonia (NH3). After depositing the silicon nitride film 3 (hereinafter abbreviated as nitride film), a first opening 13 was first formed in the nitride film.

This opening is achieved by plasma etching in Freon (CF4). (2) Next, using the nitride film as a mask, the oxide film 2 is over-etched to provide a second opening 12 having a larger area than the first opening 13.

As an example, the above-mentioned overetching was carried out extending along the film surface by about 1.5 μm from the mask (FIG. 2). (3) Next, using the oxide film 2 as a mask, boron B(7)P conductivity type material is diffused and introduced from the second opening 12 to form a P-type region 4 as a first impurity region (FIG. 3).

(4) Next, an oxide film 5 (third insulating film) is deposited on the exposed surface of the P-type region 4 by thermal oxidation (FIG. 4).

(5) Next, a first resist film 6 is applied to the exposed surface and patterned to form a patterned first resist layer 6'. Next, the oxide film 5 (third insulating film)
An oxide film 2/(
A third opening 15 was formed using a portion of the first insulating layer and the resist film 6' as a mask (FIG. 5). (6) Using the oxide film 5' opened by forming the third opening 5 and the oxide film 2' defining the second opening 12 as a mask, phosphorous oxychloride (POCl3) is removed from the third opening 15. ),
An N-type region 8 as a second impurity region was formed in a part of the P-type region 4 (FIG. 6).

(7) Next, in order to close the third opening 15, an oxide film 9 (fourth insulating film) was formed on the exposed surface of the base 1 (FIG. 7).

(8) Next, a second resist film 6'2 is formed, and the oxide film 9 is etched by ion etching using argon gas using this and the canopy-shaped nitride film 3' (second insulating film) as a mask.
A fourth opening 16 was provided in the opening.

This exposed surface is later provided with an electrode contact to the N-type region 8 of the second impurity region (FIG. 8). (9) Form a third resist film 7 with a different pattern from the second resist film 6'', and apply a third resist film formed thereon to the oxide film 5' (third insulating film). A fifth opening 17 for providing a contact electrode is formed in the P-type region 4 of the first impurity region by ion etching or sputter etching using the canopy-shaped nitride film 3' (second insulating film) as a mask. Figure 9).

(Self) Provide an electrode contact portion in the N-type region of the semiconductor tea body according to item (9) above.

Further, the resist film is removed and the nitride film 3 is removed using hot phosphoric acid (H3PO4) (not shown). Although the above example is based on the NPN structure, the same method can be applied to the PNP structure as well, with many or small electrode areas.

According to the present invention, the drawback of "misalignment" in mask operation according to the prior art described above has been solved.

That is, since the position of the side surface on the first side of the opening is determined by the insulating coating, there is a remarkable advantage that the margin for "misalignment" can be halved. This is a major contribution to improving the degree of integration in semiconductor devices, especially in ICs.

[Brief explanation of the drawing]

1 to 9 are cross-sectional views shown in the order of steps for explaining the method of manufacturing a semiconductor device of the present invention. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 1... N-type region (first conductivity type semiconductor substrate), 2... Oxide film (first insulating film), 3...
... Nitride film (second insulating film), 4... P-type region (first impurity region), 5... Oxide film (third insulating film), 9...・Oxide film (fourth insulating film), 8・
...N-type region (second impurity region), 12...
・First opening of oxide film (first insulating film), 13...
...Second opening of nitride film (second insulating film), 15...
...Third opening of oxide film (third insulating film), 16...
...Fourth opening of oxide film (fourth insulating film), 17.
...Fifth opening of oxide film (third insulating film), 61
, 6″...Resist film, 7...Third resist film.

Claims (1)

[Claims] 1. A step of depositing a first insulating film on one main surface of a semiconductor substrate of a first conductivity type, depositing a second insulating film laminated thereon and having a different material, and providing a first opening in the first insulating film; a step of over-etching the first insulating film using the second insulating film as a mask to provide a second opening having a larger area than the first opening; a step of diffusing a second conductivity type substance of an opposite conductivity type into the semiconductor substrate to form a first impurity region; a step of depositing a third insulating film on the exposed surface of the semiconductor substrate in the second opening; 3. providing a third opening using a part of the first insulating film and the first resist layer as a mask defining a second opening in a part of the insulating film; diffusing a first conductivity type substance into the semiconductor substrate from the third opening as a mask to form a second impurity region, and forming a fourth insulating film here to close the third opening; providing a fourth opening for forming a contact electrode in the second impurity region by subjecting the film to ion etching or sputter etching using the second resist layer and the eaves-shaped second insulating film as a mask;
and a fifth step for providing a contact electrode in the first impurity region by subjecting the third insulating film in the first opening to ion etching or sputter etching using the third resist layer and the canopy-shaped second insulating film as a mask. A method for manufacturing a semiconductor device comprising a step of providing an opening.