JPS5935529B2 - analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter with high speed and high resolution.

With recent advances in microcomputers (MPUs), attempts are being made to replace various analog systems with digital systems.

In this case, it is necessary to convert the analog signal into a digital signal, but the resolution associated with this A/D conversion directly affects the accuracy, continuity, etc. of the digital system.

For this reason, how to perform high-resolution A/D conversion is a major problem in improving the precision and continuity of digital systems.

In order to increase the resolution of A/D conversion, it is possible to use a counting type A/D converter or a high resolution A/D converter.

However, the former has the disadvantage of slow conversion speed, and the latter has the disadvantage of being complex and expensive.

Here, the present invention aims to realize a high-speed, high-resolution A/D converter with a simple circuit configuration.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 10 is a comparator to which an analog signal e1 is applied to one input terminal, and 20 is a processor which receives the signal from the comparator 10 as an input, for example, a microcomputer is used for this.

30 is a D/A converter that converts the digital signal from the processor 20 into an analog signal; 40 is a dither signal generation circuit that generates a dither signal based on the signal from the processor 20; and 50 is a D/A converter from the D/A converter 30. This is an addition circuit that adds the signal eA of the signal eA and the dither signal e5 from the signal generation circuit 40.

The comparator 10 has an analog signal e1 applied to one input terminal and an adder circuit 50 applied to the other input terminal.
The comparison result is provided as an input signal to the processor 20.

The processor 20 has a successive approximation function and a counting function, and includes an input port 21, a data memory section 22 configured as a read/write memory, an arithmetic control section 23, and a program memory section configured as a read-only memory, for example. 24 and an output port 25.

The input port 21 receives the signal from the comparator 10 and waits for the output signal of the comparator 10 to be read by the signal from the arithmetic control section 23.

The data memory section 22 temporarily stores a signal applied from the input port 21, for example, according to a signal from the calculation control section 23, and stores calculation results.

The program memory unit 24 stores in advance conversion procedures for converting input analog signals into digital signals, data necessary for calculations, etc., and the contents thereof are stored in the calculation control unit 2.
It is read out by the signal from 3.

The arithmetic control section 23 reads the state of the signal applied to the input port 21, writes it to the data memory section 22, decodes the conversion procedure and arithmetic procedure from the program memory section 24, and performs the following functions. Digital operations are performed using data and signals read from the data memory section 22.

The output port 25 is supplied with a digital signal output from the data memory section 22 or the arithmetic control section 23, and depending on the signal from the arithmetic control section 23, the digital signal is sent to the D/A converter 30 or to the dither signal generation circuit. A control signal is output to 40.

The D/A converter 30 converts the digital signal output from the output port 25 into an analog signal, and converts this into an analog signal.
It is given to 0.

FIG. 2 shows an example of the dither signal generation circuit 40.
A is a circuit diagram, and a is an output waveform diagram.

This circuit consists of ■ Switch Sl connected to + power supply, V-
Switch S2 connected to the power supply, each switch S1 . S2
resistors 41, 44 connected to these resistors 41, 44
It consists of a capacitor 42 that integrates the signal applied via the capacitor 42.

Then, switch S1. S2 is a dither signal e that is driven by a signal from the processor 20 and continuously changes from an output terminal (one end of the capacitor 42) to a positive polarity side and a negative polarity side with time as shown at the top.

Output.

In the present invention, the dither signal collectively refers to a first-order delayed signal, a sawtooth wave signal, or a triangular wave signal that continuously changes between positive and negative polarity over time. The timing of generation of the dither signal, etc. is controlled by a control signal from the processor 20.

The device configured in this manner first performs an A/D conversion operation using a successive approximation method without generating a dither signal, and then performs an A/D conversion operation using a counting method with a dither signal generated. It has characteristics of operation.

The operation will be described in detail below with reference to the flowchart in FIG.

First, the apparatus is placed in a mode (successive approximation mode) in which an A/D conversion operation is performed using a successive approximation method.

In this successive approximation mode, the processor 20 controls not to generate a dither signal, and the comparator 10
, processor 20, and D/A converter 30, the input analog signal e1 is converted into a digital signal by a successive approximation method.

That is, initially, A formed in a part of the arithmetic control section 23
If 1'' is set in the most significant bit of the register (step ■).

This causes the A register to contain 50% of the total capacity of this A register.
A digital quantity corresponding to the value is set.

Next, the contents of the A register are output to the D/A converter 30 (
Step ■).

As a result, the D/A converter 30 converts the digital quantity corresponding to the 50% into an analog quantity, and this analog signal ef is applied to the other input terminal of the comparator 10.

Next, the output signal of the comparator 10 is read and the state of the signal is determined (step 2).

Here, if the state of the read signal is II OII, that is, el<ef, Il 1, which was initially set in the uppermost bit of the A register, is reset to II OII (step ■).

Also, the state of the read signal is “11”, that is, e 1
>e (If so, II II II set in the highest bit of the A register is left as is.

Next, it is determined whether all the digits of this A register have been completed (step
If I If is set to (with a weight of /2) (step ■).

As a result, a digital signal corresponding to 25th or 75% of the total capacity is set in the contents of the A register.

Here, the procedure returns to step (2) again, and operations in steps (2) to (2) are performed in the same manner as described above.

Here, in the operation of step ■, this time the third bit is II.
I II is cent.

In this way, until all the digits of the A register are completed in the operations of steps ① to ②, that is, the least significant bit of the A register is filled with II II+ or If □ If
continues until set.

Then, when all the digits are completed, the successive approximation mode ends,
The content D1 left in the A register is a value obtained by converting the input analog signal e1 into a digital signal using a successive approximation method, and its resolution corresponds to the number of bits of the D/A converter 30.

Subsequently, the device shifts to a mode (counting mode) in which A/D conversion operation is performed using a counting method.

In this counting mode, first, the contents of the counting counter formed in a part of the arithmetic control section 23 are reset (step 1).

In addition, a control signal is sent to the dither signal generation circuit 40, from which a dither signal of a sawtooth wave signal that initially changes to the positive polarity side is generated, for example, as shown in FIG.
).

Note that the amplitude of this dither signal es is determined by the ILSB (Least 51gn1ficant Bi) of the D/A converter 30.
t) is desirable.

When the dither signal es is generated, in the adder circuit 50,
This dither signal es is added to the analog signal eAt corresponding to Dl output from the D/A converter 30, and e
5+eAx will be applied to the other input terminal of the comparator 10.

Next, the processor 20 reads the output signal of the comparator 10 and determines the state of the signal (step 2).

Here, if the state of the read signal is II□l11, that is, el>ef (=es+eA1), 1 is added to the counting counter (step [phase]).

Thereafter, until the state of the output signal of the comparator 10 becomes "11゛1," that is, the input analog signal e1 and the adder circuit 5
The operations in step (2) and step [phase] are repeated until the signals e5+eA1 from 0 match.

When e1≦ef (2es+eA1), the counting mode ends, the contents remaining in the counter (count value ta) are stored, and the counter is then set (step 0).

Next, D1 obtained by adding ILSB to the data D1 obtained from the D/A converter 30 in successive approximation mode+D
Output the signal corresponding to 1+ILSB (step @)
.

Next, the dither signal generating circuit 40 generates a dither signal -e5 that changes to the negative polarity side (step 0).

When this dither signal 1 is generated, the adder circuit 50 converts the analog signal corresponding to D1+ILSB to e.

is subtracted, and e AI+ I LSB - e 5 is applied to the other input terminal of the comparator 10.

Next, processor 20 reads the output signal of comparator 10 and determines the state of the signal (step 0).

Here, if the state of the read signal is "l□II," that is, el<ef (=eAa +ILSB e,), 1 is added to the counting counter (step 0).

Thereafter, the operations in steps 0 and 6 are repeated until the state of the output signal of the comparator 10 reaches 11, that is, until the input analog signal e1 and the signal from the adder circuit 50 (eAt+ILSB e8) match. Repeat.

Then, when e1≧ef, move to step [phase],
Here, the contents td of the counter are stored, and the calculation t a /(t a +t b ) is performed using the contents ta of the counter obtained by the operations from step ① to step [phase].

As is clear from FIG. 4, this calculation result D2 is ta
corresponds to ex, and ta + tb corresponds to ILSB (provided that the slope angles θ of the positive and negative dither signals are both equal), and can be expressed by the following equation.

Subsequently, the processor 20 adds the digital signal D2 obtained in the successive approximation mode and the digital signal D2 obtained in the counting mode, as shown in FIG.

As a result, the resolution is improved by the portion D2, and a high-resolution digital signal corresponding to the input analog signal e1 can be obtained.

Further, even if the amplitude value of the dither signal changes, as long as the inclination angle θ that changes to the positive polarity side and the negative polarity side is equal, it has the advantage that it will not be affected, as is clear from the equation expressing D2.

In the above embodiment, the D/A converter 30 first outputs a signal corresponding to D1+ILSB, a negative dither signal is superimposed on this to obtain tb, and then the D/A converter 30 outputs a signal corresponding to D1+ILSB.
Alternatively, ta may be determined by outputting a signal corresponding to Dl from the converter and superimposing a positive dither signal thereon.

In each of the embodiments described above, the dither signal is superimposed on the output signal of the D/A converter, but the dither signal may be superimposed on the input analog signal.

As described above, according to the present invention, a high-speed, high-resolution A/D converter can be realized with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
The figure is a circuit diagram showing an example of a dither signal generation circuit, FIG. 3 is a flowchart showing an example of the operation of the processor, FIG. 4 is a diagram explaining the operation in counting mode, and FIG. 5 is a conceptual diagram of the converted digital signal. . 10... Comparator, 20... Processor, 30... D/A converter, 40... Dither signal generation circuit, 50...・Addition circuit.

Claims (1)

[Claims] 1. A comparator that receives a human analog signal as one input, a processor that receives the signal from the comparator and has at least a successive approximation function and a counting function, and converts the digital signal from the processor into an analog signal. It is equipped with a D/A converter that converts the signal into a signal, and a dither signal generation path that is configured to input the signal from the processor and output a signal that continuously changes between the positive polarity side and the negative polarity side over time. , the processor first stops the operation of the dither signal generation circuit, and also stops the operation of the comparator, processor, and D/A.
A loop is formed including a converter, and the loop converts the input analog signal into a digital signal using a successive approximation method, and operates the dither signal generation circuit to change the polarity to the positive side from the dither signal generation circuit. Time ta until the dither signal is superimposed on the output signal of the D/A converter corresponding to the digital signal D1 obtained by the successive approximation method and this superimposed signal matches the input analog signal.
At the same time, the output signal of the D/A converter is
1+ILSB, superimposes on this signal a dither signal that changes to the negative polarity side from the dither signal generation circuit, counts the time tb until this superimposed signal matches the input analog signal, and An operation for obtaining a digital signal corresponding to the input analog signal from the digital signal D1 obtained by the successive approximation method and the digital signal D2 obtained by performing the calculation □ using the count values ta and tb. An analog product that is characterized by
Digital converter.