JPS5936469B2 - synchronous circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference signal generation circuit for generating and deriving reference signals necessary for performing various signal processing and circuit control in synchronization with television signals, for example in a television receiver. Concerning a preferred synchronous circuit.

For example, when performing various signal processing and circuit control in synchronization with television signals in a television receiver,
A reference signal generation circuit is required to generate and derive a reference signal synchronized with a desired position of a television signal.

In this case, a synchronization circuit having a counter circuit is used to synchronize the counting operation of the counter circuit with a horizontal synchronization signal or a vertical synchronization signal separated from the video signal, and the desired position of the television signal is determined based on the output of this counter circuit. The aim is to obtain a reference signal synchronized with the FIG. 1 shows a reference signal generation circuit for generating a reference signal using, for example, a horizontal synchronization signal SH.

In the figure, 11 is the input end of the video signal, and this input end 1
A horizontal synchronization signal SH is separated from the video signal supplied to the horizontal synchronization signal SH by a horizontal synchronization separation circuit 12. This separated horizontal synchronizing signal SH is supplied to an automatic frequency control AFC circuit 13, and this horizontal AFC circuit 13 derives a pulse synchronized with the horizontal synchronizing signal SH. What is shown in FIG. 2a is the horizontal synchronizing signal SH separated by the horizontal synchronizing separation circuit 12, and what is shown in FIG. 2b is the output pulse P0 of the horizontal AFC circuit 13. This pulse P1 is supplied to the reset control circuit 14, and this pulse P1 is supplied to the reset control circuit 14.
4, a pulse P2 synchronized with the rising edge of the pulse P1 as shown in FIG. 2C is derived. This pulse P2 is supplied to the counter circuit 15 as a reset pulse. This counter circuit 15 counts the clock signal CP, and its count output is supplied to the ROM circuit 16. Note that the horizontal synchronization separation circuit 12, the horizontal AFC circuit 13, the reset control circuit 14, and the counter circuit 15 constitute a synchronization circuit. Said ROM circuit 1
6 derives a reference signal P3 synchronized with a desired position of the television signal based on the output of the counter circuit 15. This reference signal P3 is, for example, a pulse. Further, the ROM circuit 16 supplies the reset control circuit 14 with an inhibit pulse P4 as shown in FIG. 2d.

This inhibition pulse P4 performs the following function. That is, since the counter circuit 15 only needs to be reset once, if the counter circuit 15 is reset by the reset pulse P2 at a certain time, the reset pulse P2 will be reset at a certain time.
2 is no longer supplied to the counter circuit 15 due to the action of the inhibit pulse P4. To put this specifically, for example, when the power is turned on, when changing channels, or when synchronization is disturbed due to transmission distortion of television signals, the counter operation of the counter circuit 15 is not synchronized with the horizontal synchronization signal SH, and is performed arbitrarily. It will work. Therefore, in this state, the prohibition pulse P4 is out of phase with the set pulse P2, and the reset pulse P does not fall within the generation period of the prohibition pulse P4. Therefore, when the power is turned on, the counter circuit 15 is generated approximately first and is reset by the set pulse P2. As a result, the counting operation of the counter circuit 15 is synchronized with the television signal, and since the predetermined counting operation is repeated cyclically, there is no need to supply the second and subsequent reset pulses P2 to the counting circuit 15. do not have. Therefore, when the count circuit 15 is reset by the first reset pulse P2, R
The generation timing of the inhibit pulse P4 derived from the OM circuit 16 is controlled so that it is in phase with substantially the second and subsequent reset pulses P2. As a result, approximately the second and subsequent reset pulses P2 are no longer supplied to the counter circuit 15. However, in the above-mentioned synchronous circuit, even if the horizontal AFC circuit 13 synchronizes its output pulse P1 with the horizontal synchronizing signal Si, the horizontal AFC circuit 13
Jitter tends to occur in the output pulse P of the circuit 13, and this jitter becomes particularly large when the video signal contains ghosts.

In such a case, the reset pulse P2 will often occur outside the inhibit pulse P4, and each time the reset pulse P2
5 is set, making it impossible to obtain a reference signal synchronized with the television signal. In this case, if the pulse width of the prohibition pulse P4 is increased, the counter circuit 15
Since the reference signal is not set frequently, the reference signal can be synchronized with the television signal. however,
In this case, depending on the resetting of the counter circuit 15 and the generation position of the set pulse P2, the obtained reference signal P3
may be synchronized with a phase difference with respect to the desired position of the television signal. In addition, in this case, even if the phase of the television signal changes for some reason to a system-inconvenient state after the counter circuit 15 is reset, the counter circuit 15 is reset so that the reset pulse P2 does not deviate outside the period of the prohibition pulse P4. It is likely that the circuit 15 will not be reset, and the problem that the reference signal P3 will not be synchronously adjusted will also likely occur. Therefore, the reference signal generated in this manner cannot be used for signal processing or circuit control that requires strict synchronization with television signals. The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide a synchronization circuit that can accurately synchronize the counter operation of a counter circuit with a repetitive signal.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 shows an embodiment of the present invention, in which a counter correction circuit 1 is used instead of the reset control circuit 14 shown in FIG.
Since this circuit is the same as the reference signal generating circuit shown in FIG. 1 except that 7 is used, the same parts are given the same reference numerals and detailed explanations will be omitted.
That is, the horizontal synchronization signal SH as shown in FIG. 4a is derived from the horizontal synchronization separation circuit 12, and
From this, a pulse P1 as shown in FIG. 4b is derived. The output pulse P1 of the horizontal AFC circuit 13 is supplied to a counter correction circuit 17 and sampled using, for example, a clock signal CP used for counting by the counter circuit 15. As a result, a set pulse P2 as shown in FIG. 4c is generated near the rising edge of the pulse P1. When the power is turned on, when a channel is changed, or when synchronization is disturbed, the first pulse P2 of the set pulses P2 generated as described above is supplied to the counter circuit 15 and reset. Thereby, the counting operation of the counter circuit 15 becomes approximately synchronized with the horizontal synchronizing signal SH. Incidentally, the counter correction circuit 17 is supplied with an inhibit pulse P4 as shown in FIG. 4d from the ROM circuit 16. Here, this prohibited pulse P4 corresponds to the reference pulse of the present invention. When the power is turned on, this prohibition pulse P4 is usually out of phase with the approximately first reset pulse P2, but once the counter circuit 15 is reset, it is not in phase with approximately the second reset pulse P2. The phases will match. As a result, approximately the second and subsequent reset pulses P2 are no longer supplied to the counter circuit 15.
However, the pulse width of the prohibition pulse P4 in this case is shown in Fig. 2d.
Specifically, in a system in which this synchronous circuit is used, the set pulse P4 is set larger than the pulse width of the inhibit pulse P4 shown in FIG.
The time width is set to be greater than the deviation range of 2. Therefore, except when the power is turned on, when changing channels, or when synchronization is disturbed, jitter occurs in the output pulse P1 of the horizontal AFC circuit 13, and the set pulse P2 rarely deviates outside the generation period of the inhibit pulse P4. The counting operation of the counter circuit 15 is approximately synchronized with the horizontal synchronization signal SH. However, in this case, depending on the generation position of the first reset pulse P2, the counting operation of the counter circuit 15 may not be synchronized with the regular horizontal synchronization signal position, so the reference signal may also be synchronized with the television signal. There may be no. In other words, the first reset pulse P2
In the setting of the counter circuit 15 according to the method, the counting operation of the counter circuit 15 is merely synchronized with the approximate position of the horizontal synchronizing signal SH. To synchronize the counting operation of the counter circuit 15 with the regular horizontal synchronization signal position,
This is done by the counter correction circuit 17.

In addition to generating the reset pulse P2, the counter correction circuit 17 performs the following operations. That is, this counter correction circuit 17 detects at which position the reset pulse P2 has occurred during the generation period of the prohibition pulse P4, and uses this detection result in the generation period of the prohibition pulse P4 one period (one horizontal scanning period) before. Add to the detection result in . In this way, by cyclically inspecting the generation position of the reset pulse P2 for each horizontal scanning period and accumulating the detection results, the distribution state of the reset pulse P2 can be known. When a predetermined accumulation result is obtained, the accumulation operation is stopped and the position where the most reset pulses P2 are generated is detected. This detected position can be regarded as the regular horizontal synchronization signal SH position. Once the position where the set pulse P2 is generated the most is detected in this way, the counter correction circuit 17 forcibly resets the counter circuit 15 based on the detected position during the generation period of the inhibition pulse P4 in the next horizontal scanning period. do. This means that the counting operation of the counter circuit 15 is synchronized with the normal horizontal synchronizing signal position. Therefore, the reference signal P3 generated from the ROM circuit 16 is also synchronized with the desired position of the television signal. After this, if the channel is changed again or if synchronization disturbance occurs, the signal obtained from the output pulse P1 of the horizontal AFC circuit 13 or the set pulse P2
However, since it deviates from the generation period of the inhibit pulse P4, the above operation is repeated again, and the counting operation of the counter circuit 15 becomes synchronized with the normal horizontal synchronizing signal position. It goes without saying that while the counter correction circuit 17 is performing the accumulation operation, the reference signal P3 may be generated or may not be generated.

FIG. 5 shows an example of a specific circuit configuration of the counter correction circuit 7.

1? A is a sampling circuit which derives the set pulse P2 by sampling the output pulse P of the horizontal AFC circuit 13 using the clock signal CP.

When the power source is switched, when the channel is switched, or when the timing is disturbed, etc., the sampling circuit 17a samples the set pulse P2 first, and the set pulse P2 is sent to the counter circuit 15 via the set pulse switching circuit 17b.
is supplied and reset. This roughly synchronizes the counting operation of the counter circuit 15 with respect to the horizontal synchronizing signal. This reset pulse switching circuit Il
A prohibition pulse P4 is also supplied to b, which prohibits approximately the second and subsequent reset pulses P2 from being supplied to the counter circuit 15. The set pulse P2 sampled by the sampling circuit 17a is also stored in the buffer memory 17c at the timing of the repetition cycle of the clock signal CP during the generation period of the inhibit pulse P4.

That is, the time width of the inhibit pulse P4 is equal to the clock signal CP.
The buffer memory 17c also has n storage sections. Therefore, the sampling circuit 17a
In the sampling operation, the digital signals of 1' (reset pulse) and '0' obtained during the generation period of the prohibition pulse P4 are sequentially written into the corresponding storage section of the buffer memory 17c. , set pulse P2 to buffer memo I river 7c
When writing of information is completed, the following operations are performed until the next horizontal synchronization signal is separated.

That is, the data stored in buffer memory 17c is added to the data stored in memory circuit 17e by addition circuit 17d. That is, this memory circuit 17e has n storage sections each corresponding to the n storage sections of the buffer memory 17c(2). Each storage section of this memory circuit 17e is, for example, l.
It is said that it is possible to create bit digital data. In the above configuration, data in each storage section of the buffer memory 17c is sequentially read out to the addition circuit 17d. At this time, the adder 17d is further provided with a memory circuit 17e in synchronization with the data reading timing from the buffer memory 17c.
The 1-bit digital data in each storage section is also sequentially read out. During this operation, the data in the storage section of the buffer memory 17c is added to the data in the corresponding storage section of the memory circuit 17e by the addition circuit 17d. The 1-bit digital data for which the addition operation has been completed is written again in the same storage section in the memory circuit 17e from which it was read. When the above operation is completed for n corresponding storage units, the addition operation in a certain horizontal scanning period is completed. By performing the above operation every horizontal scanning period, the digital data value of the memory section corresponding to the position where the set pulse P2 is generated the most among the n memory sections of the memory circuit 17e0) increases. 17f is an accumulation judgment circuit, and for example, if the most significant bit of one of the n memory sections of the memory circuit 17e reaches 61, the accumulation is stopped after the addition operation has been completed up to n memory sections. Calculate the signal P.

This accumulation stop signal P5 stops the timing pulse generated from the ROM circuit 16 to drive and control, for example, the buffer memory 17c1, the addition circuit 17d1, and the memory circuit 17e, thereby stopping the accumulation operation. When the accumulation of the reset pulse P2 is completed, during the period of the inhibition pulse P4 that occurs immediately thereafter, the accumulation determination circuit 17f sets the most significant bits of the n storage sections of the memory circuit 17e to match the repetition period of the clock signal. Read at the same timing,
It is supplied to the reset pulse switching circuit 17b.

This reset pulse switching circuit 17b is connected to the memory circuit 17e.
The read data of the most significant bit from the counter circuit 1
Supply to 5. As a result, the counter circuit 15 becomes "1".
It is reset at the timing when the most significant bit in which is stored is read out. The reset pulse switching circuit 17
b also supplies an accumulation operation stop release signal P6 to the ROM circuit 16 when the phase of the prohibition pulse P4 and the set pulse P2 is shifted.

As a result, the ROM circuit 16 supplies timing pulses for driving and controlling the buffer memory 17c, addition circuit 17d1 and memory circuit 17e to these circuits, so that the above-mentioned accumulation operation of the set pulse P2 is performed. This embodiment described in detail above has the following effects. First, the distribution state of the generation positions of the reset pulses P2 is detected and the counter circuit 15 is reset at the position where the most reset pulses P2 are generated, so that the counting operation of the counter circuit 15 is normal. The probability of synchronization with the horizontal synchronization signal position is very high. Therefore, it is possible to obtain a reference signal P3 that is accurately synchronized with the desired position of the television signal, and is suitable for use as a reference signal for signal processing or circuit control that requires strict synchronization with the television signal. It is convenient for generation and derivation. In addition, by using the reset pulse P2 obtained from the output pulse P of the horizontal AFC circuit 13 to roughly synchronize the counting operation of the counter circuit 15 with the horizontal synchronization signal SH, the inhibition pulse P4 can be synchronized with the set pulse P2. Phase matching is performed, and the time width of the inhibition pulse P4 is set larger than necessary.

Therefore, even if the reset pulse P2 jitters during the accumulation operation of the reset pulse P2, it will not deviate from the prohibition pulse P4 period, so the accumulation operation of the reset pulse P2 can be performed accurately. , the reliability of the set information obtained by the accumulation operation is high. In addition,
The invention is not limited to the previous embodiments. For example, the counter circuit 15 may always be reset only by the result of the cumulative operation, without directly supplying the reset pulse P2 to the counter circuit 15. In this case, the reference pulse of the present invention does not have the function of prohibiting the supply of the set pulse P2 to the counter circuit 15, but
Of course, the counter circuit 15 is reset each time the reset pulse P2 deviates from the generation period of this reference pulse. Furthermore, the synchronization circuit of the present invention may be applied to a reference signal generation circuit that obtains a reference signal using a vertical synchronization signal, or to a reference signal generation circuit that synchronizes a signal different from a television signal. You may do so. Furthermore, the application is not limited to only reference signal generation circuits. As described above, according to the present invention, it is possible to provide a synchronization circuit that can accurately synchronize the counting operation of a counter circuit with a repetition signal.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing a conventional synchronous circuit, FIGS. 2 a to d are signal waveform diagrams of various parts to explain the operation of the circuit in FIG. 1, and FIG. 3 is a block diagram of a synchronous circuit according to the present invention. 4a to 4d are signal waveform diagrams of various parts to explain the operation of the circuit of FIG. 3, and FIG.
FIG. 2 is a block configuration diagram showing an example of a specific circuit configuration of a main part of the circuit shown in the figure. 15...Counter circuit, 16...RO
M circuit, 17... Counter correction circuit, 17a.
...Sampling circuit, 17b...Reset pulse switching circuit, 17c...Buffer memory, 17d...Addition circuit, 17e...
Memory circuit, 1? f... Accumulation determination circuit.

Claims (1)

[Claims] 1. Synchronization pulse generation means that outputs a pulse that follows the separated synchronization signal, and the average phase of the synchronization pulses is detected by cyclically extracting the output pulses of this synchronization pulse generation means and accumulating them. sample phase information generation means for generating sample phase information corresponding to this; a counter circuit that is reset by the sample phase information generation means and counts a predetermined clock signal; A reference pulse having a wider pulse width than the pulse width of the phase information generation means is generated, and it is determined whether or not an output pulse of the sample phase information generation means exists during this reference pulse period, and the reference pulse period is determined as follows. and counter correction means for resetting the counter only when the output pulse is present in the synchronization circuit.