JPS5936781B2 - Inner and outer integral methods of digital differential analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a digital differential analyzer (DigitalDi
fferentialAnaly2er, hereinafter referred to as DDA
) relates to an integral calculation method used to perform integral calculations.

Traditionally, analog computers have been used to calculate differential equations and continuous quantities such as trajectories and figures, but in recent years, digital computers have come into use due to the development of various software and faster calculation speeds. There are, but
Analog computers have advantages such as ease of handling and excellent human interaction, but disadvantages such as poor calculation accuracy and reproducibility, while digital computers have the advantage of superior quantitative data processing ability. On the other hand, as the calculation time increases in proportion to the complexity of the calculation, the operating cost becomes high, and it lacks interactivity with humans.
DDA has been proposed as a system that compensates for the drawbacks of both and at the same time has the advantages of both.

In other words, this DDA uses a digitized numerical signal as an input variable instead of the voltage or current value used in an analog calculator, and quantizes the finite increments of the numerical signalized input variable over time. It is sent to the output as a signal representing a numerical value, and its operating principle is based on the piecewise quadrature method.

Generally, the integral calculation formula Y = fx'DT + yo '゜' ゜ ゜ ゜ ゜ ゜ ゜ ゜ ゜ ゜ ゜ ゜ (1) (1) is Y = σ XI, ΔTi ...
...(2) If it is approximated as i■0 and an equivalent operation is performed on the above-mentioned numerical signal, the same operation can be achieved even if the entire configuration is converted into a digital circuit. be able to.

However, in order to achieve economic efficiency by simplifying the configuration when converting to a digital circuit, only one set of basic arithmetic circuits is provided, and the arithmetic results are obtained as increments of a constant value, and this is used as a ΔZ memory. At the same time, a set of arithmetic circuits is configured and operated as various arithmetic elements by an arithmetic mode command, and the content of the ΔZ memory is read and used as an arithmetic input for each arithmetic element. Furthermore, it is preferable to store the calculation results based on this in the ΔZ memory again, and to perform data access between each calculation element via the ΔZ memory.

Therefore, DDA uses a set of arithmetic circuits and specifies the function of the arithmetic circuit according to the arithmetic function required at each step in a series of calculations, and also uses the calculation results of the previous stage as the calculation input. It is a serial calculation method that uses a set of calculation circuits in a time-sharing manner.

For this reason, when operating a DDA, in the same way as an analog computer, the required calculation elements, such as integral multipliers and adders, are determined, and then how the inputs and outputs of these calculation elements are connected is determined. By operating the keyboard provided on the DDA, it is necessary to specify the function of the calculation elements at each calculation stage, give mutual connection information to the DDA, and store this information in the memory within the DDA. The above calculation operations are performed sequentially based on the information.

The present invention has the object of realizing an integrator that performs both interpolation and extrapolation, which are indispensable in implementing such a DDA, and which operates as an arithmetic element in the DDA and at the same time performs basic functions. It also serves as an arithmetic circuit and provides an extremely effective DA interpolation and extrapolation method that has high arithmetic speed and high arithmetic accuracy.

The details of the present invention will be explained below with reference to block diagrams showing examples.

In the figure, connection memories MCl to MC4 that store connection information between calculation elements, a scale memo MSl that stores initial values of calculation inputs, that is, unchanged components, and calculation mode signals that specify the functions of each calculation element are stored. The read addresses of the mode memory MM are specified sequentially from the first address by the output of the address counter CUA. It is applied as a read address designation signal to the address of the required content to a plurality of ΔZ memories MZl to MZ3 which sequentially store data at each address.

Note that after the end of the calculation and before the start of the next calculation, the selectors SLl to SL4 are activated by switching pulses from a separately provided timing pulse generator, and the output of the address counter CUA is sent to the ΔZ memories MZl to MZ4. The increment from the output circuit 0Z is written as the operation result ΔZ to the address of the ΔZ memories MZl to MZ4 designated at this time. ΔZ memory MZ read by addressing from connection memories MCl to MC3
The contents of l to MZ3 are signals representing the increment of the calculation result in the previous calculation, and these are given to the first adder ADl as calculation inputs ΔY1 to ΔY3 in the current calculation, where each input ΔY1 to ΔY3 is mutually Σ is added to the first multiplier MLl and the second multiplier ML2.
It is sent out as ΔYi.

Note that i in ΔYl is an index indicating the current calculation, and the immediately preceding one is displayed as 1-1 from now on. Furthermore, when operating as an integrator, the ΔZ memory MZ4 stores minute increments representing each division of the independent variable This is sequentially read out by addressing the address counter CUA, and is always given to the arithmetic unit 0P, which will be described later, as an independent variable of numeric value.

Therefore, in this case, the output of the ΔZ memory MZ4 is not provided to the first adder ADl. This (maka, ΔZ memory M
The signals from Zl to MZ3 consist of a total of 2 bits: 1 bit indicating positive/negative and 1 bit indicating the numerical value 111 or 80°, and since these are added, the output of the first adder ADl is the total The result of addition is represented by 4 bits.

The output of the first adder ADl is multiplied by the scale signal S from the scale memory MS in the first multiplier MLl and the second multiplier ML2.
ΣΔYi and sent to the second adder AD2, but in the second multiplier ML2, in order to correct the difference, that is, error between the rectangular piecewise area and the area including the curve in the piecewise quadrature method, the first multiplier The same calculation as MLl is performed to obtain SΣΔYi corresponding to the rectangular area with the increment as one side, and this is sent as an error correction signal to the third adder A8, which will be described later.

Note that in the first and second multipliers MLl and ML2, the numerical values naturally increase due to multiplication, and a signal with a number of bits that can represent the expected maximum number is required, but for convenience, these outputs are represented by 16 bits. I take it as a thing.

The second adder AD2 is the output SΣΔYi of the first multiplier MLl.
and the contents of a register RY called the Y register, but the result is immediately given to the Y register RY to update and temporarily store the contents, so that the previous addition result Yi-1 is Y Yi-! from the register RY, and the addition result with the output of the first multiplier MLl. +S
ΣΔYi is sent to the third adder AD3 as a 16-bit signal.

The third adder AD3 is Yi-1+SΣ of the second adder AD2.
The output indicating ΔYi and the error correction signal from the second multiplier ML2 are added, and this signal is shifted to the lower order by one bit to become (1/2) SΣΔYl, and then the signal is transferred to the mode memory M.
When an interpolation integration mode signal is given from M, (1/2) SΣΔY1 is subtracted from the output of the second adder AD2,
When the extrapolation integration mode signal is given, the second adder A
Add to the output of D2, and according to the extrapolation and interpolation integral (Yi-
1+SΣ! FYi)±(1/2)SΣΔYi is obtained, and after adding or subtracting 1/2 of the rectangular area with the increment as one side, this is sent to the arithmetic unit 0P as a 16-bit signal.

The arithmetic unit 0P gives a minute increment less than a fixed value in the arithmetic result to a register RR called an R register, and sequentially registers and accumulates it, while also inputting the output of the third adder AD3 and Δ
The contents Ri-
Add the 16-bit signals indicating 1, and calculate {(Yi-1+S
After obtaining ΣΔYi)±(1/2)SΣΔYl}ΔX+Ri-1, it is sent to the output circuit 0Z as a 16-bit signal.

Note that the arithmetic unit 0P is an integrated circuit ALU (Arithmetic LOgic Uni
t) circuits etc. are suitable.

The operation of the output circuit 0Z is determined by the integral multiplier mode signal from the mode memory MM, and the increment in the output from the arithmetic unit 0P is a quantized constant value, i.e. +
When it reaches 1- or 1-pi, it is sent as a 2-bit signal representing this, and as mentioned above, the address counter CUA
Based on the address designation, the calculation results are written sequentially from the first address of the ΔZ memories MZl to MZ4. However, if the increment does not reach either ``+1゛'' or ``0'', O'' is sent out, and the 2-bit signal is 1 bit indicating positive or negative, or 1 indicating 0''. Furthermore, the calculation results stored in the ΔZ memories MZl to MZ4 are used as calculation inputs in the next calculation operation.The calculation inputs ΔY1 to ΔY given to the first adder ADl are thus Integral multiplication is performed based on ΔY3 and the independent variable ΔX from the ΔZ memory MZ4, but since the independent variable ΔX is always 1, the result is a simple integration, and the increment is 1+pi or -bi or ΔZ memory MZl as a ΔZ signal of 0゛
~MZ4, and the calculation operation as an integrator is completed.

Note that the output circuit 0Z is the most significant bit of the R register RR,
It operates based on the most significant bit in the output of the third adder AD3, the most significant bit in the output of the arithmetic unit 0P, and each bit of the 2-bit signal representing ΔX from the wired memory MC4, and uses the truth value table shown in the following table. produces the output shown in

The most significant bit of the third adder AD3 and the most significant bit of the arithmetic unit 0P represent positive by O and negative by 1. For example, (1 in the previous table) ), the content of the R register RR is positive, and from this, the positive output of the third adder AD3 is subtracted, that is, negative addition is performed by the independent variable ΔXOOl, and the output of the arithmetic unit 0P at this time is positive. If so, it indicates that a positive arithmetic operation has been performed, and when the increment of the result is less than 1+pi, a value of ``0'' is sent from the output circuit 0Z,
As shown in Table (3), even if it is positive and positive, the output power of the arithmetic circuit 0P will be 6-bi or 6-bi if it exceeds it.

However, this combination of truth values is omitted because it does not become the output of the output circuit 0Z. Further, since the circuit for obtaining the operation results shown in the preceding table can be easily constructed by combining various gate circuits, the details thereof will be omitted.

In addition, the above calculation operations are performed within one period of the timing pulse that regulates the period in which the integrator operates, and in the next period it operates as another calculation element, but this operation The timing pulse instructing the start starts the operation of the result memories MCl to MC4 and the first adder ADl, and the operations are performed in parallel in synchronization with the clock pulse generated in the same way as the timing pulse. Due to the asynchronous operation, the operation is completed within one period of the timing pulse, and the combination of this parallel operation and asynchronous operation reduces the required calculation time, and the operation as an integrator is completed in approximately 480 nsec, resulting in extremely high calculation speed. It has become a matter of speed.

The above-mentioned integrator includes all the basic circuits required to configure other various calculation elements, and includes the operation modes of the third adder AD3, output circuit 0Z, etc., and the output of the ΔZ memory MZ4, By slightly changing or switching the connections at various places such as the inputs of the first and second multipliers MLl and ML2, each operational element such as an integral multiplier, an adder, a coefficient unit, an integral comparator, an operational amplifier, etc. can be configured. .

In addition, connection memories MCl to MC4 to ΔZ memory MZl
The illustrated configuration can be modified in various ways, such as by determining the number of systems for MZ4 and the like as necessary.

As is clear from the above description, according to the present invention, an integrator with high calculation speed and high calculation accuracy that handles digital signals as calculation input can be realized with the minimum necessary configuration, and at the same time,
Since everything is constructed from digital circuits, the reproducibility of calculations is ensured, and other calculation elements are constructed with slight modifications, making it extremely effective as a basic calculation circuit for DDA.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the present invention.

Claims (1)

[Claims] 1. A first adder that mutually adds signals representing increments read from a plurality of arithmetic result memories that store increments of arithmetic results, and a scale signal from a scale memory that stores the output of the first adder and an initial value. A first multiplier that multiplies the contents of the Y register and a second multiplier that performs the same multiplication as the first multiplier and sends out an error correction signal; a second adder that adds the output of the second multiplier, and a second adder that subtracts the output of the second multiplier from the output of the second adder when performing interpolation integration, and a second adder that adds the output of the second multiplier when performing interpolation integration; a third adder that adds the output of the second multiplier to the output; and a third adder that registers an increment less than a certain value to the R register, and a link between the output of the third adder and an independent variable whose numerical value is always "1". an arithmetic unit that performs multiplication and adds the contents of the R register to the multiplication result; an output circuit that sends out an increment that reaches a certain value based on the output of the arithmetic unit as an arithmetic result and stores it in the arithmetic result memory; An interpolation-integration and extrapolation-integration method for a digital differential analyzer characterized by comprising the following.