JPS593756B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a method of changing the pitch of a musical tone generated when two different keys are pressed in sequence to a pitch corresponding to one key (hereinafter referred to as the first operation key). An electronic device that can produce a portamento sound effect or a glitsando sound effect by changing the pitch (frequency) continuously or stepwise from the pitch (frequency) corresponding to the other key (hereinafter referred to as the second operation key). It concerns the improvement of musical instruments.

In recent years, with the rapid development of electronic technology, various types of electronic musical instruments have been developed.Electronic organs, which are typified by electronic musical instruments, are capable of producing many tones and various sound effects, making them ideal for musical expression. It is widely used as an instrument that can produce a wide range of sounds and is relatively easy to play, even for beginners.

In this case, there has been a strong desire to further improve the performance effect of electronic musical instruments by adding the glissando effect and portamento effect used in natural musical instruments.

Conventionally, an electronic musical instrument equipped with a portamento function as shown in FIG. 1 has been proposed to meet these demands. To explain the electronic musical instrument shown in FIG. 1, this kind of electronic musical instrument generates a voltage signal KV(
It generates a tone pitch voltage (hereinafter referred to as a tone pitch voltage KV), and also generates a pulse signal (hereinafter referred to as a key-on signal KO) having a time width corresponding to 15 times the key depression time. The pitch voltage KV obtained from this keyboard section 1 is driven to oscillate by a voltage-controlled variable frequency oscillator T (hereinafter referred to as F0VCO) through a voltage holding time constant circuit 2 consisting of a switch element 3, a variable resistor 4, and a capacitor 5. This VCO 7 outputs a sound source signal corresponding to the pitch of the operating key. This V
The sound source signal output from the COT is supplied to a voltage-controlled variable filter 8 (hereinafter referred to as VCF) to form a tone and produce a musical tone signal. A control type variable gain amplifier 9 (hereinafter referred to as VCA) controls the musical tone signal level, that is, the envelope, and extracts the musical tone signal, amplifies it appropriately in an amplifier 10, and produces it as a performance sound from a speaker 11. In this case, the key-on signal KO is generated by the voltage holding time constant circuit 2 that holds the tone pitch voltage KV and the control device 1.
2 as control signals. This control device 12 generates a control waveform signal whose voltage value changes over time based on the coupled key-on signal KO, which rises when the key is pressed, continues for 5 seconds, and then falls from the time the key is released. This control waveform signal is applied to the above VCOT, VCF8, VC
A9 is supplied to the CO7 according to this torpedo waveform signal.
The oscillation frequency is slightly changed in the VCF8, and the cutoff frequency is changed in the VCF8 to produce a musical tone signal rich in naturalness and musicality.

Further, in CA9, an envelope for the level of musical tone is set according to the control waveform signal. The voltage holding time constant circuit 2 includes a switch element 36, a variable resistor 46, a capacitor 5, and a switch element 36 controlled by a key-on signal KO. and a portamento effect selection switch 6. During normal performance, the selection switch 6 is turned on as shown in the figure, and the pitch voltage KV generated as a result of key operation is transferred to the switch element 3 and the selection switch 6. VCO directly via 6
7 and the high pitch voltage K to the capacitor 5.
Memorize V. The capacitor 5 is used to hold the sound pitch voltage K in order to obtain a sustain (attenuation) sound after the key is released, and the switch element 3 is connected to the capacitor 5.
This is to prevent the holding voltage from discharging. When performing portamento in the electronic musical instrument configured as described above, by turning off the portamento effect selection switch 6, the pitch voltage KV is charged to the capacitor 5 via the variable resistor 4, and the capacitor 5 The terminal voltage changes in accordance with the time constant formed by the variable resistor 4 and the capacitor 5.

In this case, the 6 capacitor 5 is the previous pressed key (first operation key).
The tone pitch voltage KV, corresponding to is held, and when the tone pitch voltage KV2 corresponding to a newly pressed key (second operation key) is generated, the tone pitch voltage KV, corresponding to The terminal voltage of the capacitor 5 changes continuously as shown by the solid line A in FIG. 2, and as a result, the oscillation frequency of the VCO 7 changes continuously as shown by the solid line A in FIG. The pitch changes continuously from the pitch to the pitch of the second operation key. Next, the above explanation describes the operation when the pitch of the second operation key is higher than the pitch of the first operation key, but the pitch of the second operation key is higher than the pitch of the first operation key. If it is low, the terminal voltage of the capacitor 5 changes from the tone pitch voltage KVl corresponding to the first operation key stored in the capacitor 5 to the dotted line B in FIG. 2 according to the time constant of the resistor 4 and capacitor 5.
As shown in , the pitch voltage changes continuously down to K2 corresponding to the second operation key, and as a result. The oscillation frequency of the VCO 7 changes continuously according to the dotted line B in FIG. 2, and the pitch changes continuously downward from the pitch of the first operating key toward the pitch of the second operating key. In this way, a portamento sound effect in which the pitch of the generated musical sound continuously changes from the pitch of the first operating key to the pitch of the second operating key can be easily obtained. However, in an electronic musical instrument having such a portamento performance device, the change in pitch of the sound source signal obtained from the VCO 7 has the waveform shown by the solid line A and the dotted line B in FIG. 2 in response to the change in the terminal voltage of the capacitor 5. In the past, portamento sound effects could only be obtained in a pitch change mode that was fast at first and then changed gradually, and as a result, portamento sound effects were monotonous and lacked variation. An object of the present invention has been made with the above-mentioned in mind, and it is an object of the present invention to make it possible to appropriately select the pitch change mode of the sound effect when obtaining a portamento performance sound effect or a glitsando performance sound effect. To provide an electronic musical instrument capable of obtaining a voltament performance sound effect or a glissando performance sound effect in pitch change mode. Hereinafter, the electronic musical instrument according to the present invention will be explained in detail using the drawings.

FIG. 3 is a circuit diagram of a main part showing an embodiment of an electronic musical instrument according to the present invention, and the same parts as in FIG. 1 are given the same symbols and the explanation thereof will be omitted.

In the figure, 13 is a voltage-controlled variable resistor (hereinafter referred to as 6VCR) connected between the switch element 3 and the capacitor 5, and has a resistance value corresponding to the voltage value supplied to the control terminal 13a. , for example, a field effect transistor. 14 is a first pitch change mode setting circuit that generates a constant voltage +. 15 is capacitor 5
16 is a third pitch change mode setting circuit that sends out the terminal voltage KV' of the capacitor 5 through the exponential amplifiers 16a and 16b. , 17 are fixed contacts a-c
The output signals from the first to third pitch change mode setting circuits 14 to 16 respectively supplied to the VCR13 are selected.
This is a pitch change mode selection switch that is supplied to the control terminal 13a of the pitch change mode.

In the circuit configured as described above, when the movable contact d of the pitch change mode selection switch 17 is switched and connected to the fixed contact a as shown in FIG. A voltage +V is supplied to the control terminal 13a of the VCRl3.

On the other hand, it is assumed that the capacitor 5 stores and holds the sound pitch voltage KVl corresponding to the first operation key, and when the second key is operated in this prone position, the keyboard part
A tone pitch voltage KV2 and a key-on signal KO corresponding to the second operating key are generated. The sound high voltage KV2 is the key-on signal K
The capacitor 5 is charged via the switching element 3 and CR13, which are in the on state due to the voltage O. In this case, since the control input signal of the VCR13 is a constant voltage value +V supplied from the first pitch change mode setting circuit 14, it continues to maintain a constant resistance value corresponding to this voltage +V. Therefore, capacitor 5 is charged in accordance with a time constant determined by the value of VCR13 and the value of capacitor 5, which continue to maintain this constant resistance value. As a result, the terminal voltage KV' of the capacitor 5 rises along the integral characteristic shown by the solid line A in FIG. 4, and like the conventional portamento device shown in FIG. High change mode. Next, when the movable contact of the pitch change mode selection switch 17 is switched to the fixed contact b, the output signal of the pitch change mode setting circuit 15 changes to VCR13.
is supplied to the control terminal 13a of. Therefore, when the second key is operated in the prone state where the pitch voltage KVl corresponding to the first operating key is held in the capacitor 5, the pitch voltage KV2 corresponding to the second operating key is transferred via the VCRl3. The capacitor 5 is charged. In this case, the pitch change mode setting circuit 15 is constituted by one exponential amplifier 15a that amplifies the terminal voltage KV' of the capacitor 5 with an exponential characteristic. It generates an output obtained by exponentially converting the terminal voltage KV' of No. 5.
For this reason, the resistance value of the VCR13 changes along an exponential characteristic, that is, the resistance value changes slowly at first and then changes quickly.

Therefore, capacitors generally have integral characteristics (Figure 4A)
The terminal voltage rises with VCRl
By exhibiting such an exponential change in resistance value, the integral characteristic is canceled and the terminal voltage of capacitor 5 KV
' is a change from the pitch voltage KVl to K as shown by the solid line B in Figure 4.
It increases linearly towards V2. Therefore, the portamento sound effect when the pitch change mode setting circuit 15 is selected by the pitch change mode selection switch 17 is as follows.
This is a pitch change mode in which the pitch changes at a constant speed from the beginning to the end over the range from the first operation key pitch to the second operation key pitch. Next, press pitch change mode selection switch 1.
When the movable contact d of 7 is switched and connected to the fixed contact c, the output signal of the pitch change mode setting circuit 16 changes to ? of the VCR13. b
It is supplied to the single leg terminal 13a.

In this case, the pitch change mode setting circuit 16 is connected to the exponential amplifier 1.
6a and 16b are connected in series in two stages, this pitch change mode setting circuit 16 exhibits a double exponential characteristic, and along with this, the resistance value of the VCR13 also has a double exponential characteristic. It will change along the exponential characteristic. As a result, when the second key is operated while the tone pitch voltage KVl corresponding to the first operation key is held in the capacitor 5,
The pitch voltage KV2 corresponding to this second operation key is VCRl3.
The capacitor 5 is charged via the capacitor 5. In this case, CRl
Since the resistance value of capacitor 3 changes along a double exponential characteristic, the integral characteristic shown in Fig. 4A is canceled and becomes an exponential characteristic, and the terminal voltage K/ of this capacitor 5 is as shown in Fig. 4c.
The pitch voltage increases to the pitch voltage K2 corresponding to the second operation key along the exponential characteristic shown in FIG. Therefore, when the pitch change mode selection switch 17 selects the output signal of the pitch change mode setting circuit 16, the portamento sound effect changes gradually at first. After that, the pitch changes mode changes rapidly, and becomes the same pitch change mode as when performing portamento using a natural musical instrument. In this way, by selecting the output signals of the pitch change mode setting circuits 14 to 16 by the pitch change mode selection switch 17 and supplying them to the VCR, the pitch change in the portamento sound effect can be changed in an integral characteristic or a straight line. It can be changed in a fixed or exponential manner, and thereby portamento performance sound effects with various pitch change modes can be obtained, allowing for rich musical expression. In addition, in the above-mentioned embodiment, CRl
3 is used to configure the pitch change setting section, but the present invention is not limited to this. For example, a conductance converter proposed by the present applicant in Japanese Patent Application No. 75067/1982 may also be used. good.

In the embodiment described above, the present invention is applied to an electronic musical instrument in which a portamento sound effect is obtained through analog processing, but next, a portamento sound effect and a grissando sound effect are obtained through digital processing. A case where the present invention is applied to an electronic musical instrument will be described. FIG. 5 is a block diagram schematically showing the overall configuration of another embodiment of the electronic musical instrument according to the present invention, which can be roughly divided into key switches provided corresponding to each key, which are operated by pressing a key. A key coater 100 that detects a key switch (closing operation in the case of a meter contact, opening operation in the case of a break contact) and generates a signal (key information) 6 representing the detected key switch, that is, a key code KC; Channels that can simultaneously sound the supplied key code KC (much fewer than the number of keys).

), and a channel processor 200 for executing the operation of assigning to one of the channels; A key code converter 300 converts the key code KC' into a key code KC'; a key code/pitch voltage converter 400 generates a pitch voltage KV corresponding to the key code KC' supplied from the key code converter 300; a channel-by-channel tone pitch voltage control section 500 that controls the tone pitch voltage KV in response to key presses and key releases of operation key switches assigned to each channel by the processor 200;
Controls the musical tone forming section 600 that generates musical tone signals corresponding to the tone pitch voltages K supplied from each channel of the channel-specific tone high voltage control section 500 for each channel, and the channel-specific tone high voltage FhI leg section 500. A pitch voltage control section 700 controls the switching between glitsando and portamento and its speed; a timing signal generation section 800 supplies various timing signals to each section mentioned above; and a timing signal generating section 800 controls pitch changes during portamento performance or glitsando performance. It is composed of a pitch change mode control section 900.

In the key coater 100, a large number of key switches 10
A key switch circuit 102 having circuits 1a to 101n is provided, and each key switch 101a to 101n of this key switch circuit 102 is divided into a plurality of blocks (for example, a group for each otatorb), and each key switch in each block is divided into a plurality of blocks. notes (e.g. C,
C#, D, . . . R), one terminal (movable contact, ω
Connect the a side to the same notes of each block, pull out the wiring N1 to Nm for each note, and connect the other terminal (
Fixed terminals) b sides are commonly connected for each block, and wirings B1 and B2 are drawn out for each block.

Therefore, this key switch circuit 102 has block wirings B1 to Bl as "rows" and note wirings N1 to Nm as "rows". 101n are connected to each other. As a result, the total number of wires drawn out from the key switch circuit 102, that is, the total number of wires of the block wires B1 to B' and the note wires N1 to Nm, is much smaller than the number of all the key switches 101a to 101n. ing. For example, assuming that the number of all the key switches 101a to 101n is "゜1Xm", in this case, the total number of wires drawn out from the key switch circuit 102 is the number of procs 2+the number of notes m, and the number is "'+m". Become. Each key switch 101a to 101n of the key switch circuit 102 configured in this way is connected to the note detection circuit 103 via note wiring N1 to Nm.
It is also connected to the block detection circuit 104 via block wirings B, .about.Bl. In this case, the detection of all operating key switches among all key switches 101a to 101n is performed under several types of detection operating states (hereinafter referred to as
The detection operation is completed by sequentially executing states (simply referred to as states).

The first state (STl) is the note detection circuit 103
Apply a signal to the movable contact side a of all the key switches 101a to 101n via the notebook wiring N, to Nm,
The applied signal is derived through the fixed contact side b of only the key switch in operation to the block wirings B1 to B1 of the block to which the key switch in operation belongs, and the derived signal is supplied to the block detection circuit 104 and stored.
This will tell you which procs are running (turned on).
The presence of one or more keys is detected. In addition. The storage timing of the block detection circuit 104 in this first state is determined by the state control circuit 104 operating in synchronization with the timing signal generation section 800.
The first state signal is determined by the first state signal provided by the first state signal.
When the storage operation of block detection circuit 104 is completed, state control circuit 105 detects this and controls the second state. Next, in the second state (ST2), the block (
1 process or multiple processes) according to a predetermined priority order,
A signal is applied to the fixed contact b side of each key switch included in the block through the block wiring B1 to Bl corresponding to the block pushed out from the block detection circuit 104,
As a result, the signal is derived from the note wirings N1 to Nm on the movable contact a side of the key switch of each note in the block and is stored in the note detection circuit 103.

In this way, the operating key switches 101a to 1
The signal from the block detection circuit 103 is transmitted only to the note wirings N1 to Nm corresponding to 01n, and by storing this signal in the note detection circuit 103, Notes on the key switch(es) will be detected. Furthermore, the block signal extracted by the block detection circuit 104 is converted into a multi-bit (in this case 3 bits) block code signal (hereinafter referred to as block code BC) representing the block and sent to the sample and hold circuit 106. Supply and memorize. Note that the 1-block J block extraction timing of the block detection circuit 104 and the storage timing of the note detection circuit 103 in this second state are based on the second state supplied from the six-state control circuit 105, as in the case of the first state described above. determined by the signal. When the note detecting circuit 103 completes three memorizing movements, the lying state control circuit 105 detects this and controls the third state. Next, the third state (ST3) is an operational state following the second to second states, and the note detection circuit 10 in the second state
The notes 4 (one or more) stored in the notes 3 are extracted sequentially in synchronization with the system clock and according to a predetermined priority order, and the extracted note signals are converted into multiple bits representing the notes ( In this case, it is converted into a 4-bit note code signal (hereinafter referred to as note code NC) and sequentially supplied to the sample and hold circuit 106.

Since this third state is executed only for notes stored in the note detection circuit 103, no time is wasted. For example, if three types of notes are stored in the note detection circuit 103, the third state related to six procs will be completed in three clock times. 6 When all the note code signals stored in the note detection circuit 103 are read out, the state control circuit 1
05 detects this and controls to the next state. In this case, if the block signal is still stored in the block detection circuit 104, control returns to the second state and the third state. These states are executed in the same manner as described above. In addition, if there is no memory of a block signal in the block detection circuit 104, the charge remaining in the block wirings B1 to Bl of the key switch circuit 102 (the stray capacitance of the wiring or the charge in the minute capacitors connected to each wiring) After all charges are discharged and set, the state returns to the first state. On the other hand, the sample and hold circuit SlO6 stores and holds the block code BC supplied from the block detection circuit 104 in the second state, and is synchronized with the note code NC supplied from the note detection circuit 103 in the third state. and output.

Therefore, the sample and hold circuit 106 sends out a key code KC having a 7-bit configuration in which a block code BC and a note code NC are combined, and the operating key switch can be easily identified by this key code KC. can do. In this way, the first state (S
Tl) → second state (ST2) → third state (ST
3) Steps like this, or send out the block code BC related to all the programs first stored in the block detection circuit 104, and send the note code NC related to the note of the operating key switch in the last program.
When the data has been sent out, all of the memories in the block detection circuit 104 and note detection circuit 103 are extracted and are completely erased, resulting in a fourth state (STO entry, that is, a standby state).

Then, the key switch circuit 102 and the note detection circuit 10
After confirming that all the operations of 3 and the block detection circuit 104 have been reset, the state returns to the first state (STl).
After that, as mentioned above, the second state (ST2
), by repeating the third state (ST3) and reaching the fourth state (STO), that is, the waiting state,
The detection operation for all key switches is repeated once. The key code KC sent out from the sample hold circuit 106 of the key coater 100 is supplied to the channel processor 200, where it is assigned a channel that forms a musical tone signal.

In this case, the key code KC sent from the sample and hold circuit 106 is held for a certain period of time, and this holding time corresponds to the operating time during which one assignment process is executed in the channel processor 200. In addition, this key coater 100 converts all of the operation key switches into corresponding key codes KC and converts the start signal and send it.

This signal X is used in channel processor 200 for key-off detection. In addition, this key coater 1
Block code B of key code KC sent from 00
Table 1 shows an example of the contents of C and note code NC.

Next, the channel processor 200 includes a first key code memory 201, a key on/off detection circuit 202, a truncate circuit 203, and a key press state memory 204.

The first key code memory 201 is provided with a specific number of storage circuits corresponding to the number of channels that can be sounded simultaneously, and this storage circuit is advantageously constructed of a rotating shift register. In this case, if the number of channels is A and the number of bits of key code KC is B, then A has B storage units.
A stage (1 stage = B bits) shift register is used, and the recorded and recorded (already assigned) key codes KC are sequentially shifted by clock pulses and sent out in a time-division manner to generate musical waveforms. The signal is used as a control signal for the shift register, and is fed back to the input side of the shift register for circulation. The key-on/off detection circuit 202 compares the input key code KC supplied from the key coater 100 with all stored key codes KC sequentially sent out from the first key code memory 201 in a time-sharing manner, and if they match, the input key code KC is A key code KC identical to the code KC is assumed to have already been assigned to a certain channel, and is prevented from being stored in the first key code memory 201, that is, the channel assignment is stopped.

Furthermore, if the comparison results described above do not match, it means that a new key was operated, so this input key code K
C is stored in all empty channels of the first key code memory 201. Furthermore, if the above comparison results do not match and other key codes KC have already been assigned to all channels, the sound that has been most attenuated among the sounds that have already been separated by the truncate circuit 203 is assigned. Detect the channel that is being stored and enter the key code KC stored in this channel.
Control to forcibly rewrite to C. In addition, this key-on/off detection circuit 202 supplies the assignment state of the input key code KC to each channel to the key press state memory 204 for storage, and uses the readout output to determine the sound generation operation of each channel, which will be described later. At the same time, when a key is released, the stored contents of the corresponding channel in the key press state memory 204 are changed, and the sound of the channel is controlled according to predetermined conditions, that is, gradually attenuated. Terminate pronunciation. In the subsequent operation, an empty channel is selected from the contents stored in the key press state memory 204, and the input key code KC is stored in the stage of the corresponding channel in the first key code memory 201. The first key code memory 201 and the key press state memory 204 are arranged so that signals are stored by selecting portions corresponding to each channel in a time-sharing manner in synchronization with each other. Next, the key code converter 300
Only when a control signal is supplied to the key code shift control terminal 301, the key code KC sequentially supplied from the channel processor 200 is processed to generate a key code corresponding to a predetermined range, that is, a certain operated key. K.C.
This is the part that converts the key code KC corresponding to the next operated key into a key code Kσ that is sequentially shifted (including addition and subtraction) under certain conditions over the range of the key code KC corresponding to the next operated key. I have obtained the key code KC5 to obtain the effect. The key code conversion unit 300 is composed of a key code shift control terminal 301 and a circular shift register having a number of storage stages equal to the number of channels, and sequentially converts the key codes KC supplied from the channel processor 200. Only when a control signal is supplied to the second key code memory 302 and the key code shift control terminal 301 to store the calculated key code KC', which is obtained by adding or subtracting a predetermined value to the output key code Kσ of the second key code memory 302. an arithmetic circuit 303 that causes the second key code memory 302 to store the code again;
a comparison circuit 304 that compares the input key code KC supplied from the channel processor 200 and the output key code KC' of the second key code memory 302, and stops the arithmetic processing of the arithmetic circuit 303 when the two match; It is configured. The addition and subtraction in the arithmetic circuit 303 are controlled by the comparison result signal supplied from the comparison circuit 304, and the output key code KC' of the second key code memory 302 is output from the channel processor 200. If it is larger than the supplied input key code KC, subtraction is performed and the second key code memory 30
2 output key code KCθ1 channel processor 20
If it is smaller than the input key code KC supplied from 0, addition is performed. In other words, when a key with a pitch higher than the pitch of the key operated first is operated next, addition processing is performed and the output key code Kσ of the second key code memory 302 is changed to the key with a higher pitch. As a result, the tone forming section 600, which will be described later, generates a musical tone signal in which the pitch rises in steps in order to obtain a glitsand effect, or a tone signal in which the pitch is successively shifted. A musical tone signal is generated that rises to a certain level and produces a voltament effect. Note that the calculation cycle in the calculation circuit 303 is determined by a speed control pulse supplied to the speed control terminal 305, thereby variably controlling the speed of the glissando and portamento. Next, the key code tone pitch voltage converter 400 includes a sampling circuit 401, a sampling control circuit 402 that controls the sampling period, and a digital-to-analog conversion circuit 403.

This key code/pitch voltage converter 400 converts the key code KC' supplied from the key code converter 300 to
is sampled in a sampling circuit 401, and the sampled key code Kσ is supplied to a digital-to-analog conversion circuit 403. In this case, the sampling period of the sampling direction path 401 is determined by the output of the sampling control circuit 402, and that period is the second
This is the time when the number of clocks for shifting the contents of the key code memory 302 is counted one more than the number of channels. Therefore, the sampling circuit 401 is
Almost every time the second key code memory 302 is shifted, key codes Kσ corresponding to different channels are sequentially sampled, and this sampled key code KC'' is continued to be output until the next sampling time. This is because the key coater 100 and channel processor 200 perform deceleration sampling by the key switches 101a to 101n.
It is necessary to quickly detect the state (key pressed state and key released state) and assign it to a channel, whereas the part that handles the pitch voltage requires high-speed operation because it is processed in parallel. In addition, if the high voltage of the analog signal is handled at high speed, the operation will not follow. That is, the waveform becomes dull due to the minute capacitance in the circuit system, and as a result, it becomes impossible to obtain an accurate musical tone that matches the key code KC'.
For these various reasons, deceleration sampling of the key code KC' is performed to form a deceleration sampled key code KC'. A digital-to-analog conversion circuit 403 connected to the output side of the sampling circuit 401 is a part that converts the above-mentioned key code KCi into a corresponding tone pitch voltage K. This digital/analog conversion circuit 403
is the key code KC! which has been decelerated and sampled by the sampling circuit 401 as described above. ' is input, and this key code KC' is divided into a block code BCI and a note code NC'' and each is decoded.Then, the block code is inputted from the resistance voltage divider circuit by the decoded output of the block code BC'. Take out the voltage signal corresponding to
By further dividing the voltage signal corresponding to the note by decoding the note code NC', the pitch voltage KV corresponding to the key code Kσ is generated.
occurs. This tone pitch voltage KV is controlled by the control signal supplied from the sampling control circuit 402 to each sampled key code KC of the sampling circuit 401.
! I is distributed to the same channel to which it is assigned. In this case, the operation of distributing the tone high voltage KV to each channel operates in synchronization with the key depression state memory 204 described above, and the selected channels also match.
Next, the channel-by-channel pitch voltage control section 500 includes pitch voltage control circuits 501a to 501h that are independently provided for each channel. The pitch voltage control circuits 501a to 501h input the pitch voltage KV supplied from the digital-to-analog conversion circuit 403 for each channel, and are gated by a key-on signal supplied from the key press state memory 204. By opening the circuit, the tone pitch voltage KV is stored in a capacitor, and the terminal voltage of this capacitor is sent to a musical tone forming section 600, which will be described later. Further, each of the tone pitch voltage control circuits 501a to 501h is connected to a tone pitch voltage control section 700, which will be described later.
The charging time constant of the pitch voltage K to the capacitor is controlled by a control signal supplied from the capacitor, thereby controlling the rise (fall) of the pitch voltage KV'0) outputted from the capacitor. By changing it, you get a gritsand effect or a portamento effect. Next, the tone forming section 600 includes tone forming circuits 601a to 601 provided for each channel.
It has 1h.

In this embodiment, the tone forming circuits 601a to 601h include a voltage controlled variable frequency oscillator (hereinafter referred to as VCO), a voltage controlled variable filter (hereinafter referred to as VCF), and a voltage controlled variable gain amplifier (hereinafter referred to as VCA). ) and an envelope generator (EG) that programs the control timing and control amount of each section (VCO, CF, VCA). It is configured using a so-called synthesizer method, and includes sound pitch voltage control circuits 501a to 501a.
When the pitch voltage KV' is supplied from the input pitch voltage KV', the VCO oscillates at a frequency corresponding to the input pitch voltage KV'.
This oscillation output is sent out as a musical tone signal via the VCF and VCA, and the mixing resistors 610a to 610h
After being mixed with musical tone signals sent out from musical tone forming circuits in charge of other channels, the signal is supplied to a speaker (not shown) via an output terminal 611.

In this case, by controlling the VCO, VCF, and VCA with a control waveform signal generated from an envelope generator (EG), the VCO
In the VCF, the oscillation frequency changes minutely, and in the VCF, the frequency characteristics change to form a musical tone signal rich in naturalness and musicality.Furthermore, in the VCA, the musical tone envelope is controlled according to the controlled waveform. This envelope generator (E
G) is under the control of an adjustment lever provided on the operation panel (not shown) of the electronic musical instrument, and the control start timing is determined by a key-on signal supplied from the key press state memory 204. There is. Sound pitch voltage control section 7
00 is when the capacitors provided in each of the tone pitch voltage control circuits 501a to 501h are charged by supplying a control signal to each of the tone pitch voltage control circuits 501a to 501h of the channel-by-channel tone high voltage control section 500. By changing the constants, switching between glissando and portamento and controlling the change in pitch voltage during sustain are performed. The timing signal generator 800 counts a reference clock signal (system clock) supplied from a reference oscillator (not shown), generates various synchronization signals, and supplies these synchronization signals to each of the above-mentioned parts to improve overall operation. synchronization has been obtained.

The pitch change mode control section 900 is a part that controls the pitch change mode of the voltamento performance sound effect or the glitsando performance sound effect by controlling the calculation timing of the calculation circuit 303 during portamento performance or glitsando performance sound. , integral characteristic change, linear change, and exponential pitch change modes can be obtained. The above description is an explanation of the main part structure and its operation with respect to the overall structure schematic diagram (FIG. 5) showing one embodiment of the electronic musical instrument according to the present invention.

The configuration and operation of each block shown in FIG. 5 will be explained in detail below using a drawing showing a concrete circuit and an operation waveform diagram of the main part. Before entering into the description of the concrete circuit, the special use of symbols in the circuit will be explained.

Figures 6a to 6f show examples of symbols used, in which Figure 6a represents an inverter, B and c represent an AND gate, D and e represent an OR gate, and f represents a delay flip-flop. It represents. In this case, in the above AND gate or OR gate, when the number of inputs is small, the normal display method as shown in B and d of the same figure is adopted, and when the number of inputs is large, the special display method shown in C and e of the same figure is adopted. Adopt a projection method. In Figures C and E, one input line is drawn on the input side of the circuit, multiple signal lines are crossed with this input line, and the signal line of the signal to be input to the circuit and the input line are crossed. The points are circled. Therefore, in the case of the example shown in figure c, the logical formula is Q=A-B-D, and in the case of the example shown in figure e, the logical formula is Q=A+B-1-C. FIG. 7 is a specific circuit diagram showing a main part of the timing signal generating section 800 shown in FIG. 5, which is a part that generates a control signal that is a reference for the operation of the electronic musical instrument shown in FIG.

Therefore, this timing signal generating section 800 will be explained first. This timing signal generating section 800 includes a 4-bit counter 801 composed of four flip-flops connected in cascade, and stages corresponding to the number of channels (in this embodiment, the circuit will be described below as having an 8-channel configuration). ) and a shift register 802. The counter 801 outputs pulses φ1 and φ2 which are obtained by dividing the output pulse φ of a reference oscillator (not shown) by two.
Among them, the clock pulse φ1 shown in FIG. 8a is input and counted. The pulse interval of this clock pulse φ1 is, for example, an extremely high-speed pulse of 1 μs, and this pulse interval will hereinafter be referred to as "channel time". If the number of simultaneous sounds in this electronic musical instrument is 8, the total number of channels is 8, and the clock pulse φ
The 1 μs wide time slots successively separated by 1 are driven corresponding to the first to eighth channels in sequence. This is the channel processor 200 mentioned above.
This is because, in order to be able to produce a plurality of musical tones simultaneously, various memory circuits and logic circuits are shared in a time-division manner, and are configured in a dynamic logic manner. Furthermore, the above-mentioned channel times are generated by cycling every 8 channel times, assuming that each time slot is sequentially defined as the 1st channel time to the 8th channel time as shown in FIG. 8b. Become. In other words, counter 80
When a clock pulse φ1 is supplied from an oscillator (not shown) to the input terminal of the counter 8, the counter 8 sequentially counts the clock pulse φ1 and outputs the count result as a binary-decimal code having a parallel 4-bit configuration. Among these outputs, the output of the highest flip-flop is connected to the first flip-flop as shown in FIG. 8c via an inverter 803.
The pulses are taken out as pulses S1 to S8 which send output over the range from channel time to eighth channel time.
Further, from the flip-flop at the highest level, pulses S, -S, 6, which are inverted versions of the pulses S1 to S8, are taken out as they are as shown in FIG. 8d. Also,
The parallel 4-bit output signal outputted from the counter 801 is matched with the AND gate 804 to detect a full count state, and the output at this full count is taken out as a pulse Sl6 as shown in FIG. 8e, and By extracting this pulse Sl6 via an inverter 805, a pulse σ blue is obtained as shown in FIG. 8f. In other words, this pulse Sl6 is generated once every processing operation time (16 μs) in the channel processor 200, and each channel time requires two cycles of time. This is because the channel processor 200 compares the input key code KC with the stored key code KC, which has already been assigned, in the first 8 channels, and then performs the writing process in the following 8 channels. , and the pulses S, ~S8 and pulses S, ~S8 shown in FIGS. 8C and d described above.
S,6 separates the first 8 channel time and the second half 8 channel time. Also, the AND gate 806 selects the first of the parallel 4-bit outputs output from the counter 801.
By determining the coincidence of the third output in the AND gate 806, the pulses S8, S, 6 which generate the output at the eighth channel time as shown in FIG. 8g) are obtained.

Pulses S8, S sent out from this AND gate 806
l6 is the clock pulse φ, and this clock pulse φ1
The signal is supplied to an 8-stage shift register 802 which is shifted and driven by a two-phase clock pulse consisting of a clock pulse φ2 having an opposite phase to As shown in FIG. 8 j-Q, pulses BTl to BT8 are obtained by sequentially sampling the first to eighth channel times. Therefore, the outputs of each stage of the shift register 802 are taken out in parallel of timing signals corresponding to the first to eighth channel times. Furthermore, the first to seventh stage outputs of the shift register 802 are
The clock pulse φA shown in FIG. 8h is obtained by determining the coincidence between the output of the OR gate 807 and the most significant bit output of the counter 801 at the AND gate 808.
Further, the AND gate 809 obtains the clock pulse φB shown in FIG. 8 by determining the coincidence between the output of the OR gate 807 and the output of the inverter 803. The operations of each part are executed using such pulse signals and clock pulses as timing signals. Hereinafter, the operation of each part will be explained in detail for each block using the above-mentioned timing signals. Regarding the key coater 100, the patent application No. 50-99152, title of the invention "Key Coater" (Japanese Patent Publication No. 57-3948), which was previously filed by the applicant, and the title of the invention, Patent Application No. 50-100879. It is explained in detail in the specification of "Key switch detection processing device J (Japanese Patent Publication No. 57-3949) or Japanese Patent Application No. 5175065, title of the invention "Electronic musical instrument" (Japanese Patent Publication No. 57-57719). , the explanation thereof will be omitted here.

Channel Processor 200 The configuration and operation of channel processor 200 will be described in detail.

9 to 12 are circuit diagrams showing specific embodiments of the first key code memory 201, key on/off detection circuit 202, truncate circuit 203, and key press state memory 204 that constitute the channel processor 200. . 9th
The first key code memory 201 shown in the figure has a key code K
Shift register 205 for each bit KNl to KB3 of C
a to 205g, and this shift register 205
The number of stages a to 205g (the number of storage devices) corresponds to the number of musical tones that can be produced simultaneously, that is, the number of channels (in this embodiment, 8 channels as described above). The shift registers 205a to 205g receive the clock pulse φ1 shown in FIG.
The output signal outputted from the final stage is driven by a two-phase clock pulse consisting of a clock pulse φ2 having an opposite phase to that of the AND gate 206a.
206g and each of the OR gates 207a to 207g, the signals are fed back to each input side of each shift register 205a to 205g. Therefore, the shift registers 205a to 205g as a whole constitute an 8-stage JR circular shift register having a number of stages capable of storing key codes KC of parallel bit configuration for the number of channels. become. Moreover, on the input side of each of these shift registers 205a to 205g,
Key code K composed of bits KNl to KB3
C is supplied through each AND gate 208a-208g and each OR gate 207a-207g. Therefore, when a set signal is supplied to the line 209 from a key-on/off detection circuit 202, which will be described later, each AND gate 208a to 208g is opened and each bit signal KNl to KB3 of the key code KC is taken in, and each shift signal is input. All data is written and stored in the stage portions of registers 205a to 205g corresponding to channels to which key codes KC have not yet been assigned. Memorized key code K
Which channel C (KN1 to KB3) is assigned can be determined in half depending on the output timing of each of the shift registers 205a to 205g driven by the clock pulses φ, φ2. This is because the clock pulses φ, . . . , φ2 and the channels to which the time-division allocation process is performed are synchronized and correspond to each other. Therefore, the memory key code K assigned to each channel
C is sequentially and time-divisionally output to the output terminals 210a to 210g for each channel time shown in FIG. 8b, and
It is also fed back to the input side of each shift register 205a to 205g to continue holding the memory. In addition, or gate 20
The initial clear signal 1C is supplied to 7g, and the 11"5 signal is forcibly written at that timing.Next, the key-on/off detection circuit 202 shown in FIG. 10 is a key code comparison circuit. 211, each shift register 20 of the first key code memory 201
Memory key code KC output from 5a to 205g and key code KC currently supplied from key coater 100
are compared with. In this case, the key code comparison circuit 21
The memory key code KC corresponding to each channel supplied to the memory key code KC is supplied in circulation twice during one allocated time TP shown in FIG. 8d. In other words, each channel time from 1st to 8th goes through one cycle in the first half allocation period TPl (FIG. 8c), and the second half allocation period TP2 (FIG. 8c)
) for one more cycle. On the other hand, since the key code KC output from the sample hold circuit 106 of the key coater 100 is read out by the clock pulse φB shown in FIG. There is no change between. Therefore, in the circuit configured in this way, each shift register 205a to 205a to
By circulating the contents of 05g twice and outputting it,
In the first half assignment period TPl, a comparison operation is performed to determine whether the key code KC currently output from the key coater 100 is already stored (or not already assigned to a certain channel), and in the second half assignment period TP2, a comparison operation is performed to determine whether the key code KC currently output from the key coater 100 is already stored or not. Perform allocation actions based on the results.
Further, the match detection signal EQ outputted from the key code comparison circuit 211 is 11 if a match is obtained as a result of the comparison, and 1e01 if there is no match. In this comparison, whether the input key code KC matches the key code KC assigned to which channel is determined based on the channel time when the match detection signal EQ becomes 111. Here, the input key code KC is not assigned to any channel, and the first half assignment period T
Between Pl, the key code comparison circuits 211 to 11
Considering the case where the coincidence detection signal EQ of 01 is outputted continuously, the output signal of the AND gate 212 also becomes 15 due to the output of the coincidence detection signal EQ of 1f011.
0? It becomes V. The 10 VW output signal of AND gate 212 is stored in delay flip-flop 215 via OR gate 213 and AND gate 214. In this case, since one input terminal of the AND gate 214 is supplied with the pulse signal Sl6 shown in FIG. 110?W signal indicating that it is not allocated) is one allocation period T
It is held until the end of P. The output signal of this delay flip-flop 215 is 10W! is inverter 21
After being inverted at 6, it is supplied to AND gate 217. In this case, a shift register 218 is provided which has a number of storage stages corresponding to the number of channels (8 stages in this embodiment) and is driven in synchronization with each channel time by clock pulses φ, φ2. In this shift register 218, the allocation status of each channel is VlO for a blank channel and 111 for an allocated channel! 1 and shifted sequentially. Therefore, a blank channel is designated by determining the output of this shift register 218 and by the generation channel time of the 101 output. When the shift register 218 generates a 101 output indicating a blank channel, the 1
The 10'1 signal is supplied to AND gate 217 via inverter 219. In this case, the other three input terminals of the AND gate 217 are the 11"1 signal supplied via the inverter 216, the pulses S9 to S, 6 (FIG. 8d) indicating the second half allocation period TP2, and the key code KC. 11 from the or gate 220 that detects that the
A 1Vm signal is supplied to each. Therefore, in a state where the input key code KC has not been assigned to any channel yet, the AND gate 217 outputs every time the shift register 218 outputs the 1W011 signal at the channel time corresponding to the blank channel in the second half assignment period TP2. is 11! W, and this 11 WW signal is supplied to the line 209 of the first key code memory 201 as a set signal. When this set signal is supplied, the first key code memory 201 stores the input key code KC in the stage corresponding to the blank channel as described above. In this case, the shift register 218 is set to 101 for every blank channel at its corresponding channel time.
In order to output a signal, the same input key code KC is written in all stages corresponding to blank channels among the stages corresponding to each channel of the first key code memory 201. and gate 22
1 (FIG. 10) uses the gate input of the AND gate 217 and the truncate signal as gate inputs. As will be described later, this truncate signal is generated at the channel time corresponding to the oldest channel by determining the channel for which the key was released the earliest, especially during the second half allocation period T.
Only one occurrence occurs during the corresponding channel time of P3. Therefore, from the AND gate 221, the set signal sent from the AND gate 217 selects the channel corresponding to the channel whose key was released earliest among the channels corresponding to each stage in which the input key code KC was written. 1 "1 signal is output per hour.
The 1111 output signal of the AND gate 221 is written to the shift register 218 via the OR gate 222. In other words, that channel has already been assigned to the storage stage of the shift register 218 that corresponds to the earliest key-released channel specified by the transgate signal among the channels to which the set signal has been output from the AND gate 217. A 1111 signal is written indicating completion. That is, when a new input key code KC is supplied from the key coater 100 and this new input key code KC has not yet been assigned to any channel, a blank channel is designated by the output signal of the shift register 218. , AND gate 217 at a timing corresponding to the time of this designated blank channel.
A set signal is output from.

As a result, among the stages corresponding to each channel of the first key code memory 201, the shift register 218
A new input key code KC is written in common to the stages corresponding to all blank channels specified by . On the other hand, in the stage corresponding to a blank channel of the shift register 218, a 5V111 signal indicating that the channel has become an allocated channel is written only in the stage corresponding to the one channel whose key was released the earliest.

Next, a case will be described in which the input key code KC has already been stored in the first key code memory 201 and has been assigned to a certain channel.

If the input key code KC has already been assigned to a certain channel, the coincidence detection signal EQ of the key code comparison circuit 211 becomes 'Tll' during that channel time. This coincidence detection signal EQ=111j1 is supplied to the AND gate 212. At this time, the output signal of the OR gate 220 is 3T. Therefore, the coincidence detection signal EQ
but! 11'' and the output signal of the shift register 218 is 1.
111 (i.e. input key code KC
is the channel time of the channel that has already been assigned), the condition is satisfied and the AND gate 212
゜" signal is output. This ゛1" signal is output from OR gate 2.
13 and an AND gate 214 to a delay flip-flop 215, and is held until the end of one allocation period TP (FIG. 8) as in the case described above.

However, an inverter 216 is provided on the output side of the delay flip-flop 215, and when the match detection signal EQ=11111 is output from the key code comparison circuit 211, a 111 fW signal is obtained from the AND gate 217 and the AND gate 221. is not possible and the allocation operation is not performed. The above operation is the channel assignment operation of the input key code KC in the key-on/off detection circuit 202. Next, the key-on/off detection circuit 20
The second key release detection operation will be explained. In the channel allocation operation described above, the AND gate 221 outputs q? at the channel time corresponding to the channel to which allocation has been executed. 1 signal was output and a 111!1 signal indicating that the assignment of this channel was completed was written to the stage corresponding to that channel of the shift register 218. Therefore, this shift register 218 This means that the channel allocation state is stored, and the information stored in the shift register 218 is sequentially shifted by clock pulses φ1 and φ2 corresponding to the channel time.
The keys are sequentially output from the final stage and supplied to the key press state memory 204, which will be explained next, and are also added to the input side via an AND gate 223 and an OR gate 222, so that they are sequentially circulated and stored. . On the other hand, the signal indicating the assigned channel output from the AND gate 221 is sent to the shift register 2 via the OR gate 224.
8-stage shift register 225 with the same configuration as 18
are sequentially written and stored.

Therefore, at this point, the shift register 22
The contents of 5 are the same as the contents of shift register 218,
Further, they are sequentially shifted by the same clock pulses φ1 and φ2. The signal output from the final stage of this shift register 225 is returned to its input side via an AND gate 226 and held there. Next, in the fourth state (standby state), which is set every time the sample and hold circuit 106 of the key coater 100 shown in FIG. A start signal X sent out at the timing of clock pulse φB is supplied to AND gate 226 via inverter 227.
AND gate 226 is inhibited, thereby resetting the entire contents of shift register 225.

After this reset operation is completed, the shift register 225
is the output signal of AND gate 221 and AND gate 2
The output signal of AND gate 212 is written through 28. By performing such an operation, a 7-11W signal is written in the shift register 225 to the stage corresponding to the channel to which the key switch being operated after the fourth state (wait state) is assigned. ,
Self-holding until the next start signal X is generated. On the other hand, since the shift register 218 does not perform any resetting operation, it continues to store the Flltf signal in the corresponding stage even for channels whose keys are subsequently released.

In this case, when the fourth state is entered again and the start signal X is supplied, the output signal of the shift register 225 is no longer fed back to the input side, but is supplied to the NAND gate 230 via the inverter 229. This NAND gate 230 receives pulse signals S1 to S8 shown in FIG. 8c.
, a start signal X, an inverted output signal of the shift register 225, and an output signal of the shift register 218 are supplied. Therefore, the outputs of the shift lens 218 and the shift register 225 are compared only in the fourth state and during the period of the pulse signals S1 to S8 (first half assignment period TP1). And shift register 21
When the output of 8 is 1'' and the output of shift register 225 is 0'', that is, after the latest 4th state, the same key code KC as the key code KC assigned to that channel is supplied. If the key has not been pressed (that is, the key has been released), the inverter 2
Since the output of 29 becomes ゞ1'', NAND gate 230
The output becomes ol to detect the channel in the key release state. Therefore, by determining the channel time of the o'' signal output from this NAND gate 230, it can be determined which channel the key was released on.
23, shift register 218
The ``1'' output signal is no longer returned to the input side, and the ``1'' signal of the stage corresponding to the channel that has already been released is forcibly rewritten to the ``o'' signal. In other words, the shift The ``1'' signal in register 218 indicating the allocated status is changed to ``0°C'' indicating the blank channel status. Incidentally, 231 is an inverter which does not indicate that the key release channel has been detected and which is output from the NAND gate 230 and supplies a 1'' signal, which is an inverted version of the left/right signal, to the truncate circuit 203, which will be described next.

Next, the truncate circuit 203 will be explained. 11th
The figure shows a specific embodiment of the truncate circuit 203. When a key released channel is detected by the NAND gate 230 of the key-on/off detection circuit 202 described above, this key release channel detection signal is transmitted to the inverter 2.
At 31, it is inverted to 11 signal and the OR gate 23
4 and stored in delay flip-flop 235.
The output signal of delay flip-flop 235 is returned to the input side via AND gate 236 and OR gate 234 and held there. In this case, since the other input of the AND gate 236 is supplied with the pulse signal shown in FIG. be done. In this state, the key-on/off detection circuit 20
When the output from shift register 218 of No. 2 is sent out, No. 1Ig is supplied from inverter 237 at the channel time corresponding to the blank channel to which no allocation has been made.
6) from the AND gate 238 to the shift register 2
A pulse signal 1'' is sent out in response to the 18 o'' output. As will be explained later, Nand Gate 239
The output of the AND gate 238 is in this case 1''. The output signal of this AND gate 238 is supplied to the input terminal CI of the adder 240, thereby adding the 3-bit augend signal supplied to the input terminals A1 to A3. ``1'' is added to , and the result of this addition is output from output terminals S1 to S3 as a 3-bit signal. In this case, the output terminals S1 to S3 of the adder 240
are connected to AND gates 241a to 241c, each of which uses the output of the inverter 237 as one of its input signals. AND gates 241a to 241c are opened only during the corresponding channel time, and the 3-bit addition result signal is sent to OR gate 242 and AND gates 243 and 244.
are supplied to the input ends of shift registers 245a to 245c, respectively. Note that the AND gates 243 and 244 are opened by the 11 signal supplied via the inverter 246 (in this case, the initial clear signal IC is not generated). The shift registers 245a to 245c are constituted by shift registers having storage stages corresponding to the number of channels (8 stages in this embodiment), and their input signals are clock pulses φ1, φ synchronized with the channel time.
2, and the output signal is sent out from the final stage. The output signals of the shift registers 245a to 245c are respectively supplied to the input terminals A1 to A3 of the adder 240 for signals to be added. Therefore, these parts are connected to each shift register 245a to 245a every time the key-on/off detection circuit 202 detects the above-mentioned key release.
Of the stages 245c, a key release channel progress memory circuit 247 is configured to sequentially add 1 to the current count value in the stage corresponding to the blank channel of the shift register 218. Since this key release channel progress storage circuit 247 uses shift registers 245a to 245c having an 8-stage configuration in a 3-stage parallel configuration, the key release progress signal of parallel 3 bits given to each channel is stored in the channel time. The key release progress signal having the largest value is output as a 3-bit signal (binary code) at the channel time corresponding to the channel for which the key was released the earliest. In this case, the key release channel progress memory circuit 24
7 has a 3-bit configuration as mentioned above, so its maximum output value is 7 (゜111''), and when you add 1 to it, it becomes 0 (゜000''), which is the oldest value. There is an inconvenience that the key release channel becomes the most recently released key. For this purpose, each shift register 245a
A NAND gate 239 is provided on the output side of ~245c to find a match between the 3-bit signals, and by inhibiting the AND gate 238 with the output signal of this NAND gate 239, further addition is stopped in that channel. This eliminates the above-mentioned disadvantages. By performing the above-described operation, the circuit to be described later can sequentially allocate channels starting from the oldest key-released channel. This is because sustain is added after a key is released, so if many keys have been operated, it is necessary to determine the oldest key release channel and assign a new key code. The 3-bit key release progress signal outputted from the key release channel progress storage circuit 247 corresponding to each channel time is processed by AND gates 248a to 248c and OR gate 24 for each bit.
Delay flip-flop 250a via 9a-249c
~250c and stored.
In this case, each delay flip-flop 250a-250c
Since the 3-bit signal stored in the 3-bit signal is read in with the clock pulse φ1 and read out with the clock pulse φ2, it is delayed by one clock pulse and is output. ~
251c and each OR gate 249a to 249c, it is returned to the input side and stored therein. Therefore, delay flip-flops 250a-25
0c constitutes a memory circuit that stores a 3-bit signal. Delay flip-flops 250a-250
The output signal of c is supplied to a comparator 252 as a 3-bit key release progress signal B. The comparator 252 is configured to compare the key release progress signal B with the new key release progress signal A supplied from the ring key channel progress storage circuit 247, and generate the 11 output only when A>B. has been done. Since the 1'' signal outputted from the comparator 252 is supplied to each AND gate 251a to 251c as an o'' signal via a NOR gate 253, the output of each delay flip-flop 250a to 250c returns to the input side. to prevent Furthermore, since the 1'' signal output from the comparator 252 is supplied to the AND gate 254,
When the AND gate 254 outputs the output from the comparator 252 in the first half allocation period TPl, an AND condition is satisfied, and the output causes each bit signal of the new key release progress signal A from the storage circuit 247 to be output to the AND gate 254.
Delay flip-flop 250a through 8a-248c
~250c. Therefore, these constitute a maximum key release progress signal extraction circuit 255 that extracts the maximum key release progress signal from the key release progress signals of each channel, and at the end of the first half allocation period TPl, the maximum key release progress signal is extracted. is stored in delay flip-flops 250a-250c and reset at the end of one allocation period TP by pulse signal Sl6 (FIG. 8e). Also, the AND gate 254 generated in the first half allocation period TPl
The output signal is supplied to each AND gate 256a to 256c. At this timing, a signal coded for each 3-bit channel output from the counter 801 of the timing signal generator 800 shown in FIG. 7, that is, a channel code. Signals HCl to HC3 (channel time in binary code) are sent to each OR gate 257.
a to 257c, each delay flip-flop 258
a to 258c, respectively. The contents of the delay flip-flops 258a to 258c are similar to the case of the maximum key release progress signal extraction circuit 255, in which the output signal of the NOR gate 253 is converted to the AND gates 259a to 259c.
Therefore, the channel code signals HCl to HC3 representing the channels in which the maximum key release progress signal occurs within the first half allocation period TPl are stored. The channel code signals HCl-HC3 representing the channel in which the maximum key release elapsed signal occurred, stored in each of the delay flip-flops 258a-258c, are held until the end of one allocation period TP (FIG. 8). noah gate 2
Pulse signal Sl6 supplied via 53 (Fig. 8e)
It is reset by The channel code signals HCl-HC3 stored in the delay flip-flops 258a-258c are supplied to a comparator 260 to determine whether they match the input channel code signals HCl-HC3. When both signals match, the key-on/off detection circuit 20 outputs the matching signal Sll at that timing.
It is supplied to the AND gate 221 of No. 2 as a truncate signal. In this case, the channel control signal HC~HC
Since s circulates twice during one allocation period TP (Figure 8), the first circulation period (first half allocation period TPl)
) in each delay flip-flop 258a-258c.
Therefore, the coincidence output signal from the comparator 260 is outputted only once in a certain channel time in the second half allocation period TP2. Therefore, these circuits are the earliest key release channel extraction circuit 2.
61, and in the second half of the allocation period TP2, a pulse signal as a truncate signal is outputted at the channel time corresponding to the oldest key release channel (the channel in which truncation is the most advanced). The channel to which a new key code KC is to be assigned is reliably specified to the key-on/off detection circuit 202 only once.In the key-release channel progress storage circuit 247, the initial clear signal 1C is sent via the OR gate 242. The purpose of writing only to the shift register 245a is to first write the 11 signal to all stages of the shift register 245a to ensure the truncate operation in the initial state.In other words, the shift of the key-on/off detection circuit 202 register 218,2
25 is reset in an initial state when the power is turned on by an initial clear signal 1C (not shown). Along with this, the output signal of the NAND gate 230 is also initially always N'
1! ! Therefore, the output signal of the delay flip-flop 235 also becomes 'o', and the AND condition of the AND gate 238 is no longer satisfied.
5a to 245c are also all reset, the comparator 25 in the maximum key release elapsed signal extraction circuit 255
2, it becomes impossible to obtain the 1'' signal that is output when A>B.

As a result, the channel code signals HCl-HC3 are no longer stored in the delay flip-flops 258a-258c of the oldest key release channel extraction circuit 261, and the channel code signals HCl-HC3 are no longer stored in the delay flip-flops 258a-258c. Continue in the set state. As a result, the condition A=B cannot be obtained in the comparator 260, a truncate signal is not generated, and the first generated key code KC cannot be assigned. In order to solve this problem, the initial clear signal 1C is used to forcibly write the number 1C into all stages of the shift register 245a. Therefore, 1IP. by this initial signal 1C. The writing of the number is not necessarily limited to the shift register 245a;
It is sufficient that the shift register 245a to 245c is purchased so that the temperature of 1°C is forcibly written into at least one of the shift registers 245a to 245c.

The above description is the operation of the truncation circuit 203 that specifies only one channel that has been truncated the most. Next, the key press state memory 204 will be explained in detail.

FIG. 12 shows a specific embodiment of the key press state memory 204, in which output signals from the shift register 218 of the key-on/off detection circuit 202 described above are sequentially supplied to each AND gate 262a to 262h. ing.

In this shift register 218, as described above, the ``1'' signal is written in the stage corresponding to the channel to which the key code KC is assigned, and the ``1'' signal is written in the stage corresponding to the channel to which the key is released (blank channel). The stage has been rewritten as ゞo''. Therefore,
The signals sent from the shift register 218 in a time-division manner corresponding to each channel time represent the current key depression state of the key assigned to each channel. When such a state is stored and the output signal of the shift register 218 sent out while being sequentially shifted by clock pulses φ1 and φ2 is supplied to the key press state memory 204, the output signal ♂12 state, that is, the assigned key During the channel time when the key corresponding to code KC is pressed, the timing signal generator 800 shown in FIG. The AND gates 262a to 262h of the portions where the timings of the channel signals BTl to ST8, which are sequentially outputted in a time-division manner, coincide with each other.
The condition is satisfied, and the ♂ 1″ output is the OR gate 263a.
~263h through delay flip-flops 264a~2
64h, and its output is stored in AND gates 265a~
It is held by being returned to the input side via 265h and OR gates 263a to 263h. Therefore, the delay flip-flops 264a to 264a to 264a, which are in charge of the first to eighth channels, are controlled by the Fl2 signal indicating the key depression channel supplied from the shift register 218 (FIG. 10).
The 1'' signal is stored only in the portion in charge of the corresponding channel of 64h, and the next corresponding channel signals BTl to BT8 generated in a time-division manner are sent to the inverters 266a to 26.
It will continue to be held until the AND gates 265a to 265h are inhibited via 6h. For example, when the shift register 218 (FIG. 10) outputs the 1'' signal during the third channel time shown in FIG.
The channel signal generated during this third channel time is only the channel signal BT3, as shown in FIG. 8. As a result, the condition is satisfied only in AND gate 262c, and its output signal is written to delay flip-flop 264c via OR gate 263c. Therefore,
These circuit parts include a shift register 2 which indicates the key depression state of each channel by channel signals BTl to BT8.
The output signal of 18 (Fig. 10) is delayed by the flip-flop 2.
64a to 264h constitutes a serial/parallel conversion circuit 267 that converts signals representing the key press channels from the shift register 218, which are serially output in a time-division manner, into eight channels of parallel signals. Become. From this serial/parallel conversion circuit 261, among the output lines 268a to 268h corresponding to each channel, a key code KC is assigned and a key corresponding to the key code KC is pressed. Only the 1'' signal is output. For example, as mentioned above, in the third channel,
If the key is pressed, a signal of 11 is applied to line 268c. In this way, the 1'' signal output corresponding to the key depression channel is transmitted to each of the NOR gates 269a to 269a.
Field effect transistors 270a to 27 through 69h
No. 1 is supplied to the gate electrode of 0h, turns off this charge effect transistor, and sends out No. 1 to output terminals 271a to 271h provided corresponding to the first to eighth channels. For example, as described above, if only the third channel is pressed, the delay flip-flop 264c sends a signal to the NOR gate 269c &
1C was supplied, and this Noah Gate 269c (7)
Only the transistor 270c is turned off by the o'' output signal. As a result, only the output terminal 271c becomes 1'', and the other output terminals 271a, 271b, 271d to 2
71h becomes ゞO''. Therefore, among these output terminals 271a to 271h, it shows that the key is pressed in the channel corresponding to the part where No. 1 is sent. No. 1C, that is, key-on signal KO, controls corresponding pitch voltage control circuits 501a to 501h of a channel-specific pitch voltage control section 500, which will be described later.Key Code Conversion Section 300 Next, the key code conversion section 300 will be explained in detail. .

FIG. 13 shows a specific embodiment of the key code conversion unit 300 shown in FIG.
and a comparison circuit 304.

The key code shift control terminal 301 is a terminal that supplies a pitch variable control signal for controlling the presence or absence of pitch variable control (glitsando effect or portamento effect), and when obtaining a normal performance musical tone, the key code shift control terminal 301 is A signal is supplied, and when variable pitch control is performed, an o'' signal is supplied. First, normal operation will be explained. Note that this key code conversion unit 300 performs the key code conversion process for each channel in a time-sharing manner at the corresponding channel time, but in order to make the explanation easier to understand, the operation for one channel will be explained below as a representative. do. Key code shift control terminal 3
When the 01t1'' signal is supplied, the 11 signal is converted to each bit signal KN1 to KB3 of the key code KC from the first key code memory 201 supplied via the input terminals 307a to 307g of the key code conversion section 300. AND gate 30 provided in the arithmetic circuit 303 to gate
The respective bit signals KNl-KB3 supplied to one input terminal of the AND gates 308a-308g
08g and OR gates 309a-309g to 7-bit input terminals A1-A7 of adder 310, respectively. The 1/' signal supplied to the key code shift control terminal 301 is output to the inverter 311.
Then, the final stage output signals of the shift registers 313a to 313g connected to the 7-bit addition output terminals S1 to S7 of the adder 310 are input to the adder 310.
are returned to the input terminals B1 to B7 of the input terminals B1 to B7 to prevent them from being added. In this case, the shift registers 313a to 313g are equal to the number of channels (8 channels in this embodiment).
The number of storage stages is provided for each bit KNl to KB3 of the key code KC, and is sequentially shifted by clock pulses φ1 and φ2. Therefore, these shift registers 313a to 313g are the same as shift registers 205a to 205 of the first key code memory 201 described above.
As in the case of g (FIG. 9), this constitutes a memory in which key codes KC having a 7-bit structure are stored as many times as the number of channels and are sequentially shifted. The adder 310 combines signals supplied to each input terminal A1 to A7 and input terminals B1 to B1 to
The adder 310
When the input signals supplied to the input terminals B1 to B7 of the inverter 311 are all inhibited, the output terminals S1 to S7 of the adder 310 have a key code of KC plus "O", that is, Input key code KC
is output as is. The parallel 7-bit key code KC output from the output terminals S1 to S7 of the adder 310 has respective bit signals KNl to KB3 stored in the respective shift registers 313a to 313g. Therefore, these seven stage shift registers 313a to 313g have eight stages.
Key codes KC for the channels are stored, shifted by clock pulses φ1 and φ2, and sequentially output from the final stage as parallel 7-bit signals. A key code K consisting of these parallel 7-bit output signals KNl' to KB3'
C' is a key code/tone pitch voltage converter 40 which will be explained next.
0, the tone high voltage KV corresponding to the key code KC'
and is supplied to the channel-by-channel sound high voltage control section 500. Therefore, the key code shift control terminal 301
During normal operation when the 1″ signal is supplied,
The 7-bit key codes KC sequentially supplied from the first key code memory 201 are sequentially output as they are, and thereby a normal performance musical tone is obtained.
Next, connect the key code shift control terminal 301 to ``&'O'@
A case will be described in which the key code KC is supplied and the key code KC is converted. In this case, each of the AND gates 308a to 308g on the input side of the adder 310 is inhibited by the o(sign) supplied to the terminal 301, and the above-mentioned first key to be supplied to the adder 301 is The key code KC from the code memory 201 is all blocked. On the other hand, since the key code shift control terminal 3 old bit o'' signal is supplied, the output power of the inverter 311 is
1:. Along with this, each AND gate 312a~
312g is opened and each shift register 313a to 313
The output signal of g is supplied to input terminals B1 to B7 of adder 310. In this case, the input terminals A1 to A of the adder 310
7 from the first key code memory 201 is blocked by the AND gates 308a to 308g. shift register 313
The output signals of a to 313g are output as they are and returned to each shift register 313a to 313g,
This allows the stored contents of each shift register 313a to 313g to continue to be held. Each shift register 31
Key code KCI (KN) output from 3a to 313g
l' to KB3') are supplied to the comparator circuit 304, and the first
Key code KC output from key code memory 201
(KNl~KB3). The ratio soft circuit 304 is
If A (A1 to A7) is a larger value than B (B1 to B7) (A>B), a ゞ1'' signal is output to the terminal 314, and in the opposite case, an o'' signal is output to the terminal 314. Output. In addition, when the two match (A=B), the output of the friend NAND gate 315 becomes O''.In this case, the comparator circuit 304 uses the subtraction theory (2''
A comparison circuit is constructed by SCOmplement). In other words, input terminal A of adder 316! Each bit signal KNl to KB3 of the key code KC supplied from the first key code memory 201 is supplied to ~A7, and the output of the second key code memory 302 is supplied to the other input terminals B and ~B7. The signal is connected to each inverter 317a to 317
It is supplied via g. Further, the addition output terminals S1 to S7 of this adder 316 are connected to the NAND gate 31 described above.
5 requires complete agreement. Furthermore, when the addition result of A1 to A7 (A) and B1 to B7 (B) exceeds the value expressed by the number of output bits (7 bits in this embodiment), this adder 316 outputs the signal from the carrier out terminal CO.
It is configured to output a carry signal N (1) from 1 to 1. This comparison operation is performed as follows.The key code K supplied to the input terminals A1 to A7 is
The value of C is α, and the value of the output key code K (V of the second key code memory 302 is β. In this state, the input terminals B1 to B7 are set to the value immediately before the carry out N is output, that is, the input terminal Assuming that B1 to B7 are all 1'', the value is (N-1) minus the value of β inverted by the inverters 317a to 317g (N-1-β). Therefore, the adder 316 The input terminal A is connected to the carrier out CO and the output terminals S1 to S7, which output the addition result of
α is supplied to input terminals B1 to A7 and input terminals B1 to Bwa. (N-1-β) is the added touch value (α+N
-1-β) will be output. For example, if α>β, N=ゞ1'' is output from the carrier out CO. Also, if α≦β, the carrier out CO
The output becomes ゞ0Ib. Furthermore, if the two match (
N-1), and the output terminals S1 to S7 are all 1'I:
．． As a result, the output of NAND gate 315 becomes ゞo''
becomes. Further, a calculation control pulse 0PC synchronized with each channel time is supplied to the speed control terminal 305 from a pitch change mode control section 900, which will be described later.

In this state, a new key is operated and a new key code KC is assigned (recorded) to a certain channel of the first key code memory 201, and the first key code KC is assigned (recorded) to a certain channel of the first key code memory 201, and the first key code KC is assigned to a certain channel of the first key code memory 201. When a new key code KC having a value α larger than the value of the output key code KC' of each of the shift registers 313a to 319g is supplied from the memory 201, the output key code KC from the carrier out terminal CO of the adder 316 is output as described above. When the word is output, this 12 signal is supplied to AND gates 325 and 326. In addition, a pitch change mode control section 900, which will be described later,
The calculation control pulse 0PC is supplied to the speed control terminal 305 from
As shown in Table 1, note code NC constituting C is based on note C◆ and uses a binary code in which one semitone is a unit. In other words, when expressed in decimal notation, note C+ is "o", note D is "1", and note D+ is "2".
”, Note E is [4], Note F is [5], Note F+
[6J. Note G is assigned as a binary code "8", note G+ as "9", note A as "101", note A+ as "12", note B as "13", and note C as "14". In other words, the note code NC is not set so that the difference between the note codes of each note name directly corresponds to the pitch between each note name. This is because the note code NC is composed of 4-bit signals KNl to KN4,
ゞ0000! JllllI2 can have 16 different values, but since the number of notes in one octave is 12, as is clear from Table 1 above, here the bits KNl and KN2 are both The four codes that are ゞbiゞ0011″,ゞ0111″,ゞ1011″,ゞ11
11" is not used, and the remaining 12 chords are assigned to the 12 tones from c+ to c. As a result, if a semitone is one unit, the note difference is "1" and "2". will exist. As is clear from Table 1, the block code BC has a continuous chord structure in units of one octave. Therefore, when changing the key code KC by semitones, the substitute key code KC should be changed to "
The part that adds and subtracts ``1'' (decimal display) and the part that adds and subtracts ``2'' (10
There is a part that adds and subtracts (in decimal notation).

Specifically, when the key code KC is raised 2 at semitone intervals, when the note code NC of the current key code KC represents any of the note names CD, E, F, G, GA+, B. "1" θ addition 5 is performed, D fathom, F
When expressing the note name +, A, or C, add "2" to create a key code KC of a note a semitone higher. In this case, C+, D, E, F, G, G+, A+, B
The lower 2 bits of the note code NC of each note KN2, KN
! is '00''3 or ''01MC', so when this is detected, it is sufficient to add "1", and at other times, it is sufficient to add "2".
Similarly, if we consider the case where the zζ key code KC is sequentially lowered ♂ 7 at semitone intervals, the current note code NC is D, D.
+, F, F4P, GΦ, A, B, C When expressing the note name, subtract "1" and use CΦ, E, G, A.
◆When expressing any of the note names, subtract "2" to create the key code KC, which is a semitone lower.In this case, D, DF, F circle G≠, A, B, The lower two bits KN2 and KNl of the note code NC for each note of C are 0.
1" or 10", so when this is detected, it is sufficient to subtract "1", and at other times, it is sufficient to subtract "2".

In this way, in order to create a key code KC that ascends (descends ◆◆) sequentially at semitone intervals, the lower two bits KN2KNl of the current note code NC are determined and the current key code KC
All you have to do is add (subtract) ``1'' or add (subtract) ``2'' to .

Therefore, even though the key code converter 300 in FIG. 13 is provided with an inverter 330 and OR gates 331 and 332 to determine the lower two bits KN2 and KNl of the note code NC, the output KNl' of the shift register 313a is and an OR gate 331 which inputs the output KN2' of the shift register 313b via the inverter 330.
This indicates that if the output power of
OR gate 33 whose inputs are the outputs KNl' and KN2'
This means that when the output of 2 becomes 1'', it is sufficient to subtract 1. In addition, if the outputs of the OR gates 331 and 332 are both O′t)),
This indicates that it is sufficient to add or subtract "2". The output signal of this OR gate 331 is the key code KC
AND gates 325 and 326 when increasing sequentially
The output signal of OR gate 332 is used by AND gates 327 and 328 when sequentially lowering key code KC. Here, the case of the rising mode in which the key code KC is raised sequentially will be explained using a specific example.

For example, bit signals KNl' to KN4' output from shift registers 313a to 313d represent node D'.
If it is 1000'', a 12 signal is output from the OR gate 331. This OR gate 331-1'' signal is supplied to an AND gate 326 and also to an AND gate 325 via an inverter 333. As a result, only the AND gate 326 satisfies the condition and sends out the ``1'' output, but the ``Pi output'' of this AND gate 326 is
It is supplied only to the A1 terminal of adder 310 via OR gate 309a. As a result, "1" is added to the key code KC' supplied to the input terminals B1 to B7, and the addition result is supplied to the input side of each shift register 313a to 313g via the output terminals S1 to S7. be remembered by In addition, shift registers 313a to 313
If the note codes KNl' to KN4' output from d are, for example, SOlOOI representing the note DΦ, then (
The output of friend or gate 331 is 'o'', and this 0C
The condition of only the AND gate 325 is satisfied by the ゞ1'' signal which is inverted by the inverter 333.The output signal ゞ1'' of the AND gate 325 is supplied only to the input terminal A2 of the adder 310 via the OR gate 309b. and the output key code KC of shift registers 313a to 313g
The key code KC' obtained by adding "2" to the key code KC' is supplied to the input sides of the shift registers 313a to 313g and stored. Therefore, if the output key code KC' of the second key code memory 302 for a certain channel is smaller than the value of the input key code KC, "1" is set corresponding to the note codes KNl' to KN4'. Alternatively, "2" is sequentially added and recorded in the second key code memory 302 again. In this operation, each time the calculation pulse 0PC is supplied to each channel in a time-division manner, one addition process is performed on the key code KC' of that channel. Become. Then, the key code K to which "1" or "2" is added in this way
If C' is not read in the next cycle, the key code K
C' is output as a chord representing a node one step higher (a semitone higher). After this, the next new calculation control pulse 0PC
When the key code KC' is supplied, "1" or "2" is added to the current key code KC' by the same operation as described above, and the key code KC' representing a note one level higher is obtained. In this way, each time the arithmetic control pulse 0PC is supplied, the key code KC' increases stepwise to the value α of the input key code KC.
When the value β of the key code KC' output from the second key code memory 302 matches, the adder 3
The output signal of the 16 carrier out CO becomes 0'', and accordingly, the AND gates 325 and 326 for controlling the addition of ``1'' or ``2'' are inhibited, and the arithmetic processing ends. Note that the cycle of the above-mentioned addition operation is based on the calculation control pulse 0PC, which is supplied to each channel in a time-division manner.
The key code K is determined by the period of the calculation control pulse 0PC.
The stepwise rising speed and rising mode of C′ are controlled;
As a result, the speed of pitch change and the mode of change in the portamento or grissando tones described later can be changed.

Next, a value α smaller than the value of the output key code KC' of the second key code memory 302 at a certain channel time is determined.
When a new input key code KC having a value of
From the carrier out terminal CO of the inverter 335, the signal power of
1" output signal is supplied only to AND gates 327 and 328. In this state, OR gate 332 outputs "1" output signal.
When the ``1'' signal instructing subtraction is output, only the AND gate 328 satisfies the condition, and its output is sent to the adder 3.
10 input terminals A1 to A7. In this case, supplying the 1″ signal to all input terminals A1 to A7 means
As mentioned above, (N-1) is added, and the addition result is N-1+β, and the output terminals S1 to S7 have N, which corresponds to the carrier out, removed (β-1).
is output, and the result of subtracting "1" from the key code KC' is obtained. On the other hand, the output of the OR gate 332 is O''
In this case, only the condition of the AND gate 327 is satisfied by the 1'' output signal of the inverter 334, and 1C is output.This AND gate 327d1
'' signal is supplied to the input terminals A2 to A7 of the adder 310. That is, by removing the input terminal A1, the (N-2
) has been added. As a result, the added value is N
-2+β, and (β-2) from which the value N corresponding to carryout is removed is output to the output terminals S1 to S7, and the result of subtracting "2" from the key code KC' is obtained.
By performing such arithmetic processing every time the arithmetic control pulse 0PC is supplied, the second key code memory 3
The key code KC' corresponding to the channel stored in 02 decreases step by step. When the value β of the output key code KC' of the second key code memory 302 and the value α of the new input key code KC match, the adder 31
All the signals at the output terminals S1 to S7 of 6 become ゞ1'', and the output signal of the NAND gate 315 becomes ゞo''. As a result, the conditions of AND gates 327 and 328 are not satisfied, and the subtraction processing operation is stopped. By the way, the first key code in the channel processor 200. In the memory 201, as described above, new input key codes KC are stored for all stages corresponding to blank channels.

Therefore, among the key codes KC' recorded in the second key code memory 302 in the key code conversion section 300,
The key code KC' corresponding to the blank channel is changed for each channel by the above-described arithmetic operation until it matches the target value using the new input key code KC as the target value. In this case, the new input key code K
Only one tone generation channel based on C is specified by the output signal of the shift register 218 of the key-on-off detection circuit 202. Therefore, only for channels to which a new input key code KC is assigned, portamento changes automatically and at any speed from the pitch corresponding to the previously pressed key to the pitch corresponding to the newly pressed key. effect or gritsand effect. For example, after the key with the pitch name B is released and all channels become blank channels, the key with the pitch name D is pressed first, and the key code KC corresponding to this key becomes the first channel. Assignment Next, let's look at the case where in addition to the key with the note name D, the key with the note name F is pressed, and the key code KC corresponding to the key with the note name F is assigned to the second channel. Then, when the key for the note name B is released and all channels become blank channels, the stored contents of the stage of each channel in the second key code memory 302 all indicate the key code KC' for the note name B. There is.

Therefore, when the key with the pitch name of D is pressed and the key code KC of this key is assigned to the first channel, the key code KC for the pitch name of B stored in all stages of the second key code memory 302 is ' changes sequentially until it matches the key code KC corresponding to the note name of D. After this, F
When the key with the note name of is pressed, the key code KC of this key becomes the second key.
When assigned to a channel, the second key code memory 302 corresponds to the remaining channels except the first channel.
The key code KC' corresponding to the D note name stored in the stage of is the key code KC' corresponding to the latest F note name.
It will change sequentially until it matches. As a result, in the first channel, a portamento effect or a glissando effect is obtained in which the pitch of the note name of the previously pressed key, B, changes sequentially from the pitch of the note name of the newly pressed key, D.

In addition, in the second channel, a portamento effect or a glissando effect is obtained in which the pitch of the note name of the previously pressed key, D, changes sequentially from the pitch of the note name of the newly pressed key, F. By the way, in the channel processor 200, when a pressed key is released, the stored contents of the stage in the shift register 218 corresponding to the channel to which this key has been assigned are rewritten to number 0C, which indicates a blank channel state, and the key is released. However, if the key code of a new pressed key is assigned to the same channel during this decay, the key code KC' of the sound in the process of decay is stored in the second key code memory 302. remains, and as a result of the arithmetic operation described above, the pitch of the note in the process of decay changes toward the pitch corresponding to the newly pressed key until the decay is completed.

The above description is a detailed description of the key code conversion section 300. Key code/pitch voltage converter 400 Next, the key code/pitch voltage converter 400 will be explained in detail.

14 and 15 show a specific embodiment of the key code/pitch voltage converter 400, and this key code/pitch voltage converter 400 is constructed using the sampling control circuit 402 shown in FIG. , a sampling circuit 401 and a digital-to-analog conversion circuit 403 shown in FIG. In this case, in the key code/pitch voltage conversion section 400, the sampling control circuit 402 that generates the reference timing signal and control signal will be explained first. FIG. 14 shows a specific circuit diagram of the sampling control circuit 402.
The AND gate 404 receives the channel signal BT output from the timing signal generating section 800 shown in FIG.
8 and an initial clear signal 1C are supplied.
This initial clear signal 1C becomes S1'' only once immediately after the power is turned on, and the period of its pulse width C1'' corresponds to the times of the first to eighth channels. Therefore, the timing signal BT8 is output from the AND gate 404 only once immediately after the power is turned on. The output signal (timing signal BT8) of this AND gate 404 is passed through an OR gate 406 to an 8-stage shift register 4 driven by clock pulses φ1 and φ2.
05 and is sequentially shifted by clock pulses φ1 and φ2. Therefore, from each stage of this shift register 405, a signal C1'' signal which is sequentially delayed from the timing signal BT8 outputted from the AND gate 404 is outputted in synchronization with the first channel time to the eighth channel time. Then, when the one "12 signal" written in the first stage of this shift register 405 is shifted to the final stage, the output of the NOR gate 407a becomes "1" and "1" is written in the first stage again. Therefore, from now on, the shift register 405 will be used as the NOR gate 4.
The S11'' signal output from 07a is input and shifted sequentially.As a result, the shift register 4
05 operates in synchronization with the shift register 802 shown in FIG.
Channel signals BTl to BT8 (FIGS. 16b to 1) which are the same as the channel signals BTl to BT8 outputted from 2 are outputted. In this way, two shift registers 40 are required to obtain the same channel signals BTl to BT8.
The reason why synchronous driving is performed using 5,802 is that when a circuit is divided into multiple blocks and integrated, or when both are installed in a relatively distant part, it is not possible to use a single synchronous signal line. This is to easily obtain eight synchronized channel signals BTl to BT8 by using only one channel. The output signal of the AND gate 404 is also supplied via an OR gate 410 to the input side of a nine-stage shift register 411 driven by clock pulses .phi., .phi.2. Therefore, from the final stage of this shift register 411, a signal C1'' which is obtained by delaying the timing signal BT8 outputted from the AND gate 404 by nine channel times is outputted in synchronization with the first channel time. Since the first stage output to the eighth stage output of the shift register 411 are SO'', the NOR gate 407b which receives these as input outputs the '1'' signal, and this '1'' signal is sent to the shift register 411 via the OR gate 410. is written in the first stage of As a result, the shift register 411 sequentially shifts the ``1'' signal applied from the NOR gate 407b and outputs it from its final stage after the channel time.In other words, the shift register 411 initially outputs the ``1'' signal from the AND gate 404 only once. The timing signal BT8 is inputted and shifted sequentially, and then the 1'' signal repeatedly outputted from the NOR gate 407b is inputted and shifted sequentially. As a result, from the final stage of the shift register 411, every 9th count (9th
A 1" pulse signal SC is output for each channel time). In addition, the 16th pulse signal SC is output from the inverter 412.
An inverted signal SC of the pulse signal SC shown in FIG. k is taken out. Furthermore, the output signals of the first stage and the final stage of the shift register 411 are outputted via the NOR gate 413, as shown in FIG. The above is the explanation of the sampling control circuit 402, and since the various pulse signals outputted here are used in the sampling circuit 401, which will be explained next, that part will be explained in detail.

FIG. 15 shows a specific embodiment of the sampling circuit 401 and the digital/analog conversion circuit 403, and the output key code KC' of the second key code memory 302 shown in FIG. By the pulse signal SC (Fig. 16j) supplied from
Each bit signal KN' to KB3' is connected to each AND gate 414.
a-414g and OR gates 415a-415g to delay flip-flops 416a-416g for storage.

This stored information (memory key code) is then supplied to the inverter 417 with the next pulse signal SC, and the output of this inverter 417 is used to input each AND gate 418.
a~418g is held until inhibited. In this case, since the shift register 411 in FIG. 14 has a 9-stage configuration, which is one stage more than the number of channels, as described above, the pulse signal SC output from the shift register 411 is transmitted for one cycle of the channel time. The pulse signal is synchronized with a different channel time each time. Therefore, the pulse signal SC, which is the final stage output signal of this shift register 411, causes the second key code memory 3 to
By sampling the output key code KC' of 02, key codes KC' of different channel times can be sequentially sampled. That is, as shown in FIG. 16j, the pulse signal SCl is the first channel signal B.
The key code KC' corresponding to Tl can be sampled and stored in the delay flip-flops 416a to 416g, and the pulse signal SC generated in the next period can be
2, the key code KC' corresponding to the second channel time BT2 is sampled and the delay flip-flop 416
a to 416g. Therefore, the sampling in this part is to decelerate the output key code KC' of the second key code memory 302 to 1/8 and sample it sequentially for each channel, and this sampled key code KC'' continues to be stored until the next sampling. The reason for performing such deceleration sampling is that the digital-to-analog conversion circuit 403, which will be explained next, cannot follow high-speed operation, and the subsequent circuit system performs parallel processing divided by channel, so time-division processing is not performed. This is because it does not require the high speed performance of the key coater 100, channel processor 200, etc. that are currently used. Therefore, these parts are decelerated and the key code K for each channel is
This constitutes a sampling circuit 401 that sequentially takes in C'. Next, the key codes Kσ decelerated and sampled by the pulse signal SC of the sampling circuit 401 and stored in the delay flip-flops 416a to 416g are the no codes KNl'' to KN4'' and the block codes KB,'' to KB3. The parallel 1
It is converted into a 0-base signal and a '1' signal is output only to the output terminal corresponding to the code.

For example, the key code KC representing the B note of the 5th block.
When V' is supplied, '1011' is supplied to input terminals A-D of decoder 419, and 'SlO1' is supplied to input terminals A-C of decoder 420. Therefore, the decoder 4 converting the block code KBl'-KB3''
20, the 1'' signal is output only to the output terminal 5. Furthermore, the decoder 419 that converts the note codes KN1 to KN4'' outputs the S1'' signal only to the output terminal 13. As a result, , transistors 420a to 420 connected to the output terminals of each decoder 419, 420, respectively.
01 and 421a to 421f, only the transistor 420b and the transistor 421a connected to the terminal 13 and terminal 5 to which the output '1'' signal is output are turned on.As a result, the power supply + is connected to the voltage dividing resistor 〆 to 16r. The potential at point A of the first voltage dividing circuit 422 configured to divide the voltage at
It is supplied to point a of 23. On the other hand, when the transistor 420b is turned on by the output of the decoder 419 as described above, the potential at point b is taken out and output. In this case, the potential at point a is the block code KB,''~
Since it is the output of the first voltage dividing circuit 422 selected corresponding to KB3'', the output signal of the transistor 420b is
Block code KBl″~KB3″ and note code KN
The voltage value corresponds to l〃~KN4'', and this is the tone pitch voltage KV that controls the voltage-controlled variable frequency oscillator described later.
becomes. The key code Kσ supplied from the key code converter 300 is decelerated and sampled and sent to the decoder 419.
420, resulting in an output signal that is held for one period of deceleration sampling, as shown in FIG. 16, 1, m. In this case, when converting a digital signal into an analog pitch voltage KV, transistors 420a to 4201 connected to the output sides of decoders 419 and 420,
Due to the capacitance in 421a to 421f, etc. and the stray capacitance in the circuit system, the rising part of the conversion output signal (sound pitch voltage KV) rises along the time constant of CR, so there may be some distortion. However, this problem does not become a problem as it is processed at the time of allocating the sound pitch voltage KV to each channel, which will be explained next. The pulse signal SC generated in the sampling control circuit 402 is applied to each AND gate 42 of the digital-to-analog conversion circuit 403.
4a to 424h are also supplied.

The other input terminal of each AND gate 424a to 424h is connected to a channel signal B shown in FIG. 16b-1.
Since Tl to BT8 are supplied, the pulse signal SC
Only the AND gate 424 to which the channel signal synchronized with the generation timing of FIG.
Delay flip-flops 426a-426h through 5h
is memorized. Since the pulse signal SC supplied to the AND gates 424a to 424h is the final stage output signal of the shift register 411 (FIG. 14) which has counted one clock pulse more than the number of channels as described above, the channel signal BTl is supplied to the AND gates 424a-424h. ~BT8 corresponds to channel signals sequentially shifted by one. Therefore, this pulse signal SC is equal to the channel signal BTl~
This means that BT8 is decelerated to 1/8 and sampled, and this sampled channel signal BTl'
~BT8' is stored in one of the delay flip-flops 426a to 426h, and is held until the AND gates 427a to 427h are inhibited by the output signal of the inverter 417 when the next pulse signal SC is supplied. . In this case, the channel signal BTl~
The deceleration sampling of BT8 and the key code KC' is performed using the same signal, that is, the pulse signal SC, and the key code KC' supplied to the key code/pitch voltage converter 400 is based on the key code KC'. is supplied at the channel time corresponding to the assigned channel. As a result, the key code KC sampled by the sampling circuit 401! The tone pitch voltage K obtained by converting ' into an analog signal is taken in by the pulse signal SC and applied to the delay flip-flops 426a to 426h.
All that is required is to supply the signal to the channel in which it is stored. Therefore, this delay flip-flop 4
By turning on the transistors 428a to 428h connected to the output side with the output signals of 26a to 426h, the tone pitch voltage KV is output to the output terminals 429a to 429h.
It is possible to supply the pitch voltage KV only to the target channel (the channel to which the assignment processing has been performed in the channel record processor 200) via the channel recorder processor 200. In this case, AND gates 430a to 430h are provided on the output side of each delay flip-flop 426a to 426h, and each gate 430a to 430h is connected to a It is controlled by a pulse signal SOF shown in FIG. Since this pulse signal SOF is a signal in which the output portions of the first stage and the final stage of the 9-stage shift register 411 are SO'', it is set to 0'' for two channel times from the generation of the pulse signal SC. It becomes a signal. The sound pitch voltage K output from this digital-to-analog conversion circuit 403 to each channel is 0,
As shown in p, the first two channel time portion becomes an inhibited signal, and only the tone pitch voltage K which is in a stable state with the rounded portion that occurs when the tone pitch voltage K rises is completely removed is sent out. The above explanation is based on the sampling circuit 401 that decelerates and samples the key code KC' supplied from the second key code memory 302 and sequentially captures it for each channel, and the sampling circuit 401 that converts the sampled key code KC into a corresponding analog signal. High voltage K
This is a detailed explanation of the digital-to-analog conversion circuit 403 that generates the tone pitch voltage KV and supplies this pitch voltage KV to the channel to which this key code KC'' is assigned.

Channel-specific tone high voltage control section 500, musical tone forming section 600
, pitch voltage control section 700 Next, channel-specific pitch voltage control section 500, musical tone forming section 600, and pitch voltage control section 7
00 will be explained.

FIG. 17 shows a specific embodiment of the channel-by-channel tone high voltage control section 500, the tone forming section 600, and the tone pitch voltage control section 700.
0 is a sound pitch voltage control circuit 501a to 50 for each channel.
01h. The tone pitch voltage control circuit 501a in charge of the first channel operates a transistor 502 whose gate input is the key-on signal KOl output from the output terminal 271a of the key press state memory 204 shown in FIG. 12 via an inverter 517. It turns on when the '1'' output of the key-on signal KOl (a signal indicating that a key is pressed in this channel) is supplied.In this way, the key-on signal KOl is supplied to this first channel.
lCl'') is supplied, the tone pitch voltage KV corresponding to the key code KC'' assigned to this channel is supplied from the digital-to-analog conversion circuit 403 to the first channel as described above. Then, when the transistor 502 is turned on by the inverted key-on signal [1,
A resistor 503 is connected to the emitter side of this transistor 502.
504 and a capacitor 505, this differential circuit allows the differential output when the transistor 502 is turned on to be output to the inverter 50.
6 and is taken out as a positive pulse. The output signal of the inverter 506 turns on the transistor 507, and accordingly, the capacitor 508 is rapidly charged with the tone pitch voltage KV. Further, a resistor 50 with a medium resistance value is connected between both ends of this transistor 507.
A series circuit of a resistor 511 and a transistor 512 having a large resistance value are connected in parallel, and by selectively turning on transistors 510 and 512 when the transistor 507 is off, the capacitor 508 The charging time constant of the pitch voltage K is selected relative to the pitch voltage K. In addition, Nand Gate 513,
AND gates 514, 515 and OR gate 516 are used to control pitch voltage KV charged in capacitor 508 by an output signal of pitch voltage control section 700, which will be explained in detail later. The above explanation is the first
The structure of the tone pitch voltage control circuit 501a in charge of the channel section is the same as that of the tone pitch voltage control circuits 501b to 501h of the other channel sections. It has musical tone forming circuits 601a to 601h provided.

When looking at the first channel portion of the musical tone forming circuits 601a to 601h, the tone pitch voltage control circuit 5
VCO6O2 which receives the terminal potential KV' of the capacitor 508 that charges the tone pitch voltage KV provided at 01a and oscillates a sound source signal of the corresponding frequency, CF6O3 which controls this sound source signal to form a tone, and a musical tone generator. CA6O4 that controls the envelope of the signal, and these are controlled by envelope generators (EG) 605 to 607 triggered by the key-on signal KO1.
In addition, this envelope generator (EG) 605~
It goes without saying that 607 is under the control of an adjustment polyurethane provided on an operation panel (not shown). The output signal (musical tone signal) of the musical tone forming circuit 601a of the first channel configured in this way is transmitted to the mixing resistor 6.
10a to the output end 611, and this output end 6
Musical tones are generated from a speaker connected to 11, and the configuration is similar to a commonly used musical tone forming circuit. Furthermore, musical tone forming circuits 601b to 601h in charge of other channels have the same configuration, and their output signals (musical tone signals) are sent to mixing resistors 610b to 610h.
10h to an output terminal 611. The above is the configuration of the musical tone forming section 600. Next, the pitch voltage control section 700 will be explained.

This pitch voltage control section 700 is a section that controls the speed of portamento or glitsando, switches between portamento and glitsando, and controls whether or not the pitch of the musical tone signal changes during sustain. 701 is a variable resistor, and the output voltage of its slider 702 is supplied to a pitch change mode control section 900 (described later) as a speed control signal TC that controls the generation cycle of the arithmetic control pulse 0PC described above.

The output voltage of the variable resistor 701 is determined by the comparators 703, 704,
705, and is compared with reference values R, -Vr3 in each comparator 703-705. The reference values Vrl to R3 are R,>R2>R3.
The output signal of the comparator 703 is supplied to the key code shift control terminal 301 shown in FIG. 13 as a pitch voltage variable control signal. 706 is a switch for switching between portamento (P) and dalitsando (q), 707 is a switch for switching between the presence or absence of pitch change (glitsando or portamento) of the musical tone signal in the sustain state, and 708 is an OR gate.

Hereinafter, the channel-by-channel tone high voltage control section 500, musical tone forming section 600, and tone pitch voltage control section 700 having the above-described configurations will be described.
The operation will be explained in detail. First, the operation will be described when the switch 706 is switched to the portamento side (as shown) and the switch 707 is switched to the non-sustain control side (as shown).

In this state, when the sliding piece 702 of the variable resistor 701 is positioned closest to the ground side, a voltage lower than the reference value Vr3 is output, and the pitch change mode control section 900 described below outputs a voltage lower than the reference value Vr3.
is the long period calculation control pulse 0 corresponding to this low voltage.
Send PC. Each comparator 703, 704, 705 is
Since the voltage supplied from the variable resistor 702 is a signal lower than the reference value Vr3, all comparison outputs are 0.
Since the output of the comparator 703 becomes SO'', this SO'' output is supplied to the key code shift control terminal 301 shown in FIG. 13 as a pitch variable control signal. As described above, the arithmetic circuit 303 sequentially performs the above-described addition or subtraction process for each channel until the key code KC corresponding to the first operating key matches the key code KC corresponding to the second operating key. This calculation is performed every time the calculation control pulse 0PC is supplied from the pitch change mode control section 900, and in this case, the speed is extremely slow. , as described above, the key code KC' output from the second key code memory 302 rises or falls in stepwise order for each channel. The channel key code KC' is a key code in which calculation processing is performed every time an extremely long period calculation control pulse 0PC corresponding to the voltage output from the variable resistor 701 is supplied, and the pitch changes sequentially by semitone. It will be converted into KC' and output.

The key code KC' of each channel, which changes at a slow speed in this way, is sampled in the sampling circuit 4 and then sent to the digital-to-analog conversion circuit 40.
3, the sound pitch voltage control circuits 501a to 501h are converted into the corresponding sound pitch voltage K and corresponding to the channel.
is supplied to In the following description, the first channel will be described. First, in the channel processor 200, the key code KC corresponding to the second operation key is assigned to the first channel.
The output terminal 271a (the first
A key-on signal KOl is supplied from the key-on signal KOl (Fig. 2). This key-on signal KOl is a signal that becomes S11'' when the key is on, and the transistor 502 is turned on by this inverted signal r, and when this transistor 502 is turned on, a differential pulse is generated at the connection point between the capacitor 505 and the resistor 504. This differential pulse is inverted by the inverter 506 to become a positive pulse, and this positive pulse is inverted by the OR gate 51.
6 to the gate electrode of a field effect transistor 507, and this transistor 507 is momentarily turned on. During the period when the transistor 507 is on, the high tone voltage KV of the first channel supplied to the drain electrode of the transistor 507 (the first channel of the key code memory 201 of the channel processor 200 is connected to the key of the second operation key). Since the key code KC of the first operation key was stored until just before the code KC was stored, this pitch voltage K initially has a voltage value corresponding to the pitch of the first operation key.) But in this moment, 50 capacitors
8, and a musical tone signal corresponding to the terminal voltage KV', that is, corresponding to the first operating key, is generated. Further, when the key-on signal KOl of '1'' is supplied from the terminal 271a of the key press state memory 204, the input of the NAND gate 513 becomes '1''&0'', and its output becomes '12'. 512, and while the key-on signal KOl is supplied, the transistor 5
12 will continue to be held in the on state. The above-mentioned transistor 507 is turned on only at the instant of key-on, and therefore only the transistor 512 remains on thereafter. Thereafter, the pitch changes stepwise at a slow cycle from the voltage value corresponding to the pitch of the first operating key supplied via the digital-to-analog conversion circuit 403 to the voltage value corresponding to the pitch of the second operating key. Voltage K is applied to capacitor 508 via high resistance 511.
is charged. Therefore, the charging time constant in this case becomes extremely large, and the pitch voltage K that changes stepwise becomes the pitch voltage KV' that changes continuously and is supplied to the musical tone forming circuit 601a. As a result, a portamento effect is obtained in which the pitch of the first operating key changes continuously and slowly at the pitch of the second operating key. In this case, the second
When the operation key is released, the key-on signal KO changes from ゞ1'' to ゝ0〃, so the input of the NAND gate 513 changes to ゞ1''S1'' and its output becomes ゞ0.
''.As a result, charging to the capacitor 508 is stopped at the same time as the key is released, and no portamento effect can be obtained in the sustain section.
When 07 is switched to the sustain control side (opposite to the illustration), the o'' signal is supplied to the NAND gate 513, and the transistor 512 is turned on even when the key is released when the inverted key-on signal becomes S11''. If this condition continues, a portamento effect will also be obtained for the sustain section. Next, when the slider 702 of the variable resistor 701 is slid slightly upward to output a voltage greater than the reference value R3 and smaller than the reference value R2, the pitch change mode is controlled accordingly. The cycle of the calculation control pulse 0PC output from the section 900 becomes faster, the calculation cycle also becomes faster, and the change in the pitch voltage K also becomes faster.

On the other hand, since the variable resistor 702 outputs a voltage equal to or higher than the reference value Vr3, the output of the comparator 705 becomes
becomes. This S11'' signal is supplied to the AND gate 515, and the condition of the AND gate 515 is satisfied by the '1'' output of the NAND gate 513, which is always output during the supply period of the key-on signal KO. This and gate 515
The S1'' output turns on the transistor 510 and charges the capacitor 508 with the tone pitch voltage KV that changes at a relatively fast speed through the medium resistor 509.The charging voltage KV' of the capacitor 508 is .configuration circuit 601
A is converted into a musical tone signal, and a musical tone having a portamento effect that changes continuously at a relatively fast speed is obtained from a speaker (not shown). In this case, the reason why the transistor 510 is selected and turned on so as to lower the charging resistance value when the tone pitch voltage KV changes quickly is because the tone pitch voltage KV changes relatively quickly when the charging time constant is large. This is because they become unable to keep up with changes. Next, when the slider 702 of the variable resistor 701 is slid to output an even higher voltage, the outputs of the comparators 704 and 705 are both S
It becomes 11″.

Then, the S1'' output of this comparator 704 is supplied to the AND gate 514 via the OR gate 708, and a match with the NAND gate 513 output when the key-on signal KOl is supplied is determined, and the S1'' output is supplied to the AND gate 514 through the OR gate 708. The transistor 507 is turned on via the .
As a result, when the tone pitch voltage K changes quickly, this tone pitch voltage K passes through the transistor 507 to the capacitor 508.
is charged directly to produce a fast-changing, gritsand-like portamento effect. Next, the slider 7 of the variable resistor 701
When the output voltage is further increased by controlling 02 to the upper side, the pitch change mode control section 900 outputs an arithmetic control pulse 0PC with an extremely fast cycle.

However, when such a high voltage is output from the variable resistor 701, this voltage becomes higher than the reference value Vrl, and accordingly, the output of the comparator 703 changes from ゞ0'' to ゞ1''. . In this case, the output signal of the comparator 703 is supplied to the key code shift control terminal 301 of the arithmetic circuit 303 shown in FIG. 13, and becomes a pitch voltage variable control signal. Therefore, when the output voltage of the variable resistor 701 is controlled to be higher than the reference value Vr, the output signal of the comparator 703 becomes "1" and the operation of the arithmetic circuit 303 is stopped and normal operation is resumed. Control so that The above operation is the operation when obtaining the portamento effect.

Next, the operation for obtaining the glissand effect will be explained.

To obtain the glissand effect, the switch 706 is turned in the opposite direction as shown to supply the S1'' signal to the OR gate 708.

When a '1'' signal is supplied to the OR gate 708, this
'' signal is constantly supplied to the AND gate 514. On the other hand, the output of the NAND gate 513, which is the other input of the AND gate 514, is a key-on signal indicating that the key assigned to the first channel is pressed. Signal KO,
is supplied, the state is always S1'' as described above. Therefore, the AND gate 514 receives the key-on signal K.
When Ol is supplied, the condition is always satisfied and a '1'' signal is obtained, and this '1'' signal turns on the transistor 507 via the OR gate 516.
As a result, as long as the output of the variable resistor 701 is equal to or less than the reference value Vrl, any value, that is, if the change in the tone pitch voltage KV changes at a speed less than the speed determined by the reference value Vrl, the tone pitch is always transmitted through the transistor 507. The voltage charging capacitor 508 is directly charged, and the charging voltage KV' of the capacitor 508 is changed stepwise in response to the stepwise change in the pitch voltage K. Therefore,
The musical tone forming circuit 601a outputs a musical tone signal in which the pitch changes in a stepwise manner. For example, a musical tone signal in which the pitch changes in a stepwise manner is generated, similar to when the keys of a piano are sequentially operated. You will be able to obtain the desired results. It goes without saying that when the output of the variable resistor 701 is made equal to or higher than the reference value Vr, the arithmetic processing of the arithmetic circuit 303 is stopped and normal operation resumes, as in the case of portamento described above.
Furthermore, when the switch 707 is switched to sustain control (opposite to the illustration), the "O" signal is always supplied to the NAND gate 513, and during sustain, the '1' output of this NAND gate 513 and the switch 706 The condition of the AND gate 514 is established by the ``1'' signal supplied via the OR gate 708, and the ``1''
In order for the transistor 507 to remain on at the output,
Gritsand effect can now be obtained even during sustain. Also, a variable resistor 7 as an output voltage regulator
01 has both the speed control of portamento or glitzando and the on/off control of variable pitch control (gritsando or portamento), so it has fewer operating parts and is relatively easy to operate even for beginners. This is an extremely effective method for achieving this. In this case, it goes without saying that the reference value Vrl needs to be set to a voltage value that changes quickly enough to prevent the portamento glissando effect from being obtained. Pitch change mode control section 900 Next, pitch change mode control section 90
0 will be explained.

FIG. 18 shows a specific embodiment of the pitch change mode control section 900, which has voltage controlled oscillators 901a to 901h for each channel. Each of the voltage controlled oscillators 901a to 901h has a characteristic that its output frequency varies linearly in response to the input voltage, and switches 902a to 902a for selecting a pitch change mode are provided on the input side of each of the voltage controlled oscillators 901a to 901h. 902h is provided. and,
The fixed contacts a of each of the switches 902a to 902h are connected to the common DC power supply +, and the fixed contacts b of each of the switches 902a to 902h are connected to the output terminals 518a to 518a of the channel-specific sound high voltage control section 500.
518h (FIG. 17), and receives the tone pitch voltage KV' for each channel as an input signal. Furthermore, the fixed contact c inputs the sound pitch voltage KV' for each channel, and the sound pitch voltage KV' has a symmetrical inverse change characteristic, that is, as the input signal increases, the output signal corresponds to the increase. Characteristic conversion circuits 903a to 90 with decreasing characteristics
They are respectively connected to the output terminals of 3h. Further, the oscillation frequency of the voltage controlled oscillators 901a to 901h is changed by the speed control signal TC commonly supplied from the variable resistor 701 (17th F) of the pitch voltage control section 700. ing. Each input voltage and a common speed control signal T from the outside as shown in
The output signals of voltage-controlled oscillators 901a to 901h whose oscillation frequencies are variably controlled by C are differentiated in synchronous differentiating circuits 904a to 904h, respectively, and the differential signals are outputted to each AND gate 905a to 905h as shown in FIG. Coincidence with the timing signals BTl to BT8 shown in Q is determined, and this coincidence output signal is supplied to the speed control terminal 305 of the key code converting section 300 as an arithmetic control pulse 0PC via an OR gate 906. Next, the operation of the pitch change mode control section 900 having the above configuration will be explained.

When the switches 902a to 902h of each channel are connected to the fixed contact a as shown in FIG. 18, a constant voltage +V is supplied to each voltage controlled oscillator 901a to 901h, respectively. 901
h performs oscillation with a period corresponding to this input voltage +V.
Each oscillation output signal is transmitted to each synchronous differentiator circuit 904a to 904.
At h, the signal is differentiated into pulse widths corresponding to the first to eighth channel times in synchronization with the clock pulse φ, and each of the differentiated signals is supplied to each AND gate 905a to 905h, respectively. In this case, timing signals BTl to BT8 synchronized with each channel time are supplied to the other input terminals of each AND gate 905a to 905h, and each time the two match, an arithmetic control pulse 0PC synchronized with each channel time is supplied. is supplied to the speed control terminal 305 via the OR gate 906. Therefore, as described above, each time the arithmetic control pulse 0PC is supplied, the key code converter 300 performs an operation of addition or subtraction to the key code KC of the channel to which the arithmetic control pulse 0PC is supplied, thereby converting the portamento or Change the key code KC for Gritsando performance. In this case, voltage controlled oscillators 901a to 901h are switched to switches 902a to 902h.
Since oscillation is performed with a constant period using voltage + as an input voltage, the generation period of the calculation control pulse 0PC is also constant, and accordingly, the calculation period of the calculation circuit 303 is also constant, and the pitch is increased. The voltage K changes linearly as shown in FIG. 4B. Therefore, in this case, a portamento or glitsando effect sound in which the pitch changes linearly from the first operating key pitch to the second operating key pitch is obtained, and the pitch change The mode becomes linear. In this case, the oscillation frequency of the voltage controlled oscillators 901a to 901h is determined by the variable resistor 701 of the pitch voltage control section 700.
When the slider 702 of the variable resistor 701 is moved to the power supply +V side to output a high voltage, each oscillator 901a The oscillation frequency of ~901h also increases, and the pitch change speed of portamento and glissando increases. Next, each switch 902a~
When 902h is connected to fixed contact b, the sound high voltage KV' of each channel is changed to each voltage controlled oscillator 901a to 901h
will be supplied to each.

As a result, each voltage-controlled oscillator 901a to 901h oscillates at a frequency corresponding to each tone pitch voltage KV', and this oscillation output is synchronously differentiated, and the AND gates 905a to 901h
After a match with timing signals BT and BT8 is determined in 5h, the signal is supplied to the arithmetic circuit 303 via an OR gate 906 as an arithmetic control pulse 0PC. Therefore, in this case, when the pitch voltage KV' is low, the oscillation frequency of each voltage-controlled oscillator 901a to 901h during a portamento or glissando performance is low, and the pitch voltage KV' becomes high. As a result, its oscillation frequency also increases. Therefore, since the frequency of the calculation control pulse 0PC increases linearly with the passage of time, the pitch change in portamento or grissando performance in this case will change with the exponential characteristic shown in Figure 4c. . It goes without saying that in this case as well, the speed of pitch change is adjusted by the output signal of the variable resistor 701, as in the case described above. Next, when each switch 902a-902h is connected to fixed contact c, the output signal of each characteristic conversion circuit 903a-903h is supplied to voltage-controlled oscillation circuit 901a-901b, respectively.

In this case, the characteristic conversion circuits 903a to 903h, which receive the tone pitch voltage KV' of each channel as input, are configured with emitter grounding circuits, for example, and have inverse change characteristics such that the output voltage decreases when the input voltage increases. is converting. Therefore, the oscillation frequency of the voltage controlled oscillators 901a to 901h decreases as the pitch voltage KV' increases. As a result, the output signals of the voltage controlled oscillators 901a to 901h are synchronously differentiated, and the timing signals BTl to B
The period of the calculation control pulse 0PC, which is generated at each channel time in accordance with T8, becomes longer as the pitch rises, and accordingly, the pitch changes when playing portamento or gris sando. It changes with the integral characteristic shown in FIG. 4A. In this case as well, the speed control of the pitch change is controlled by the variable resistor 7.
Needless to say, this is carried out by 01. In addition,
In the above explanation, a case was explained in which a key coater configured to encode and extract key information was used, but the present invention is not limited to this. May be used.

Furthermore, although each channel is driven in the same pitch change mode, the positions of the switches 902a to 902h may be made different for each channel, thereby making the pitch change mode different for each tone generation series. As explained above, the present invention provides a pitch change that controls the pitch change mode of the pitch change section that changes the pitch from the pitch of the previously pressed key to the pitch of the subsequently pressed key. Since a plurality of mode setting circuits are provided and the output signal of the pitch change mode setting circuit selected by the pitch change mode selection switch is supplied to the pitch change section, the sound during portamento or glissando performance is The high variation mode can be changed in various ways, and this has an excellent effect of enriching musical expression.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram of the main parts of an electronic musical instrument having a conventional portamento device, Fig. 2 is a waveform diagram showing changes in the terminal voltage of the capacitor shown in Fig. 1, and Fig. 3 is an electronic musical instrument according to the present invention. 4 is a waveform diagram showing changes in the terminal voltage of the capacitor shown in FIG. 3; FIG. 5 is an overall configuration diagram showing another embodiment of the electronic musical instrument according to the present invention; FIG. 6 is a diagram explaining the representation diagram of the logic element used in this embodiment, FIG. 7 is a detailed circuit diagram showing an example of the timing signal generation section shown in FIG. 5, and FIG. 8 is a diagram explaining the timing signal generation section shown in FIG. 7. A waveform diagram showing various timing pulses generated in the signal generating section, FIG. 9 is the same as the waveform diagram shown in FIG.
A detailed circuit diagram showing an example of the key code memory, FIG. 10 is a detailed circuit diagram showing an example of the key-on/off detection circuit shown in FIG. 5, and FIG. 11 is a detailed circuit diagram showing an example of the truncate circuit shown in FIG. 5. 12 is a detailed circuit diagram showing an example of the key press state memory shown in FIG. 5, and FIG. 13 is a detailed circuit diagram showing an example of the comparison circuit, arithmetic circuit, and second key code memory shown in FIG. , FIG. 14 is a detailed circuit diagram showing an example of the sampling control circuit shown in FIG. 5, and FIG. 15 is a detailed circuit diagram showing an example of the sampling control circuit shown in FIG.
FIG. 16 is a detailed circuit diagram showing an example of the sampling circuit and analog-to-digital conversion circuit shown in the figure. FIG.
The figure is a detailed circuit diagram showing an example of the channel-specific tone high voltage control section, musical tone forming section, and tone pitch voltage control section shown in FIG. 5, and FIG. 18 is a detailed circuit diagram of the pitch change mode control section 900 shown in FIG. 5. It is a circuit diagram. 2... Pitch change part, 14, 15, 16...
... Pitch change mode setting circuit, 17 ... Pitch change mode selection switch, 100 ... Key coater, 200 ... Channel processor, 300 ...
...Key code conversion section, 302...Second
Key code memory, 303... Arithmetic circuit, 30
4... Comparison circuit, 400... Key code tone pitch voltage conversion section, 501a to 501h... Tone pitch voltage control circuit, 600... Musical tone forming section , 60
1a to 601h...music tone forming circuit, 700...
....Tone pitch voltage control section, 800 ....timing signal generation section, 900 ....pitch change mode control section, 901a to 901h ....voltage controlled oscillator, 902a to 902h... Pitch change mode selection switch, 903a to 903h... Characteristic converter, 904a to 904h... Synchronous differentiation circuit, 90
5a-905h...and gate, 906...
...or gate.

Claims (1)

[Claims] 1. A pitch changing section that changes the pitch of the generated musical tone continuously or stepwise from a first pitch to a second pitch, and setting the pitch change characteristics of the generated musical tone pitch to different states. a plurality of pitch change mode setting circuits, and a selection switch means for selecting one of the plurality of pitch change mode setting circuits; An electronic musical instrument capable of performing a portamento performance effect or a glissando performance effect corresponding to the selected pitch change mode by controlling the part.