JPS5937586B2 - Souhogatadenkaikoukasoshiyuusekikairosouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary field-effect element integrated circuit device, and in particular to a random access memory (hereinafter referred to as ``calculator'') that is improved so that it can be used in electronic desktop calculators (hereinafter referred to as ``calculators'').
The present invention relates to a complementary field effect element integrated circuit device having a "RAM").

RAMs using complementary MOS field effect transistors (hereinafter referred to as CMOS) are in practical use, but as is well known, CMOS-RAMs are low-power and cannot be used after the system power is turned off. It is also used as a non-volatile RAM by using it for battery backup.

However, this kind of RAM is designed for high speed and is used in large computers, etc., so it is very expensive, and also requires a separate power supply system, making it unsuitable for use in calculators, etc. It is. In systems such as hand-held programmable calculators, it would be extremely advantageous if the program or written data could be prevented from being lost even after the power to the system is turned off. , and the added value increases, but non-volatile RAM is required to realize this. In this case, FAMOS, etc., which erase written data due to ultraviolet rays, are incompatible, and CM, which is backed up by a battery even after the system power is turned off, is incompatible.
OS-RAM is compatible. However, the power supply for general-purpose CMOS-RAM is designed with the lowest voltage possible, around 1 to 2 volts, in order to reduce power consumption, but it is set to 5 volts to make it TTL compatible to speed it up. Usually, the lowest possible threshold voltage is adopted to achieve this, and maximum effort is also made to increase the writing and reading speeds so as to be compatible with as many systems as possible. For this reason, manufacturing yield is also poor and costs are high. Needless to say, such an expensive RA is required in systems such as calculators.
M is unnecessary, and in order to manufacture the system itself at the lowest cost, it is common to select a threshold voltage that can be controlled most naturally (approximately 2.5 volts), so the power supply voltage It is also common to select 5 to 6 volts. It is very difficult to adapt such a system to the above-mentioned RAM. However, if we successfully match this difficult-to-match system with RAM,
It could be effectively used in inexpensive calculators, etc. Therefore, the main object of this invention is to provide an improved R
An object of the present invention is to provide a complementary field effect element integrated circuit device having AM.

Other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings. Briefly, a random access memory consisting of a P-channel field effect element and an N-channel field effect element and a system are formed on one chip, and the power supply for the system is separated from the power supply for the random access memory. It is characterized by having been configured.

FIG. 1 is a block diagram of a system according to an embodiment of the present invention.

The notable features of this invention are CMOS-RAM and CM
The system S other than the OS-RAM is configured in one chip CH. In addition, in order to make the CMOS-RAM non-volatile, the system S and the CMOS-RAM
The main reason for this is that the power supply was made separate. That is, the external power P is directly applied to the CMOS-RAM, while it is applied to the system S via the switch SW. Of course, this switch SW is closed when in use. On the other hand, power is constantly supplied to the CMOS-RAM to prevent the memory contents from volatilizing. In this way, if RAM is built into one chip and its power supply system is separated, the threshold voltages of system S and RAM will be almost the same due to the nature of being integrated into one chip, and the above-mentioned input/output compatibility will be achieved. There are no problems with R, and the speed is compatible with the system.
(There is no need to leave too much or too little margin in the frequency margin.) Figure 2 shows a self-refresh CMOS-RAM, which is an example of the CMOS-RAM in Figure 1. It is.

Points to note in this example are as follows. In other words, when the power of the system S other than the RAM is completely off, even if the level of the read/write line (data line) l is open, there will be no current for sinking from the outside, and therefore unexpected No state is written. However, there is a high possibility that an unexpected state will be written at each instant (or during a transition period) when the power of the system S other than the RAM is turned on and off. FIG. 3 is an example for solving this problem. That is, FIG. 3 shows the RAM of FIG.
A decoder (not shown) for forming the digit selection signal Di.

Instead, it shows a circuit that further logically processes the output of the decoder (decoder output shown in FIG. 3), and shows the digit selection signal Di generation circuit as a whole. In FIG. 3, power supplies for systems other than RAM. , 8 are used. First, at the moment the power is turned on (the moment the switch SW is closed), the level of the point N1 becomes the level of the power supply voltage 8 due to the action of the capacitor C1. These 8 levels are NAN
D is given to one input of gate G. NAND gate G
The decoder output is given to the other input. By doing so, the levels of Di and Di can be uniquely determined, and reading and writing can be prohibited. After time has passed and normal operation starts, point N1 becomes VO level, the NAND gate is activated, and the digit selection signal Di is activated only by the level of other decoder outputs.
, Di can be determined. Similarly, since point N1 is discharged to the Vs level at the instant the power is turned off, reading and writing can also be prohibited. As explained above, according to the present invention, by integrating CMOS-RAM and other systems into one chip, an inexpensive system with non-volatile RAM can be obtained, which can also be used in hand-held calculators, etc. Effects such as:

[Brief explanation of drawings]

FIG. 1 shows a schematic diagram of a system according to an embodiment of the present invention. FIG. 2 is a circuit diagram of an example of the CMOS-RAM shown in FIG. 1. FIG. 3 shows the digit selection signal Di, Di generation circuit of FIG. In the figure, S indicates a system other than CMOS-RAM, P indicates a power supply, and SW indicates a switch.

Claims (1)

[Claims] 1 A random access memory consisting of a P-channel field effect element and an N-channel field effect element and a system for performing electronic logic processing such as arithmetic processing are formed as one integrated circuit, and the random access memory and the Complementary field effect element integrated circuit device with separate energizing power supply from the system.